JP2001255856A - Driving power source for liquid crystal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving power source for liquid crystal capable of reducing power consumption without lowering the display state of a liquid crystal display. SOLUTION: When the liquid crystal alternating signal concerned with the display of a liquid crystal display is inputted to a power control signal generating part 14, a power control signal having prescribed widths T at fronts and rears of rising and falling edges of this liquid crystal alternating signal is generated to be supplied to voltage-followers 131 to 134. Then, the voltage-followers 131 to 134 are in normal operating states when the power control signal is at 'H' level and the voltage-followers are in operating states in which their powers are at low power consumption when the power control signal is at 'L' level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving power supply for a liquid crystal used in a liquid crystal display. The present invention relates to a liquid crystal drive power supply to be supplied.

[0002]

2. Description of the Related Art Conventionally, as an example of this type of liquid crystal driving power supply, as shown in FIG. 6, a predetermined voltage is divided by resistors R1 to R5 connected in series, and each divided voltage is
, And supplies the output voltages V1 to V4 to a driver of a liquid crystal display (not shown) as a drive voltage thereof. The resistors R1 to R5 have the same resistance value as the resistors R1, R2, R4, and R5. If the resistance value is R, the resistance R3 is n times n times the resistance value R.
The resistance value is R.

[0003]

By the way, the buffer 1
In (4), since the driving current always flows to the driver during the operation of the liquid crystal display, the current consumption in the buffers (1) to (4) tends to increase as the size of the liquid crystal display increases. This hinders a reduction in the power consumption of the liquid crystal drive power supply, and a solution has been desired.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal drive power supply that reduces power consumption without lowering the display state of a liquid crystal display.

[0005]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, the inventions according to claims 1 to 3 are configured as follows.

That is, according to the first aspect of the present invention, a liquid crystal drive power supply for dividing a predetermined voltage by N resistors and outputting each divided voltage as a drive voltage for a driver of a liquid crystal display via each buffer. In each of the buffers, the driving capability can be controlled in accordance with an external power control signal, and the buffer generates the power control signal based on a liquid crystal alternating signal applied to the display of the liquid crystal display. ,
A power control signal generating means for outputting the power control signal to each of the buffers is provided.

Here, the liquid crystal alternating signal has the same properties as the liquid crystal alternating signal, and is a concept including a frame signal related to display on a liquid crystal display.

According to a second aspect of the present invention, in the liquid crystal driving power supply according to the first aspect, the power control signal generated by the power control signal generating means is before and after the rising and falling of the liquid crystal alternating signal. And has a predetermined width.

According to a third aspect of the present invention, in the liquid crystal driving power supply according to the first or second aspect, the power control signal generating means detects a rise and a fall of the liquid crystal alternating signal, respectively. An edge detector, and a first count is performed for a period from a rise to a fall of the liquid crystal alternating signal detected by the edge detector, and after the first count is completed, the edge detector detects the liquid crystal. Each time a rising or falling edge of the AC signal is detected, a counter unit that performs a second count from a predetermined initial value based on the detection, and counts the count value after the first count of the counter unit is completed. A latch unit for storing, and comparing a count value of the counter unit by a second count with a count value stored in the latch unit, and calculating the count value of the second count by the latch unit. When the count value is exceeded, a comparison unit that outputs the fact and a pulse generation unit that generates a pulse of a predetermined width based on the detection when the edge detection unit detects the rising or falling of the liquid crystal alternating signal. And a power control signal generator for generating the power control signal based on the output of the comparator and the pulse of the pulse signal generator.

In the present invention having such a configuration, the power control signal generating means generates the power control signal based on the liquid crystal alternating signal applied to the display of the liquid crystal display, and the power control signal is stored in each buffer. Added output.
For this reason, it is possible to control the driving capability of each buffer within a range in which the display state of the liquid crystal display is acceptable, and it is possible to reduce the power consumption without lowering the display state of the liquid crystal display.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

The configuration of the first embodiment of the liquid crystal drive power supply of the present invention will be described with reference to the circuit diagram of FIG.

As shown in FIG. 1, the liquid crystal drive power supply according to the first embodiment is a switching regulator 11.
, A voltage regulator 12, a driver drive voltage generator 13 for generating a drive voltage for a driver of a monochrome or color liquid crystal display, and a power control signal generator 14, which are integrated on a semiconductor substrate ( (One chip) and integrated circuit.

As shown in FIG. 1, the switching regulator 11 includes at least a switch transistor 111 composed of a MOS transistor, a PWM control circuit 112, and an electronic volume control unit 113.

The PWM control circuit 112 compares the DC output voltage VOUT1 output from the output terminal 21 with a triangular wave, and controls on / off of the switch transistor 111 with an on / off signal obtained according to the comparison result.
As a result, the DC output voltage VOUT1 is stabilized at a predetermined value.

The electronic volume control unit 113 includes control data DA for changing a resistance value of an electronic volume 122 described later.
When the TA is received from the outside, the resistance value of the electronic volume 122 is changed based on the control data DATA.

As shown in FIG. 1, the voltage regulator 12 includes a switch transistor 121 composed of a MOS transistor, an electronic volume 122, a resistor R11, and a resistor between the output terminal 21 of the DC output voltage VOUT1 and the ground.
And a resistor R12 are connected in series. Then, the comparator 123 is connected to the electronic volume 122 and the resistor R1.
1 (a divided voltage of the DC output voltage VOUT1) is compared with a reference voltage, and the switch transistor 121 is turned on / off by an on / off signal corresponding to the comparison result, thereby outputting. The DC output voltage VOUT2 output to the terminal 22 is stabilized at a predetermined value. The resistance of the electronic volume 122 can be changed electronically based on control data from the electronic volume control unit 113.

The driver drive voltage generator 13 is provided with a drive voltage V1 supplied to a driver of a liquid crystal display (not shown).
To V4, for example, resistors R1 to R5 are connected in series between the output terminal 22 of the DC output voltage VOUT2 of the voltage regulator 12 and the ground, and the DC output voltage VOUT2 is divided by the resistors R1 to R5. It has become.

A common connection point between the resistors R1 and R2 is connected to the output terminal 23 via a voltage follower 131, and a common connection point between the resistors R2 and R3 is connected to the output terminal 24 via a voltage follower 132. ing.
Further, the common connection point of the resistors R3 and R4 is connected to the output terminal 25 via the voltage follower 133, and the common connection point of the resistors R4 and R5 is connected to the voltage follower 13
4 is connected to an output terminal 26.

The resistors R1 to R5 are resistors R1, R2, R
The resistance values of R4 and R5 are the same, and when this resistance value is R, the resistance R3 has a resistance value of nR which is n times the resistance value R. In this example, the number of the resistors R1 to R5 is five, but the number is not limited thereto. The resistance R3
May be replaced with the resistor R2 or the resistor R4 as well as the position in FIG.

Each of the voltage followers 131 to 134 functions as a buffer, and has a drive capability that can be controlled in accordance with a power control signal, which will be described later, from outside, and has a control terminal for receiving the power control signal.

The power control signal generator 14 generates the above-mentioned power control signal based on the liquid crystal alternating signal applied to the display of the liquid crystal display, whereby the driver is controlled so that the display state of the liquid crystal display is within an allowable range. The power consumption of the voltage followers 131 to 134 of the drive voltage generator 13 is reduced.

That is, the power control signal generation unit 14
When a liquid crystal alternating signal as shown in FIG. 2A is input, a power having a predetermined width T before and after the rising and falling edges of the liquid crystal alternating signal as shown in FIG. A control signal is generated. The power control signal is supplied to the voltage followers 131 to 134. When the control signal is at the “H” level, the voltage followers 131 to 134 are in a normal operation state, and when the control signal is at the “L” level, the voltage followers are driven. 131
１３４134 are designed to be in an operation state of low power consumption.

The power control signal generating section 14 uses a liquid crystal alternation signal for display on a liquid crystal display as an input signal, but instead provides a display having the same properties as the liquid crystal alternation signal. Such a frame signal described later may be used, and the frame signal described later can be replaced with a liquid crystal alternating signal.

Next, a specific configuration of the power control signal generator 14 will be described with reference to the block diagram of FIG.

As shown in FIG. 3, the power control signal generator 14 includes a frame counter 141 and an AND gate 14.
2, a frame length counter 143, a frame length storage latch 144, a comparator 145, a frame edge detector 146, and a power control signal generator 147.

The frame counter 141 counts the number of frame signals FRAM related to the display of the liquid crystal display, and based on the frame signal FRAM, a clock capture signal S1 for capturing a clock CLOCK to the frame length counter 143. Is generated and output to the AND gate 142, and an initial value change signal S2 for setting the initial value of the frame length counter 143 to "0" or "m" is generated to generate the frame length counter 14
3 is output.

The frame edge detecting section 146 receives the frame signal FRAM and the clock CLOCK, and resets the counting operation of the frame length counter 143 at each rising and falling edge of the frame signal FRAM based on the input. Is generated and output to the frame length counter 143, and at the timing of each edge thereof, a frame edge pulse S4 having a width n times the pulse width of the clock CLOCK is generated and output to the power control signal generator 147. ing.

The frame length counter 143 counts the period from the rise to the fall of the frame signal FRAM when the clock fetch signal S1 becomes "H" level, and the count value x after the completion of the counting is the frame length storage latch. 144. After the initial value change signal S2 goes to the “H” level and the count value x is stored in the frame length storage latch 144, the frame length counter 143 sets the preset initial value every time the reset pulse S3 occurs. The counting is started from m.

The comparator 145 compares the count value when the frame length counter 143 starts counting from the initial value m with the count value x already stored in the frame length storage latch 144, and counts the frame length counter 143. When the numerical value becomes (x−m) and the timing coincides with the count value x stored in the frame length storage latch 144, that fact is output.

The power control signal generator 147 outputs the output from the comparator 145 and the frame edge detector 146
And outputs a power control signal S5 based on the frame edge pulse S4 output from the controller.

Next, the operation of the first embodiment configured as described above will be described with reference to FIGS.

As shown in FIG. 1, the DC output voltage VOUT2 of the voltage regulator 12 is divided by resistors R1 to R5.
The output voltage V1 is applied to the output terminals 23 to 26 through 1-134.
ＶV4. Further, the output voltages V1 to V1
V4 is supplied to a driver of a liquid crystal display (not shown).

On the other hand, the power control signal generator 14
When a liquid crystal alternating signal as shown in FIG. 2A is input, a power control signal as shown in FIG. 2B is generated based on the liquid crystal alternating signal. The power control signal is supplied to the voltage followers 131 to 134, and when the control signal is at “H” level, the voltage followers 131 to
4 is in a normal operation state, and the voltage followers 131 to 134 are in an operation state in which power consumption is low when the control signal is at the “L” level.

Next, the operation of the power control signal generator 14 will be described with reference to FIGS.

When a frame signal FRAM as shown in FIG. 4B is input to the frame counter 141, the frame counter 141 starts the frame signal FRAM at its rising edge.
The number of RAMs is counted. Frame edge detector 146
Detects a rising edge and a falling edge of the frame signal FRAM, and resets the counting operation of the frame length counter 143 based on the detection.
3 is generated as shown in FIG. 4 (F), and this is output to the frame length counter 143. Further, the frame edge detecting section 146 detects each rising edge and falling edge of the frame signal FRAM, and generates and outputs a frame edge pulse S4 having a width n times the pulse width of the clock CLOCK at the timing of this detection ( (See FIG. 4H).

Now, at time t1, the frame signal F
When the RAM rises, the clock capture signal S1 output from the frame counter 141 changes from “L” level to “H” level at the rising timing as shown in FIG. 4C. Therefore, the clock CL
The OCK is taken into the frame length counter 143 via the AND gate 142 and can be counted.

At this time, the frame edge detector 14
6 generates a reset pulse S3 as shown in FIG. 4 (F), thereby resetting the frame length counter 143 and setting its initial value to 0. When the reset is completed, the frame length counter 143 starts counting the clock CLOCK from the initial value of 0. Thereafter, at time t2, the frame signal FRAM falls, and when this is detected by the frame edge detector 146, the count value x of the frame length counter 143 at this time is taken into the frame length latch 144, and the frame length is latched by the reset pulse S3. The counter 143 is reset.

At time t3, as shown in FIG. 4B, when the frame signal FRAM rises, the initial value setting signal S2 output from the frame counter 141 at the rising timing is shown in FIG. 4D. Thus, the level changes from the “L” level to the “H” level. At this timing, an initial value m is set in the frame length counter 143, and the frame length counter 143 is reset by a reset pulse S3 from the frame edge detector 146.

After the reset, the frame length counter 143 starts counting the clock CLOCK from the initial value m. The count value of the frame length counter 143 is compared by the comparator 145 with the count value x stored in the frame length storage latch 144. At time t4, when the count value of the frame length counter 143 becomes (x−m) and matches the count value x stored in the frame length storage latch 144, the output of the comparator 145 becomes
As shown in FIG. 4G, the level changes from “L” level to “H” level. Thereby, the power control signal generator 147
4 changes from "L" level to "H" level as shown in FIG. 4 (I).

Thereafter, at time t5, as shown in FIG. 4B, when the frame signal FRAM falls, the frame edge detection unit 146 causes the frame signal FRAM to fall.
4 (F) is detected by this detection.
As shown in (H), a reset pulse S3 and a frame edge pulse S4 are output. The reset pulse S3
Resets the frame length counter 143,
The frame length counter 143 starts counting the clock CLOCK from the initial value m.

At time t6, as shown in FIG. 4H, when the frame edge pulse S4 output from the frame edge detector 146 changes from the "H" level to the "L" level, as shown in FIG. As shown, the power control signal S5 output from the power control signal generation circuit 147 changes from “H” level to “L” level.

Thereafter, at time t7, when the count value of the frame length counter 143 reaches (x−m), the output of the comparator 145 changes from “L” level to “H” level as shown in FIG. . Thereby, the power control signal S5 output from the power control signal generator 147
Changes from the "L" level to the "H" level as shown in FIG.

Subsequently, at time t8, FIG.
When the frame signal FRAM signal rises as shown in FIG.
The rising edge of the RAM is detected, and the detection results in FIG.
(F) As shown in (H), the reset pulse S3 and the frame edge pulse S4 change. When the frame length counter 143 is reset by the reset pulse S3, the frame length counter 143 sets the clock CLOCK.
Is started from the initial value m.

At time t9, as shown in FIG. 4H, when the frame edge pulse S4 output from the frame edge detecting section 146 changes from "H" level to "L" level, the power control signal generating section 147 4 changes from "H" level to "L" level as shown in FIG. 4 (I).

By repeating such operations, the power control signal S5 output from the power control signal generator 147 has a predetermined width T before and after the rising and falling edges of the frame signal FRAM. (See FIG. 4 (I)).

As described above, the liquid crystal drive power supply according to the first embodiment generates a power control signal based on a liquid crystal alternating signal or a frame signal applied to the display of the liquid crystal display, and generates the power control signal. To voltage followers 131 to 134. Therefore, when the power control signal is at the “H” level, the voltage followers 131 to 134 are in a normal operation state, and when the power control signal is at the “L” level, the voltage followers 131 to 134 are in the normal operation state.
Reference numeral 134 denotes an operation state where power consumption is low. Therefore, the voltage follower 13 is set within a range where the display state of the liquid crystal display is acceptable or within a range where the display state is not reduced.
A reduction in power consumption of 1 to 134 can be realized.

In the liquid crystal drive power supply according to the first embodiment, the switching regulator 11, the voltage regulator 12, the driver drive voltage generator 13, and the power control signal generator 14 are integrated on a semiconductor substrate to form an integrated circuit. As a result, the mounting area is reduced as compared with the case where the driver driving voltage generator 13 and the like are individually configured, so that the overall size can be reduced.

Next, the configuration of a liquid crystal drive power supply according to a second embodiment of the present invention will be described with reference to the circuit diagram of FIG.

As shown in FIG. 5, the liquid crystal drive power supply according to the second embodiment is provided at both ends of the resistor R3 of the driver drive voltage generator 13 as shown in FIG. The adjustment terminals 27 and 28 to which an external adjustment resistor R0 for finely adjusting the brightness can be connected are connected. As the external adjustment resistor R0, a fixed resistor having a fixed resistance value, a variable resistor having a variable resistance value, or the like can be used.

The configuration of the other parts of the liquid crystal drive power supply according to the second embodiment is the same as that of the liquid crystal drive power supply of FIG. 1, and the same components are denoted by the same reference numerals. Is omitted.

As described above, in the liquid crystal driving power supply according to the second embodiment, the adjusting terminals 27 and 28 connected to both ends of the resistor R3 are provided, and the external adjusting resistor R0 can be connected thereto. And Therefore, for example, if the adjustment resistor R0 is a variable resistor, the output voltages V1 to V4 can be finely adjusted by finely adjusting the resistance value of the variable resistor, and the brightness of the display screen of the liquid crystal display device can be adjusted. Fine adjustment is possible.

In the liquid crystal drive power supply according to the second embodiment, the power consumption of the voltage followers 131 to 134 of the driver drive voltage generator 13 is reduced as in the liquid crystal drive power supply according to the first embodiment. Of course.

[0054]

As described above, according to the present invention, a power control signal is generated based on a liquid crystal alternating signal for display on a liquid crystal display, and the power control signal is output to each buffer and output. Drive ability is controlled. For this reason, it is possible to control the driving capability of each buffer within a range in which the display state of the liquid crystal display is acceptable, and it is possible to reduce the power consumption without lowering the display state of the liquid crystal display.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a liquid crystal drive power supply of the present invention.

FIG. 2 is a waveform diagram illustrating an operation of a power control signal generator shown in FIG.

FIG. 3 is a block diagram illustrating a specific configuration of a power control signal generation unit.

FIG. 4 is a waveform chart showing waveforms of respective parts of the power control signal generator shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a liquid crystal drive power supply according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional device.

[Explanation of symbols]

 R1 to R5 Dividing resistor 11 Switching regulator 12 Voltage regulator 13 Driver drive voltage generator 14 Power control signal generator 23 to 26 Output terminal 141 Frame counter 142 AND gate 143 Frame length counter 144 Frame length storage latch 145 Comparator 146 Frame edge detector 147 Power control signal generator

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H093 NA07 NA34 NC04 NC21 NC25 NC26 NC27 NC49 NC59 ND15 ND35 ND39 5C006 AC21 AF64 AF69 AF71 BB11 BC13 BC16 BC20 BF14 BF25 BF43 BF50 EB05 FA47 5C080 AA10 BB05 DD03 JJ03 JJ03

Claims (3)

[Claims] 1. A liquid crystal driving power supply which divides a predetermined voltage by N resistors and outputs each divided voltage as a driving voltage of a driver of a liquid crystal display via each buffer, wherein each of the buffers is externally supplied. The drive capability can be controlled in accordance with a power control signal, and the power control signal is generated based on a liquid crystal alternating signal applied to the display of the liquid crystal display, and the power control signal is transmitted to each of the buffers. A liquid crystal drive power supply, comprising: a power control signal generating means for outputting the power control signal to a liquid crystal display. 2. The power control signal according to claim 1, wherein the power control signal generated by the power control signal generation means has a predetermined width before and after the rise and fall of the liquid crystal alternating signal. LCD drive power supply. 3. The power control signal generating means includes: an edge detector for detecting a rising edge and a falling edge of the liquid crystal alternating signal; and a rising edge to a falling edge of the liquid crystal alternating signal detected by the edge detector. After the first count is completed, every time the edge detector detects the rising or falling of the liquid crystal alternating signal, a predetermined initial count is performed based on the detection. A counter for performing a second count from the value; a latch for storing the count after the first count of the counter is completed; and a count for the second count of the counter stored in the latch. A comparison unit that outputs a signal indicating that the count value of the second count is greater than the count value of the latch unit. A pulse generation unit that generates a pulse of a predetermined width based on the detection of the rising or falling of the liquid crystal alternating signal; and the power control based on the output of the comparison unit and the pulse of the pulse signal generation unit. 3. The liquid crystal drive power supply according to claim 1, further comprising a power control signal generator for generating a signal.