JP2001245258A - Digital video recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital video recorder by which packet data is recorded surely in a magnetic tape by correcting deviations and fluctuations from the prescribed fixed period of a packet period in packet data, in the digital video recorder for transmitting the packetized digital video signal to a video recording part through a serial bus. SOLUTION: The video recording part 1 is provided with a receiving means 6 for receiving the packetized digital video signal from the serial bus 5, period correcting means 8-11 for correcting the packet period of the received packetized digital video signal into the prescribed period and a recording means 16 for recording the packetized digital video signal having the prescribed period from the period correcting means in the magnetic tape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital video recording device.

[0002]

2. Description of the Related Art DV standard digital VTRs (digital magnetic tape recorders / reproducers) having a serial bus (digital interface) conforming to IEEE 1394 and enabling transmission and reception of high-quality digital video signals are commercially available. The heel digital VTR includes an A / D converter, supplies an analog video signal to the A / D converter, converts the analog video signal into a digital video signal, packetizes the digital video signal, and transmits the digital video signal through an IEEE 1394 serial bus. There is a commercially available digital VTR that transmits the image to a video recording unit and magnetically records the image on a magnetic tape.

[0003]

A digital VT provided with the above-mentioned A / D converter and an IEEE 1394 serial bus
If the frame frequency of the analog video signal supplied to the A / D converter of R deviates or fluctuates from the standard frequency, the video recording unit of the digital VTR uses a serial bus due to a system failure in the recording unit. However, there is a problem that the packet data of the digital video signal transmitted from the PC cannot be reliably recorded on the magnetic tape.

In view of the above, the present invention relates to a digital video recording apparatus which transmits a packetized digital video signal to a video recording unit via a serial bus, and transmits the packetized digital video signal from the serial bus to the video recording unit. The frame frequency of the digital video signal of the packet data of the digital video signal is deviated from the standard frequency or is corrected. An object of the present invention is to propose a device capable of reliably recording packet data on a magnetic tape.

[0005]

According to a first aspect of the present invention, a packetized digital video signal is transmitted through a serial bus.
In a digital video recording device configured to transmit to a video recording unit, the video recording unit includes a receiving unit that receives a packetized digital video signal from a serial bus, and a packetized digital video signal from the receiving unit. And a recording unit for recording, on the magnetic tape, a packetized digital video signal having a packet period of a predetermined constant period from the period correction unit. It is a digital video recording device.

According to the first aspect of the present invention, the receiving means receives the packetized digital video signal from the serial bus and the period correcting means converts the packetized digital video signal from the receiving means. The packet period is corrected to a predetermined constant period, and the recording unit records the packetized digital video signal having the packet period of the predetermined constant period from the period correction unit on the magnetic tape.

[0007] A second aspect of the present invention is the first aspect of the present invention, wherein:
The period correction means includes a FIFO memory to which a packetized digital video signal from the serial bus is supplied, and a frame synchronization detection means for detecting a frame synchronization signal included in the packetized digital video signal from the serial bus. And timing signal generating means for generating a timing signal indicating a standard generation timing of each packet generated after the frame synchronization signal, based on the frame synchronization signal detected by the frame synchronization detection means, This digital video recording apparatus supplies a timing signal from a timing signal generating means to a FIFO memory to control the read timing of a packetized digital video signal.

[0008] In a third aspect of the present invention, in the first aspect,
The serial bus is a serial bus conforming to IEEE1394, and the video recording unit is a digital video recording device that is a DV video recording unit.

A fourth invention is the third invention, wherein
The period correction means includes a FIFO memory to which a packetized digital video signal from the serial bus is supplied, and a frame synchronization detection means for detecting a frame synchronization signal included in the packetized digital video signal from the serial bus. And timing signal generating means for generating a timing signal indicating a standard generation timing of each packet generated after the frame synchronization signal, based on the frame synchronization signal detected by the frame synchronization detection means, This digital video recording apparatus supplies a timing signal from a timing signal generating means to a FIFO memory to control the read timing of a packetized digital video signal.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a digital video recording apparatus according to the embodiment, and FIG. 2 shows a detailed configuration of the output control apparatus of FIG.

Referring to FIG. 1, a video camera, a VTR
An analog video signal (color video signal or monochrome video signal) from a video signal source 2 such as a (magnetic tape recording / reproducing apparatus) is supplied to an A / D converter 3 and converted into a digital video signal. The digital video signal from the A / D converter 3 is supplied to a packetizing circuit 4 and packetized.

The packetized digital video signal from the packetizing circuit 4, ie, the packet data of the isochronous communication of the digital video signal is transferred to the IEEE 1394.
From a serial bus terminal 5A, through a serial bus 5 (hereinafter simply referred to as an IEEE 1394 serial bus) 5 conforming to IEEE 1394 and the IEEE 1394 serial bus terminal 5B, a video recording unit 1 of a digital VTR (digital magnetic tape recorder / reproducer) of DV standard. Send to

The packet data of the isochronous communication of the digital video signal transmitted from the serial bus 5 is
It is supplied to and received by the physical layer (Pysical Layer) 6 of the video recording unit 1. The physical layer 6 is the same as the physical layer having the layer structure of the IEEE 1394 serial bus.

The packet data from the physical layer 6 is supplied to a link layer (Link Layer) 7 and separated into a header and data. The link layer 7 is the same as the link layer having the layer structure of the IEEE 1394 serial bus.

The header and data from the link layer 7 are supplied to a frame synchronization detection circuit 8. The frame synchronization detecting circuit 8 is a SY defined by the AV protocol in the header.
By decoding the T area, a frame synchronization signal is detected, and the detected frame synchronization signal is supplied to the microcomputer 11. This microcomputer 11 controls each unit of the video recording unit 1.

The data from the link layer 7 simply passes through the frame synchronization detection circuit 8 and is transmitted through a FIFO (First-In-Fi
(rst-Out) is supplied to the memory 9.

FIG. 4 shows common isochronous packet data on IEEE1394. The packet data includes a 1394 header, a CIP header 1 and a CIP header 2
And payload data. The hatched portion indicates the above-mentioned SYT area of the CIP header 2.

The output control circuit 10 performs FIFO control based on the parameters set by the microcomputer 11 and the frame synchronization signal from the frame synchronization detection circuit 8.
The FIFO memory 9 is controlled so as to determine the timing of reading data supplied from the memory 9 to the data recording unit 16.

The data read from the FIFO memory 9 is supplied to the error correction encoding circuit 12 of the data recording section 16 to be encoded, and then supplied to the recording modulation processing circuit 13.
A modulation process for recording is performed, and the packet data of the digital video signal subjected to the modulation process is supplied to a rotating magnetic head provided on a rotating drum 15 of a tape guiding drum device to form an inclined track. As described above, the information is recorded on the magnetic tape T.

FIG. 2 shows a detailed configuration of the output control circuit 10 of FIG. 1, which will be described below. The output control circuit 8 includes a timer 18, a timer decoder 19, and a timing generation circuit 20, as shown.

The timer 18 is connected to the microcomputer 11
The clock of a predetermined frequency synchronized with the frame synchronization signal is counted, and time data based on the frame synchronization signal is output. The microcomputer 5, based on the parameter, that is, the frame synchronization signal, generates the first, second, third,.
The data of the standard generation time (equivalent interval time) of the packet data of ‥‥‥‥ is generated. And the timer decoder 1
Reference numeral 9 compares the time data from the timer 18 with the parameters from the microcomputer 5, and based on the frame synchronization signal, the first, second, third,.
The control signal of the standard generation timing of the packet data of ‥‥‥‥ is generated.
0 is supplied. Based on the control signal from the timer decoder 19, the timing generation circuit 20 generates the first, second, third,. Generate the timing pulse of the packet data of ‥. The timing pulse from the timing generation circuit 20 is supplied to the FIFO memory 7, the read timing of which is controlled, and the packet data in which the cycle of the packet data is corrected to a predetermined constant cycle is read from the FIFO memory 7.

Next, the operation of the digital video recording apparatus according to the embodiment will be described with reference to FIG. 3A and 3B show the case where the frame frequency is higher than the standard frequency,
Packet data (shown in a rectangle) which is the output of the packetizing circuit 4 in the embodiment of the present invention and the conventional example (the circuit in which the output control circuit 10 is omitted in FIG. 1) when the signal is low (original signal) (In the case shown in FIGS. 3A and 3B,
(The cycle of packet data is fixed.)
And cycle start packet data on the IEEE 1394 serial bus 5 (shown by thin solid lines in FIG. 3A,
B, packet data (shown in a rectangle) including the same fixed period) and packet data (shown in a rectangle) output from the FIFO memory 9 according to the embodiment of the present invention and the conventional example. (Including a frame synchronization signal shown by a thick solid line).

According to FIG. 3, in the case of the conventional example, depending on whether the frame frequency is higher or lower than the standard frequency,
The time interval between the frame synchronization signal and, for example, the third packet data (indicated by a rectangle with a large number of dots) after the frame synchronization signal is, as shown in Toa and Tob, respectively. It becomes long and short.

However, according to FIG. 3, in the case of the embodiment of the present invention, regardless of whether the frame frequency is higher or lower than the standard frequency, the frame synchronization signal and the subsequent frame synchronization signal For example, it can be seen that the time interval Tna between the third packet data (indicated by a rectangle with a large number of dots) is constant. Even if the cycle of the packet data of the original signal fluctuates, the frame synchronization signal and, for example, the third packet data (indicated by a rectangle with a large number of dots) after the frame synchronization signal are output. The time interval Tna between them is constant.

The serial bus is not limited to a serial bus conforming to IEEE1394. Further, the video recording unit is not limited to the DV system.

[0026]

According to the first aspect of the present invention, in a digital video recording apparatus for transmitting a packetized digital video signal to a video recording unit via a serial bus, the video recording unit is connected to the serial bus. Receiving means for receiving the packetized digital video signal, cycle correcting means for correcting the packet cycle of the packetized digital video signal from the receiving means to a predetermined constant cycle, and a packet from the cycle correcting means. Recording means for recording, on a magnetic tape, a packetized digital video signal having a predetermined fixed period, the digital video signal of the packet data of the digital video signal transmitted from the serial bus to the video recording unit. Of the packet data due to the frame frequency deviating or fluctuating from the standard frequency. Deviation and variation from a predetermined constant period of Tsu preparative period to correct, it is possible to obtain a digital video recording apparatus capable of recording the packet data to ensure the magnetic tape.

According to a second aspect of the present invention, in the first aspect of the present invention, the period correction means includes a FIFO memory to which a packetized digital video signal is supplied from a serial bus, and a packetized digital video signal from the serial bus. Frame synchronization detection means for detecting a frame synchronization signal included in the digital video signal, and a standard for each packet generated after the frame synchronization signal with respect to the frame synchronization signal detected by the frame synchronization detection means. And a timing signal generating means for generating a timing signal indicating the timing of the occurrence of the video signal. The timing signal from the timing signal generating means is supplied to a FIFO memory to control the read timing of the packetized digital video signal. The digital data transmitted from the serial bus to the video recording unit. The packet frequency of the packet data of the video signal is corrected by correcting the deviation and fluctuation of the packet period of the packet data from a predetermined constant period due to the frame frequency of the digital video signal being shifted or fluctuated from the standard frequency. A digital video recorder capable of reliably recording data on a magnetic tape can be obtained.

According to a third aspect of the present invention, in the first aspect of the present invention, the serial bus is a serial bus conforming to IEEE1394, and the video recording unit is a digital video recording device which is a DV type video recording unit. Because there is IEEE
The packet data of the digital video signal transmitted from the E1394 serial bus to the DV video recording unit due to the frame frequency of the digital video signal being shifted or fluctuated from the standard frequency. It is possible to obtain a digital video recording device capable of recording the packet data on a magnetic tape reliably by correcting deviation and fluctuation of the period from a predetermined period.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the period correction means includes a FIFO memory to which a packetized digital video signal is supplied from a serial bus, and a packetized signal from the serial bus. Frame synchronization detection means for detecting a frame synchronization signal included in the digital video signal, and a standard for each packet generated after the frame synchronization signal with respect to the frame synchronization signal detected by the frame synchronization detection means. And a timing signal generating means for generating a timing signal indicating the timing of the occurrence of the video signal. The timing signal from the timing signal generating means is supplied to a FIFO memory to control the read timing of the packetized digital video signal. From the IEEE1394 serial bus, The frame frequency of the packet data of the digital video signal transmitted to the video recording unit of the system is deviated from the standard frequency or fluctuates from the standard frequency. It is possible to obtain a digital video recording device capable of recording the packet data on the magnetic tape by correcting the deviation and the fluctuation.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a digital video recording device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of an output control circuit of an example of the digital video recording device of FIG.

FIG. 3 is a diagram showing a timing chart for explaining the operation of an example of the digital video recording device of FIG. 1;

FIG. 4 is a diagram showing the contents of a packet of packet data on a serial bus conforming to IEEE 1394;

[Explanation of symbols]

1 video recording unit, 2 video signal source, 3 A / D converter,
4 packetization circuit, 5 serial bus conforming to IEEE 1394, 6 physical layer, 7 link layer, 8 frame synchronization detection circuit, 9 FIFO memory, 10 output control circuit,
11 microcomputer, 12 error correction coding processing circuit, 13 recording modulation processing circuit, 14 recording amplifier,
15 Rotating drum.

Claims (4)

[Claims] 1. A digital video recording apparatus for transmitting a packetized digital video signal to a video recording unit via a serial bus, wherein the video recording unit comprises a packetized digital video signal from the serial bus. Receiving means for receiving the packet signal; a period correcting means for correcting the packet period of the packetized digital video signal from the receiving means to a predetermined constant period; Recording means for recording a packetized digital video signal on a magnetic tape. 2. The digital video recording apparatus according to claim 1, wherein said period correction means includes a FIFO memory to which a packetized digital video signal from said serial bus is supplied, and a packetization from said serial bus. Frame synchronization detection means for detecting a frame synchronization signal included in the digital video signal obtained, and a frame synchronization signal which is generated after the frame synchronization signal with reference to the frame synchronization signal detected by the frame synchronization detection means. Timing signal generating means for generating a timing signal indicating a standard generation timing, wherein a timing signal from the timing signal generating means is supplied to the FIFO memory to control a read timing of a packetized digital video signal. A digital video recording device characterized in that: 3. The digital video recording device according to claim 1, wherein said serial bus is a serial bus conforming to IEEE1394, and said video recording unit is a DV video recording unit. Digital video recording device. 4. The digital video recording apparatus according to claim 3, wherein said period correction means includes a FIFO memory to which a packetized digital video signal from said serial bus is supplied, and a packetization from said serial bus. Frame synchronization detection means for detecting a frame synchronization signal included in the digital video signal obtained, and a frame synchronization signal which is generated after the frame synchronization signal with reference to the frame synchronization signal detected by the frame synchronization detection means. Timing signal generating means for generating a timing signal indicating a standard generation timing, wherein a timing signal from the timing signal generating means is supplied to the FIFO memory to control a read timing of a packetized digital video signal. A digital video recording device characterized in that: