JP2001245012A - Delay detection device and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a circuit scale from being expanded even if the number of input terminals is increased in a delay detection device provided with a shift register successively delaying input digital data by a clock input and a data operating part operating an output of the shift register and the input digital data. SOLUTION: A data multiplexing part 102 performs time division multiplexing of the data of input digital data terminals 101 consisting of N systems, the multipelxed data are inputted to a shift register 103 having N-stage registers needed to delay the data, and the data stored in the register are successively shifted to the next register to be delayed by inputting a clock to the register 103 from a clock input terminal 104. Only one data operating part 105 can perform delay detection in such a manner that the part 105 operates output data from the part 102 and the output data from the register 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to differential detection of a digital phase modulated signal.

[0002]

2. Description of the Related Art A differential detection apparatus is generally used for receiving a differentially encoded signal on a transmission side, obtaining a phase difference between one symbol of a received signal, and obtaining a demodulated signal. It is mounted on devices, base station devices, and mobile station devices.

FIG. 6 is a vector diagram of input / output data in a delay detection apparatus for a π / 4 shifted QPSK signal. From FIG. 6, the input data is mapped around eight points on the complex plane, and the output data after differential detection is 4 points on the complex plane.
Is mapped around two points.

[0004] The delay detection apparatus uses continuous phase data (θ
_{When (1} , θ ₂ ) is input, (θ ₂ −θ ₁ ) is output as a detection signal. In addition, continuous data (I ₁ ,
If I ₂ , Q ₁ , Q ₂ ) are input, I ₃ = I ₂ I ₁ + Q
_{2 Q 1, Q 3 = I} 1 Q 2 -I 2 Q 1 is outputted as a detection signal.

When there are a plurality of systems of input data, it is necessary to perform delay detection for each system. Conventionally, delay detection has been performed by a delay detection device prepared for each input data of each system. FIG. 7 shows a configuration of a conventional differential detection device.

Hereinafter, a conventional delay detection apparatus will be described with reference to FIG. As shown in FIG. 7, N input digital data terminals 401a, 401b,.
n, input digital data terminals 401a, 401b,
, 401n for delaying input data of the shift registers 402a, 402b,..., 402n, and a clock input terminal 403 for inputting a clock for delaying data in the shift registers 402a, 402b,.
, 403n, input digital data terminals 401a, 401b,..., 401n, and input data of shift registers 402a, 402b,. Parts 404a, 404
b,... 404n and data operation units 404a, 404
b,..., 404n connected to the output terminals
5a, 405b,..., 405n.

[0007] The operation of the differential detection apparatus configured as described above will be described below. Shift registers 402a, 40b corresponding to respective systems from the input digital data terminals 401a, 401b,.
, 402n, and shift register 402
., 402n, the clock signals are input from clock input terminals 403a, 403b,.
a, 402b,..., 402n are operated to sequentially move and delay the data. The number of shift stages and the clock are set so as to delay the input signal by one symbol, and thereafter, the input digital data terminals 401a, 401b,.
01n and shift registers 402a, 402
2b,..., 402n, and
, 404n, and outputs the operation results to operation output terminals 405a, 405b,.
The delay detection is performed by outputting from n.

[0008]

However, in the prior art, when there are N systems of input digital data, N data operation units in the differential detection operation circuit are required. Therefore, when designing a circuit, there is a problem that the circuit scale is enlarged and the number of wirings between the shift register and the data operation unit is increased.

[0009]

DISCLOSURE OF THE INVENTION The present invention has been made to solve such a problem, and it has been proposed that data can be obtained regardless of the number of systems.
The data processing unit is realized by one and the circuit scale can be reduced. In order to solve the problem, a multi-input digital data is subjected to time division multiplex processing, a shift register having a necessary number of registers for delaying the multiplexed data, and sequentially delaying by a clock input; The multiplexed data and the output data of the shift register
A data calculation unit for calculating data is provided.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following embodiments will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block connection diagram showing a first embodiment of the differential detection apparatus according to the present invention. The delay detection apparatus shown in FIG. 1 includes an N-system input digital data terminal 101, an N-system input digital data input data input unit 102, and a data multiplex unit 102. An N-stage shift register 103 for delaying the division multiplexed data, a clock input terminal 104 for inputting a clock for delaying the data by the shift register 103, and output data from the data multiplexing unit 102 A data operation unit 105 for operating output data from the shift register 103; and an operation output terminal 10 connected to an output terminal of the data operation unit 105
6 is provided.

The operation of the differential detection apparatus shown in FIG. 1 will be described.
The data of an N-system input digital data terminal 101 is input to a data multiplexing unit 102, which is a device for time-division multiplexing, and N stages of data necessary for delaying the multiplexed data. By inputting the data to the shift register 103 having a register and inputting a clock from the clock input terminal 104 to the shift register 103, the data stored in the register is sequentially moved to the next register and delayed. And
The output data from the data multiplexing unit 102 and the output data of the shift register 103 which is the input data one symbol before.
Data is calculated by the data calculation unit 105 and the calculation result is output from the calculation output terminal 106 to perform delay detection.

By employing the configuration shown in FIG. 1, N data operation units conventionally required are constituted by one, and the number of wires between the shift register and the data operation unit is designed to be small. It becomes possible.

(Embodiment 2) Next, a second embodiment of the present invention will be described. In the second embodiment of the present invention, continuous phase data (θ1, θ2) is This is an embodiment in which phase difference data (θ2−θ1) is output. FIG.
FIG. 3 is a block diagram of a second embodiment of the delay detection apparatus according to the present invention, and FIG. 3 is a time chart showing the operation of the second embodiment.

The differential detector shown in FIG. 2 has four input digital data terminals 201a, 201b, 201c, and 2
01d, a selector 202a for selecting input data,
A data multiplexing unit 102 comprising a flip-flop circuit 202b to which the output data of the selector 202a is input.
And flip-flop circuits 203h and 203l for delaying output data of the flip-flop circuit 202b.
Shift register 103 composed of 203m and 202n
And a flip-flop circuit 2 in the data multiplexing unit 102.
02b and the flip-flop circuit 20 in the shift register
3h, 203l, 203m and 202n, a clock input terminal 104 for inputting a clock for synchronizing and delaying data, a shift register 103 which is output data from the flip-flop circuit 202b and data one symbol before. Output data from the flip-flop circuit 203n
A data calculation unit 105 for calculating data and a data calculation unit 1
And an arithmetic output terminal 206 connected to the output terminal of the output terminal 05.

The operation of the differential detection apparatus shown in FIG. 2 will be described. Input digital data terminals 201a, 201b, 201
c, 201 d from the data multiplexing section 102.
Of the selector 202a, and the output data of the selector 202a is sequentially input to the flip-flop circuit 202b, so that the input data is time-division multiplexed and the data is output from the flip-flop circuit 202b. The flip-flop circuits 203h, 203l, and 20 are used to delay the output data time-division multiplexed by the data multiplexing unit 102.
3m, 203n, and the flip-flop circuits 203h, 203l, 203 are input to the shift register 103 from a clock input terminal 104.
The data is delayed by inputting a clock signal to m and 203n. At this time, the timing of multiplexing the input data and the timing of delaying the multiplexed data are synchronized because a clock signal is input from the same clock input terminal 104. Thereafter, the output data from the flip-flop circuit 203n of the shift register 103 is subtracted from the output data from the flip-flop circuit 202b of the data multiplexing unit 102 by the data operation unit 105, and the operation result is output. Delay detection is performed by outputting from the terminal 206.

As shown in FIG. 2, a selector 202a for selecting input data from four input digital data terminals 201a, 201b, 201c and 201d, and a selector 2
02a, and the output data of the flip-flop circuit 202b.
Flip-flop circuits 203h, 203l, 203 constituting a four-stage shift register 103 for delaying data
m, 203n and a data operation unit 10 composed of a subtractor.
5, the number of data operation units conventionally required four can be constituted by one, and the number of wires between the shift register and the data operation unit can be designed to be small. Become. Also, input digital data terminals 201a, 201
The input data of 1b, 201c and 201d and the output data of the operation output terminal 206 may be 1-bit data or plural-bit data. Although the present embodiment has been described for the case of four multiplexing, it can also be realized for the case of N multiplexing (N is a natural number).

(Embodiment 3) Next, a third embodiment of the present invention will be described. In the third embodiment of the present invention, continuous IQ data (I1, Q1, I2, Q2) is used. Enter I
3 = I2 · I1 + Q2 · Q1, Q3 = I1 · Q2−I2 · Q
This is an embodiment when 1 is output. FIG. 4 is a block diagram of a third embodiment of the delay detection apparatus according to the present invention, and FIG. 5 is a time chart showing the operation of the third embodiment.

The differential detection apparatus shown in FIG. 4 has input digital data terminals 301aI and 301aI each having four systems of IQ data.
301bI, 301cI, 301dI, 301aQ,
301bQ, 301cQ, 301dQ, a data multiplexing unit 102 to which digital data is input, a shift register 103 for delaying the output of the data multiplexing unit 102,
A data operation unit 105 that performs an operation based on the output of the data multiplexing unit 102 and the output of the shift register 103 is provided.

The data multiplexing section 102 is composed of selectors 302a and 302b having input digital data as input and flip-flop circuits 302c and 302d having output data from the selector 302a as input. The outputs of the first and second flip-flop circuits 302 c and 302 d constitute the shift register 103.
3hi, sent to 303hq. The selector 302a
Input digital data terminals 301aI, 301bI, 3
The selector 302b selects the input data from 01cI and 301dI and sends it to the flip-flop circuit 302c. The selector 302b includes an input digital data terminal 301a.
The input data from Q, 301bQ, 301cQ and 301dQ are selected and sent to the flip-flop circuit 302d.

The shift register 103 includes flip-flop circuits 303hI, 303lI, 303mI, 30 for delaying the output of the flip-flop circuit 302c.
3nI I-side shift register and flip-flop circuits 303hQ, 303lQ, 303mQ,
It comprises a Q signal side shift register composed of 303nQ, and operates synchronously with a clock from the clock input terminal 104 together with the flip-flop circuits 302c and 302d.

The data operation unit 105 includes a multiplier 304x
I, 304yI, 304yQ, 304xQ and adder 3
05I and a subtractor 305Q.
From the output terminal 306I of I3 = I2 · I1 + Q2 · Q1
Is output from the output terminal 306Q of the subtractor 305Q. A signal corresponding to Q3 = I1 · Q2−I2 · Q1 is output.

The multiplier 304xI includes a data multiplexing unit 10
2 from the flip-flop circuit 302c and the flip-flop circuit 303n of the shift register 103.
Multiplied by the output data from I, the multiplier 304yI
Flip-flop circuit 302d of data multiplexing section 102
Is multiplied by the output data from the flip-flop circuit 303nQ of the shift register 103.
The multiplier 304yQ multiplies the output data from the flip-flop circuit 302c of the data multiplexing unit 102 by the output data from the flip-flop circuit 303nQ of the shift register 103. The output data from the flip-flop circuit 302d of the data multiplexing unit 102 is multiplied by the output data from the flip-flop circuit 303nI of the shift register 103. The adder 305I adds the output data of the multiplier 304xI and the output data of the multiplier 304yI, and
05Q is based on the output data of the multiplier 304.times.Q.
04yQ output data is subtracted.

The operation of the delay detection circuit shown in FIG. 4 will be described.
Input digital data terminals 301aI, 301b, 30
The input data from 1cI and 301dI are input to the selector 302a of the data multiplexing unit 102, and the selector 302a
Is input to the flip-flop circuit 302c to input digital data terminals 301aI and 301aI.
The input data from bI, 301cI, and 301dI are time-division multiplexed and output from flip-flop circuit 302c. Similarly, input digital data terminal 301a
Input data from Q, 301bQ, 301cQ, and 301dQ are input to the selector 302b of the data multiplexing unit 102, and output data of the selector 302b is input to the flip-flop circuit 302d to input digital data. The input data from the terminals 301aQ, 301bQ, 301cQ, and 301dQ are time-division multiplexed and output from the flip-flop circuit 302d.

Next, flip-flop circuits 303hI, 303lI, 303mI, 303nI, 3 are used to delay the data time-division multiplexed by the data multiplexing section 102.
The output data from the flip-flop circuit 302c is supplied to the flip-flop circuit 30 in the shift register 103 composed of 03hQ, 303lQ, 303mQ, and 303nQ.
3hI, and inputs a clock signal from the clock input terminal 104 to the flip-flop circuits 303hI, 303lI,
The data is sequentially delayed by inputting the signals to 303m and 303nI. Similarly, the output data from the flip-flop circuit 302d is input to the flip-flop circuit 303hQ.
A clock signal is supplied from the clock input terminal 104 to the flip-flop circuits 303hQ, 303lQ, 303mQ, 30
Data is sequentially delayed by input to 3nQ. At this time, the timing for multiplexing the input digital data and the timing for delaying the multiplexed data are supplied from the same clock input terminal 104 to the flip-flop circuits 302c and 30c.
2d, 303hI, 303lI, 303mI, 303
nI, 303hQ, 303lQ, 303mQ, 303n
Q is synchronized by inputting a clock signal.

The output data from the flip-flop circuit 302c of the data multiplexing unit 102 and the data output from the flip-flop circuit 303nI of the shift register 103 are multiplied by a multiplier 304xI. The output data from the flip-flop circuit 302d of the data multiplexing unit 102 and the output data from the flip-flop circuit 303nQ of the shift register 103 are multiplied by a multiplier 304yI, and multiplied by the output data of the multiplier 304xI. Container 304y
The output data of I is added by an adder 305I to obtain I
The delay detection of the axis component data is performed, and the calculation result is output from a calculation output terminal 306I. Similarly, data multiplexing section 102
Output from the flip-flop circuit 302d and the flip-flop circuit 303 of the shift register 103.
The output data from nI is multiplied by a multiplier 304xQ,
Flip-flop circuit 302c of data multiplexing section 102
Is multiplied by the data output from the flip-flop circuit 303nQ of the shift register 103 by the multiplier 304yQ, and the output data of the multiplier 304xQ is output.
The output data of the multiplier 304yQ is subtracted from the data by the subtractor 305Q.
, The delay detection of the Q-axis component data is performed, and the calculation result is output from the calculation output terminal 306Q.

By using the configuration as shown in FIG. 4, when the input of the conventional IQ data is four systems, the multiplier 4 requires 16 adders, 4 adders and 4 subtractors. , One adder and one subtractor, and the number of wires between the shift register and the data processing unit can be reduced. Also, input digital data terminals 301aI,
301bI, 301cI, 301dI, 301aQ,
Input data of 301bQ, 301cQ, 301dQ;
The output data of the operation output terminals 306I and 306Q may be 1-bit data or multi-bit data. Although the present embodiment has been described for the case of four multiplexing, it can also be realized for the case of N multiplexing (N is a natural number).

[0028]

As described above, according to the present invention, input digital data of a plurality of systems are subjected to time division multiplexing processing, registers having a register necessary for delaying the multiplexed data, and sequentially delayed by a clock. By providing a delay detection device including a shift register to be operated and a data operation unit for performing an operation based on the output of the shift register and the multiplexed data,
A single data operation unit can be realized, the number of wires between the data multiplexing unit and the shift register can be reduced, and the circuit scale can be reduced when the circuit is actually realized. Therefore, in the case of realizing the hardware for performing the delay detection of the multi-input digital data, the circuit scale can be reduced and the design can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a differential detection apparatus according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the differential detection apparatus according to the present invention;

FIG. 3 is a time chart showing the operation of the second embodiment.

FIG. 4 is a block diagram showing a third embodiment of the differential detection apparatus according to the present invention;

FIG. 5 is a time chart showing the operation of the third embodiment.

FIG. 6 is a vector diagram of input / output data in a π / 4 shift QPSK modulation differential detector.

FIG. 7 is a block diagram of a conventional differential detection device.

[Explanation of symbols]

101: input digital data terminal 102: data multiplexing unit 103: shift register 104: clock input terminal 105: data operation unit 106: ··· Arithmetic output terminals 201a to 201d ··· Input digital data terminals 202a ··· Selector 202b ··· Flip-flop circuits 203h, 203l, 203m and 203n ··· Flip-flop circuits 206 ··· · Operation output terminals 301aI to 301dI ··· Input digital data terminals 301aQ to 301dQ ··· Input digital data terminals 302a and 302b ··· Selectors 302c and 302d ··· Flip-flop circuits 303hI and 303lI, 303mI, 303nI ...
・ Flip-flop circuit 303hQ, 303lQ, 303mQ, 303nQ
・ Flip-flop circuit 304xI, 304xQ, 304yI, 304yQ
· Multiplier 305I ··· Adder 305Q ··· Subtractor 306I and 306Q ··· Operation output terminals 401a to 401n ··· Input digital data terminals 402a to 402n ··· Shift register 403a ... 403n... Clock input terminals 404a to 404n... Subtracters 405a, 405b, 405n.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryusuke Kiryu 2-45-1, Hikosancho, Kanazawa City, Ishikawa Prefecture Inside the Matsushita Communication Kanazawa Research Institute Co., Ltd. (72) Atsushi Matsumoto 2, Hikosancho, Kanazawa City, Ishikawa Prefecture No. 1-45 F-term in Matsushita Communication Kanazawa Laboratory (reference) 5K004 AA05 FA05 FG02 FG03 5K028 AA07 FF13 KK01 KK03 KK18

Claims (10)

[Claims] 1. A data multiplexing section for time-division multiplexing a plurality of systems of input digital data, a shift register to which output data of a data multiplexing section are sequentially inputted, and an output data of the shift register. And a data calculation unit for performing a predetermined calculation based on output data of the data multiplexing unit. 2. The delay detection device according to claim 1, wherein the input digital data of the plurality of systems is phase data, and the data calculation unit is a subtractor. 3. The differential detection apparatus according to claim 1, wherein the input digital data of the plurality of systems comprises an in-phase (I) component and a quadrature (Q) component of a baseband signal, and A multiplexing unit includes an in-phase (I) component data multiplexing unit for time-division multiplexing the in-phase (I) component of each system and an orthogonal component (Q) for time-division multiplexing the orthogonal (Q) component of each system. ) A data multiplexing unit, wherein the shift register comprises: an in-phase (I) component shift register to which output data of the in-phase (I) component data multiplexing unit is sequentially inputted; and a quadrature (Q) component. A quadrature (Q) component shift register to which the output data of the data multiplexing unit is sequentially inputted, wherein the data calculation unit calculates the in-phase (I) component data. And a quadrature (Q) component data operation for calculating the quadrature (Q) component data Delayed detection device composed of a. 4. The differential detection apparatus according to claim 3, wherein said in-phase (I) component data calculating section is configured to output data of said in-phase (I) component data multiplexing section and said in-phase (I) component data multiplexing section. (I) a first multiplier for multiplying output data of the component shift register, output data of the orthogonal (Q) component data multiplexing unit, and output of the orthogonal (Q) component shift register; A second multiplier for multiplying the data by the data; an adder for adding output data of the first multiplier to output data of the second multiplier; A third multiplication unit for multiplying the output data of the in-phase (I) component data multiplexing unit with the output data of the quadrature (Q) component shift register by the (Q) component data operation unit; A multiplier for multiplying the output data of the orthogonal (I) component shift register by the output data of the orthogonal (Q) component data multiplexing unit. And the multiplier, the fourth multiplier output data - the other third multiplier output de - delay detection device composed of a subtracter for subtracting the data. 5. A wireless communication device equipped with the delay detection device according to claim 1. 6. A base station device equipped with the differential detection device according to claim 1. 7. A mobile station device equipped with the differential detection device according to claim 1. 8. A plurality of systems of input digital data are time-division multiplexed, the multiplexed data is sequentially delayed, a predetermined operation is performed based on the delayed data and the multiplexed data, and detection output is performed. Obtain a differential detection method. 9. The differential detection method according to claim 8, wherein the input digital data of the plurality of systems is phase data, and the predetermined operation is a subtraction. 10. The differential detection method according to claim 8, wherein the input digital data of the plurality of systems comprises an in-phase (I) component and a quadrature (Q) component of a baseband signal; The operation is performed in-phase (I) of the multiplexed data.
The component is I2, the data of the quadrature (Q) component is Q2, the in-phase (I) component of the delayed data is I1, and the quadrature (Q)
When the component is Q1, a differential detection method is an operation of I2 · I1 + Q2 · Q1, and an operation of I1 · Q2−I2 · Q1.