JP2001244394A - Heat dissipating structure of semiconductor package - Google Patents

Heat dissipating structure of semiconductor package

Info

Publication number
JP2001244394A
JP2001244394A JP2000056795A JP2000056795A JP2001244394A JP 2001244394 A JP2001244394 A JP 2001244394A JP 2000056795 A JP2000056795 A JP 2000056795A JP 2000056795 A JP2000056795 A JP 2000056795A JP 2001244394 A JP2001244394 A JP 2001244394A
Authority
JP
Japan
Prior art keywords
heat
semiconductor chip
semiconductor package
wiring board
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000056795A
Other languages
Japanese (ja)
Inventor
Kozo Masuda
幸造 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000056795A priority Critical patent/JP2001244394A/en
Publication of JP2001244394A publication Critical patent/JP2001244394A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the heat transfer efficiency between a CPU and a heat sink for CPU heat dissipating structure of personal computer. SOLUTION: Using both of heat conduction grease 10 and heat conduction sheet 6 which is shaped hole style provide heat liberation function that can do with high quality, high heat up CPU package by conduction to heat sink 7 from both side of surface CPU package and basis 3 of CPU package.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、パーソナルコンピ
ュータのCPUの放熱構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat radiation structure for a CPU of a personal computer.

【0002】[0002]

【従来の技術】モバイル用パソコンに使用するCPU
は、小型、軽量、薄型、放熱性の機能を追求した結果、
ベアチップに近い状態でパケージ化されている。図4に
モバイル用CPUパッケージの断面図を示す。図4にお
いて、51は半導体チップ、52はチップ基板、53は
半導体チップ51に設けたバンプ電極、54は半田ボー
ル、55は封止樹脂である。半導体チップ51はシリコ
ンよりなり、裏面にはバンプ電極53が設けられてい
る。バンプ電極53は、チップ基板52を貫通する図に
は示していない導体回路によって、半田ボール54と接
続している。半導体チップ51とチップ基板52との隙
間は封止樹脂55が充填され、バンプ電極53を外気の
湿度、温度より保護している。半導体チップ51の表面
はシリコンチップ面が露出していて、半導体チップ51
内部で発生した熱の放熱をよくしている。
2. Description of the Related Art CPU used in mobile personal computers
Is pursuing small, lightweight, thin, and heat-dissipating functions.
It is packaged in a state close to a bare chip. FIG. 4 is a sectional view of a mobile CPU package. In FIG. 4, reference numeral 51 denotes a semiconductor chip, 52 denotes a chip substrate, 53 denotes a bump electrode provided on the semiconductor chip 51, 54 denotes a solder ball, and 55 denotes a sealing resin. The semiconductor chip 51 is made of silicon, and a bump electrode 53 is provided on the back surface. The bump electrodes 53 are connected to the solder balls 54 by conductor circuits (not shown) penetrating the chip substrate 52. The gap between the semiconductor chip 51 and the chip substrate 52 is filled with a sealing resin 55 to protect the bump electrodes 53 from the humidity and temperature of the outside air. The silicon chip surface is exposed on the surface of the semiconductor chip 51, and the semiconductor chip 51
The heat generated inside is improved.

【0003】図5に従来行われている半導体チップ51
の放熱構造を説明する。図5において、56は配線基
板、57はヒートシンク、58は熱伝導性グリスであ
る。半田ボール53は配線基板56に設けた図には示し
ていない配線ランドと接続され演算回路を形成してい
る。ヒートシンク57は、半導体チップ51が発生する
熱を授受し、自身は例えば周囲を空冷するファン59等
の冷却手段によって、授受した熱を空気中に放熱してい
る。半導体チップ51とヒートシンク57との間の熱授
受は、熱伝導性グリス58を介して行われる。熱伝導性
グリス58は100μm以下の厚さに塗布されて、半導
体チップ51とヒートシンク57との間の接触を確実に
し、熱抵抗を小さくしている。この方法は、熱伝導性グ
リス58の膜厚を薄くできるので放熱効果に優れている
が、半導体チップ51がヒートシンク57との間に狭持
されているため挟持圧力が小さな場合には振動によるが
たつきが発生し、反対に挟持圧力が大きな場合には半田
ボール53と配線ランド間の接点を破損する危惧があっ
た。
FIG. 5 shows a conventional semiconductor chip 51.
Will be described. In FIG. 5, 56 is a wiring board, 57 is a heat sink, and 58 is heat conductive grease. The solder balls 53 are connected to wiring lands (not shown) provided on the wiring board 56 to form an arithmetic circuit. The heat sink 57 transfers the heat generated by the semiconductor chip 51, and radiates the transferred heat into the air by a cooling means such as a fan 59 that cools the surroundings. Heat transfer between the semiconductor chip 51 and the heat sink 57 is performed via the heat conductive grease 58. The thermally conductive grease 58 is applied to a thickness of 100 μm or less to ensure contact between the semiconductor chip 51 and the heat sink 57 and to reduce thermal resistance. This method has an excellent heat dissipation effect because the thickness of the heat conductive grease 58 can be reduced. However, since the semiconductor chip 51 is sandwiched between the heat sink 57 and the heat sink 57, when the clamping pressure is small, the method may cause vibration. When the holding pressure is large, the contact between the solder ball 53 and the wiring land may be damaged.

【0004】また、半導体チップ51とヒートシンク5
7との間の他の熱伝導方法として図6(a)に示すよう
なゴム弾性を有する熱伝導性シート60を使用して、弾
性シート60を圧力で変形させて密着性、熱伝導性を確
保していた(図6(b))。この方法はゴム弾性体を介
在させているので、半導体チップ51には掛かる応力を
均一化できるが、弾性シート60の厚みが厚くなるの
で、熱伝導効率が悪い欠点があった。
A semiconductor chip 51 and a heat sink 5
7A and 7B, a rubber-elastic heat-conductive sheet 60 as shown in FIG. 6A is used, and the elastic sheet 60 is deformed by pressure to improve adhesion and heat conductivity. (FIG. 6B). In this method, since the rubber elastic body is interposed, the stress applied to the semiconductor chip 51 can be made uniform. However, since the thickness of the elastic sheet 60 is increased, there is a disadvantage that heat conduction efficiency is poor.

【0005】[0005]

【発明が解決しようとする課題】半導体チップの高性能
化に伴う発熱量の増大、高密度化による半田ボールの小
型化に伴い放熱性が良好で、かつ半導体チップを信頼性
よく保持することのできる放熱構造が強く望まれてい
る。放熱性を改善するためヒートシンク用の効率のよい
ファンシステムが開発されているが、改良されたファン
システムを使用しても、半導体チップからヒートシンク
への熱伝導効率を上げなければ、十分な放熱効果を得る
ことができなくなってきている。図5の構造では熱伝導
面積が半導体チップの上面積に限定され、また図6の構
造では熱伝導面積は拡大するが、熱伝導シートはある程
度の厚さが必要になるため、熱抵抗が大きくなりヒート
シンクへ十分に伝熱させることができないという課題が
あった。
SUMMARY OF THE INVENTION It has been found that the heat dissipation is good and the semiconductor chip is reliably held with the increase in heat generation accompanying the high performance of the semiconductor chip and the miniaturization of the solder ball due to the high density. There is a strong demand for a heat dissipation structure that can be used. Efficient fan systems for heat sinks have been developed to improve heat dissipation, but even with the improved fan system, sufficient heat dissipation is required unless the heat transfer efficiency from the semiconductor chip to the heat sink is increased. Can't get any more. In the structure of FIG. 5, the heat conduction area is limited to the upper area of the semiconductor chip, and in the structure of FIG. 6, the heat conduction area is increased. However, since the heat conduction sheet requires a certain thickness, the heat resistance is large. However, there is a problem that the heat cannot be sufficiently transferred to the heat sink.

【0006】本発明は、以上のような従来例の課題を解
決するためになされたもので、高性能、高発熱の半導体
チップに対応できる効率の良い放熱構造を提供すること
を目的としている。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional example, and has as its object to provide an efficient heat radiation structure which can cope with a semiconductor chip having high performance and high heat generation.

【0007】[0007]

【課題を解決するための手段】この課題を解決するため
に本発明は、弾性を有する熱伝導シートを半導体チップ
の周囲に配し、半導体チップの上表面、半導体チップの
側面、および半導体基板表面の三方向の熱をヒートシン
クへ効率良く熱伝導できるように構成し、かつ半導体チ
ップにかかる圧力を熱伝導シートにも分担させ、半導体
チップの上表面に無理な圧力がかからないように構成し
たものである。
SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a heat conductive sheet having elasticity around a semiconductor chip, the upper surface of the semiconductor chip, the side surface of the semiconductor chip, and the surface of the semiconductor substrate. It is configured so that heat in three directions can be efficiently conducted to the heat sink, and the pressure applied to the semiconductor chip is also shared by the heat conductive sheet so that excessive pressure is not applied to the upper surface of the semiconductor chip. is there.

【0008】[0008]

【発明の実施の形態】本発明の請求項1に記載の発明
は、半導体チップを実装する配線基板と、前記半導体チ
ップの周囲を取巻く弾性を有する熱伝導体と、半導体チ
ップの上表面に塗布した熱伝導性グリスと、前記熱伝導
性グリスと対向するヒートシンクと、前記ヒートシンク
と前記配線基板との間に設けたばね手段とよりなること
を特徴とするものであり、半導体チップの上表面、半導
体チップの側面、および半導体基板表面の三方向の熱を
ヒートシンクへ効率良く熱伝導できるので、放熱性に優
れている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a wiring board on which a semiconductor chip is mounted, an elastic heat conductor surrounding the periphery of the semiconductor chip, and a coating on an upper surface of the semiconductor chip. Heat conductive grease, a heat sink opposed to the heat conductive grease, and a spring means provided between the heat sink and the wiring board, the upper surface of the semiconductor chip, the semiconductor Since heat in three directions on the side surface of the chip and the surface of the semiconductor substrate can be efficiently conducted to the heat sink, the heat dissipation is excellent.

【0009】本発明の請求項2に記載の発明は、請求項
1に記載の発明において、熱伝導体の厚みが、半導体チ
ップの背の高さよりも厚いことを特徴とするものであ
り、ヒートシンクへの熱伝導を確実にし、かつ半導体チ
ップにかかる圧力を熱伝導体に分担させることができる
ため、放熱性がよく、信頼性が高い。
According to a second aspect of the present invention, in the first aspect, the thickness of the heat conductor is larger than the height of the back of the semiconductor chip. Since heat conduction to the semiconductor chip can be ensured and the pressure applied to the semiconductor chip can be shared by the heat conductor, heat dissipation is good and reliability is high.

【0010】本発明の請求項3に記載の発明は、請求項
2に記載の発明において、配線基板の筐体底面に設けた
ボスを基準として、配線基板とヒートシンクの間にばね
手段を設けたことを特徴とするものであり、ばね圧力が
安定するので最適の圧力を設定することができ、放熱効
率がよい。
According to a third aspect of the present invention, in the second aspect, a spring means is provided between the wiring board and the heat sink with reference to a boss provided on the bottom surface of the housing of the wiring board. The spring pressure is stable, so that an optimal pressure can be set, and the heat radiation efficiency is good.

【0011】以下、本発明の実施の形態について、図
1、2を用いて説明する。
An embodiment of the present invention will be described below with reference to FIGS.

【0012】(実施の形態1)図1は、本発明の放熱構
成を示す斜視図、図2は断面図、図3はばね手段の要部
拡大断面図である。
(Embodiment 1) FIG. 1 is a perspective view showing a heat dissipation structure of the present invention, FIG. 2 is a sectional view, and FIG. 3 is an enlarged sectional view of a main part of a spring means.

【0013】図1、図2において、1は半導体パッケー
ジ、2は半導体チップ、3はチップ基板、4は配線基
板、5は封止樹脂、6は熱伝導シート、7はヒートシン
ク、8はファン、9は半田ボール、10は熱伝導性グリ
ス、11は配線基板4を内蔵するモバイルパソコンの筐
体底面である。
1 and 2, 1 is a semiconductor package, 2 is a semiconductor chip, 3 is a chip substrate, 4 is a wiring board, 5 is a sealing resin, 6 is a heat conductive sheet, 7 is a heat sink, 8 is a fan, 9 is a solder ball, 10 is a thermally conductive grease, and 11 is a bottom surface of the housing of the mobile personal computer in which the wiring board 4 is built.

【0014】半導体パッケージ1、配線基板4の構造
は、従来例で説明したのと同じものであり、半導体パッ
ケージ1は、従来法によって配線基板4に実装されてい
るので、再度の説明は省略する。
The structures of the semiconductor package 1 and the wiring board 4 are the same as those described in the conventional example. Since the semiconductor package 1 is mounted on the wiring board 4 by a conventional method, the description will not be repeated. .

【0015】ヒートシンク7はファン8を内蔵し、ファ
ン8は、例えば図2においては筐体底面11近辺の温も
った空気を吸引し、筐体外部に排出している(矢印は空
気の流れを示す)。
The heat sink 7 has a built-in fan 8, and the fan 8 in FIG. 2, for example, sucks warm air near the housing bottom surface 11 and discharges it to the outside of the housing (arrows indicate the flow of air). Shown).

【0016】半導体パッケージ1はヒートシンク7と配
線基板4との間に設けたばね手段によって圧力が加えら
れ、半導体パッケージ1とヒートシンク7との間の熱伝
導性を高めている。図3によって実施の形態1における
ばね手段の構造の一例を説明する。
Pressure is applied to the semiconductor package 1 by a spring means provided between the heat sink 7 and the wiring board 4 to increase the thermal conductivity between the semiconductor package 1 and the heat sink 7. An example of the structure of the spring means according to the first embodiment will be described with reference to FIG.

【0017】図3において、20は筐体底面11に設け
たボス、21はボス20に設けたねじ穴、22はヒート
シンク7に設けた貫通孔、23はねじ、24はコイルば
ね、25はばね止めボス、26は配線基板4に設けた馬
鹿穴である。ねじ穴21と、穴26と、穴22とを位置
合わせし、配線基板4と、ヒートシンク7とを重ね合せ
る。コイルばね24を装填したねじ23を穴22に入
れ、ねじ止めによって配線基板4とヒートシンク7とを
ボス20の上に固定する。図2に示しているように半導
体パッケージ1は配線基板4とヒートシンク7との間に
挟まれているので、半導体パッケージ1はばね24の力
によって押圧されている。
In FIG. 3, 20 is a boss provided on the bottom surface 11 of the housing, 21 is a screw hole provided on the boss 20, 22 is a through hole provided on the heat sink 7, 23 is a screw, 24 is a coil spring, and 25 is a spring. Stop bosses 26 are stupid holes provided on the wiring board 4. The screw hole 21, the hole 26, and the hole 22 are aligned, and the wiring board 4 and the heat sink 7 are overlapped. The screw 23 loaded with the coil spring 24 is inserted into the hole 22, and the wiring board 4 and the heat sink 7 are fixed on the boss 20 by screwing. As shown in FIG. 2, since the semiconductor package 1 is sandwiched between the wiring board 4 and the heat sink 7, the semiconductor package 1 is pressed by a spring 24.

【0018】半導体パッケージ1を配線基板4に実装す
ると、半田バンプ9の熔融ばらつきによって半導体チッ
プ2の表面高さは、実装高さばらつき(0.5mm程
度)を持つようになる。ねじ23を完全にねじ込むこと
によって、配線基板4を筐体底面11に固定している
が、実装ばらつきが最大の半導体パッケージ1の場合に
も、ばね止めボス25と配線基板4との間には隙間がで
きる寸法に設計している。この構成により、半導体パッ
ケージ1は所定の範囲の押圧力で、ヒートシンク7と配
線基板4との間に狭持される。
When the semiconductor package 1 is mounted on the wiring board 4, the surface height of the semiconductor chip 2 has a mounting height variation (about 0.5 mm) due to a variation in the melting of the solder bumps 9. The wiring board 4 is fixed to the bottom surface 11 of the housing by completely screwing the screw 23. However, even in the case of the semiconductor package 1 in which the mounting variation is the largest, there is a gap between the spring stopper boss 25 and the wiring board 4. It is designed to have a gap. With this configuration, the semiconductor package 1 is held between the heat sink 7 and the wiring board 4 with a predetermined range of pressing force.

【0019】半導体チップ2の寸法は、高さ0.85m
m、幅11.5mm、奥行き9.2mmの立方体であ
が、周囲を封止樹脂5によって覆われてチップ基板3と
接着されているので、半導体チップ2は完全な立方体形
状ではない。
The dimensions of the semiconductor chip 2 are 0.85 m in height.
m, a width of 11.5 mm and a depth of 9.2 mm, but the periphery is covered with the sealing resin 5 and adhered to the chip substrate 3, so that the semiconductor chip 2 is not a perfect cube.

【0020】熱伝導シート6は開口部を有し、開口部の
中に半導体チップ2を収納するよう構成し、開口部の外
周はチップ基板3と同じ面積を持つ。熱伝導シート6は
シリコン系の樹脂であり、熱伝導シートとして熱伝導
率、硬さ、厚み等異なるものが市販されている。熱伝導
性グリス10も放熱用ととして市販されているものであ
り、熱伝導率、粘度等異なるものを入手することができ
る。
The heat conductive sheet 6 has an opening, and the semiconductor chip 2 is accommodated in the opening. The outer periphery of the opening has the same area as the chip substrate 3. The heat conductive sheet 6 is a silicon-based resin, and heat conductive sheets having different heat conductivity, hardness, thickness, and the like are commercially available. The heat conductive grease 10 is also commercially available for heat dissipation, and different materials such as heat conductivity and viscosity can be obtained.

【0021】上記説明した構成の半導体パッケージ1の
組立て方法と、放熱作用について説明する。
A method of assembling the semiconductor package 1 having the above-described structure and a heat radiation function will be described.

【0022】配線基板4の上に実装した半導体パッケー
ジ1の周囲に熱伝導シート6を装着する。次に、半導体
チップ2の頭部に熱伝導性グリス10を薄く塗布し、ね
じ穴21と、穴26と、穴22とを位置合わせし、配線
基板4と、ヒートシンク7とを重ね合せる。コイルばね
24を装填したねじ23を穴22に入れ、ねじ止めによ
って配線基板4とヒートシンク7とをボス20の上に固
定すると、図2の放熱構造が得られる。半導体パッケー
ジ1に加わる荷重は、ばね24によって0.8kg〜
1.4kgの範囲に収められている。
A heat conductive sheet 6 is mounted around the semiconductor package 1 mounted on the wiring board 4. Next, the heat conductive grease 10 is thinly applied to the head of the semiconductor chip 2, the screw holes 21, the holes 26, and the holes 22 are aligned, and the wiring board 4 and the heat sink 7 are overlapped. When the screw 23 loaded with the coil spring 24 is inserted into the hole 22 and the wiring board 4 and the heat sink 7 are fixed on the boss 20 by screwing, the heat dissipation structure of FIG. 2 is obtained. The load applied to the semiconductor package 1 is 0.8 kg to
It is in the range of 1.4 kg.

【0023】実施の形態1における半導体パッケージの
放熱構造は、下記の特徴を有する。 (1)半導体パッケージ1からヒートシンク7への熱伝
導路は、半導体チップ2の頭部から熱伝導性グリス10
を経由するもの、半導体チップ2の側面から熱伝導シー
ト6を経由するもの、チップ基板3から熱伝導シート6
を経由するもの3通りの経路があること。 (2)半導体パッケージ1に加わる荷重は、ばね24に
よって均一化されており、かつ荷重をパッケージ基板3
全面積で受けるので、半導体チップ2に機械的損傷を及
ぼすことが少ないこと。
The heat dissipation structure of the semiconductor package according to the first embodiment has the following features. (1) The heat conduction path from the semiconductor package 1 to the heat sink 7 is formed from the head of the semiconductor chip 2 to the heat conductive grease 10.
Through the heat conductive sheet 6 from the side of the semiconductor chip 2, from the chip substrate 3 to the heat conductive sheet 6
There are three routes that go through. (2) The load applied to the semiconductor package 1 is made uniform by the spring 24 and the load is applied to the package substrate 3.
Since the semiconductor chip 2 is subjected to the entire area, the semiconductor chip 2 is hardly mechanically damaged.

【0024】次に、上記半導体パッケージ放熱構造に通
電して、半導体チップ2の内部温度を測定した結果を表
1に掲げる。
Next, the results of measuring the internal temperature of the semiconductor chip 2 by supplying electricity to the semiconductor package heat dissipation structure are shown in Table 1.

【0025】[0025]

【表1】 表1は、市販されているモバイルパソコンより半導体パ
ッケージ(CPU)を取り外し、代わりにサーマルパッ
ケージを取り付けたときの温度上昇の実測データであ
る。サーマルパッケージの構造は、寸法、熱特性がCP
Uに似せて作られており、内部に抵抗を内蔵している。
直流を通電することによって、CPUパッケージを使用
したときと同様な温度測定結果が得られる。
[Table 1] Table 1 shows measured data of temperature rise when a semiconductor package (CPU) is removed from a commercially available mobile personal computer and a thermal package is attached instead. The structure of the thermal package has the dimensions and thermal characteristics of CP
It is made to resemble U and has a built-in resistor inside.
By applying a direct current, the same temperature measurement result as when using the CPU package is obtained.

【0026】表1において使用した熱伝導性グリスは、
G765(信越化学工業、熱伝導率2.8W/mK)で
ある。熱伝導シートは2種類を用いた。表1で熱伝導シ
ート1と表記したものは、商品名サーコンGR−i(富
士高分子工業、熱伝導率5.6W/mK)、熱伝導シー
ト2と表記したものは、商品名FSB−A(電気化学工
業、熱伝導率8.0W/mK)である。ヒートシンクと
サーマルパッケージとの間の隙間に存在する熱伝導性グ
リスの厚みは、100μm以下である。CPU表面温度
は、サーマルパッケージに内蔵した表面近傍のセンサー
温度である。
The thermally conductive grease used in Table 1 is:
G765 (Shin-Etsu Chemical Co., Ltd., thermal conductivity 2.8 W / mK). Two types of heat conductive sheets were used. In Table 1, what is described as the heat conductive sheet 1 is the trade name Sarcon GR-i (Fuji Polymer Industries, thermal conductivity 5.6 W / mK), and what is described as the heat conductive sheet 2 is the trade name FSB-A. (Electrochemical industry, thermal conductivity 8.0 W / mK). The thickness of the thermally conductive grease existing in the gap between the heat sink and the thermal package is 100 μm or less. The CPU surface temperature is the temperature of the sensor near the surface built in the thermal package.

【0027】測定はモバイルパソコンの使用状態とし、
室温、事務机上に液晶パネルを開いた状態に置き、所定
のファン回転数とした。発熱量10.2Wより実験を開
始し、飽和温度を測定した。温度上昇が飽和した時点で
順次発熱量を増加させ、各発熱量に対する飽和温度を測
定した。
The measurement is performed using a mobile personal computer.
The liquid crystal panel was opened on the office desk at room temperature, and the fan rotation speed was set to a predetermined value. The experiment was started from a calorific value of 10.2 W, and the saturation temperature was measured. When the temperature rise was saturated, the calorific value was sequentially increased, and the saturation temperature for each calorific value was measured.

【0028】表1において、左より2番目欄、グリス塗
布のみとは、熱伝導シートを使用しない場合であり従来
技術での測定結果である。左より3番目欄〜5番目欄は
実施の形態1の放熱構造であり、3番目欄は、t=0.
7mmの熱伝導シート1を、4番目欄は、t=0.9m
mの熱伝導シート1を、5番目欄は、t=0.9mmの
熱伝導シート2を使用した場合である。表1の3〜5番
目欄の数値は、従来技術による飽和温度と実施の形態1
による飽和温度との差である。
In Table 1, the second column from the left, “only application of grease” refers to the case where a heat conductive sheet is not used, and is a measurement result in the prior art. The third to fifth columns from the left show the heat dissipation structure of the first embodiment, and the third column shows that t = 0.
7 mm heat conductive sheet 1, the fourth column is t = 0.9m
The fifth column shows the case where the thermal conductive sheet 1 of t = 0.9 mm is used. Numerical values in the third to fifth columns of Table 1 indicate the saturation temperature according to the conventional technique and the first embodiment.
Is the difference from the saturation temperature.

【0029】表1より、以下のことが明らかである。 (1)従来の放熱構造に比較して、0.5〜1.2℃飽
和温度をさげることができる。 (2)熱伝導率の高い熱導電シートを使用すると放熱効
果が大きい。 (3)熱導電シートの厚みによって放熱効果が異なり、
半導体チップの背の高さよりやや厚めのものがよい。な
お、実施の形態1の半導体チップ2の背の高さは0.8
5mmであるが、厚みが0.7mmの熱導電シートの場
合でも封止樹脂5によって底上げされて、半導体チップ
2の周辺部では熱導電シートの方が背が高いものと思わ
れる。 (4)発熱量が大きくなるに従い従来飽和温度と、本発
明の飽和温度との温度差が小さくなっているが、ヒート
シンクの冷却能力が限界に達したための現象であり、ヒ
ートシンク冷却能力を、ファンの回転数を増加するなど
して大きくすれば、従来と本発明との放熱効果の差はさ
らに顕著となるものと思われる。
From Table 1, the following is clear. (1) The saturation temperature can be reduced by 0.5 to 1.2 ° C. as compared with the conventional heat dissipation structure. (2) When a heat conductive sheet having a high heat conductivity is used, the heat radiation effect is large. (3) The heat radiation effect differs depending on the thickness of the heat conductive sheet.
It is preferable that the semiconductor chip is slightly thicker than the height of the semiconductor chip. The height of the semiconductor chip 2 of the first embodiment is 0.8
Although the thickness is 5 mm, even in the case of a heat conductive sheet having a thickness of 0.7 mm, the height is raised by the sealing resin 5, and the heat conductive sheet is considered to be taller around the semiconductor chip 2. (4) Although the temperature difference between the conventional saturation temperature and the saturation temperature of the present invention becomes smaller as the calorific value increases, this is a phenomenon because the cooling capacity of the heat sink has reached its limit. If the number of rotations is increased by increasing the number of rotations, it is considered that the difference in the heat radiation effect between the conventional and the present invention becomes more remarkable.

【0030】表1では従来例と比較した場合、最大1.
2℃の放熱効果が得られた。1.2℃の放熱効果は、従
来例の放熱構造でファンの回転数を200rpm程度早
くするのと同レベルの効果である。即ち、本発明の放熱
構造は、ファン回転数を遅くでき、これによりファンの
騒音を小さくでき(約1.5dBと見積もられる)、か
つファンの駆動電圧を下げることができる(約0.25
V見積もられる)ので、消費電力削減となり、バッテリ
ー駆動時間を延長することができる。
In Table 1, when compared with the conventional example, at most 1.
A heat radiation effect of 2 ° C. was obtained. The heat dissipation effect of 1.2 ° C. is the same level of effect as increasing the rotation speed of the fan by about 200 rpm in the heat dissipation structure of the conventional example. That is, the heat dissipation structure of the present invention can reduce the fan rotation speed, thereby reducing the noise of the fan (estimated to be about 1.5 dB) and reducing the drive voltage of the fan (about 0.25).
V is estimated), the power consumption is reduced, and the battery driving time can be extended.

【0031】なお、実施の形態1の熱導電シートは厚み
が均一のものを使用したが、封止樹脂の厚み分、熱導電
シートの下部に面取り処理をすれば、押圧力を均一にす
ることができ、さらに好結果が得られる。
Although the heat conductive sheet of the first embodiment has a uniform thickness, the pressing force can be made uniform by chamfering the lower portion of the heat conductive sheet by the thickness of the sealing resin. And good results can be obtained.

【0032】また、半導体パッケージに加える荷重は、
熱導電シートに荷重を加えたとき、熱導電シートの上面
が略半導体チップの表面高さにするのが適正荷重であ
る。
The load applied to the semiconductor package is
When a load is applied to the heat conductive sheet, the proper load is such that the upper surface of the heat conductive sheet is substantially at the surface height of the semiconductor chip.

【0033】なお、実施の形態では半導体パッケージと
して、モバイル用のCPUについて説明したが、金属パ
ッケージ、樹脂モールドパッケージ等についても、本発
明が効果があることは言うまでもない。
Although the embodiment has been described with respect to a mobile CPU as a semiconductor package, it goes without saying that the present invention is also effective for a metal package, a resin mold package, and the like.

【0034】また、ばね手段としてコイルばねを説明し
たが、コイルばねのかわりに、他のばねや弾性体を使用
しても同様な結果が得られる。
Although the coil spring has been described as the spring means, similar results can be obtained by using another spring or an elastic body instead of the coil spring.

【0035】[0035]

【発明の効果】本発明によれば、半導体パッケージとヒ
ートシンクの間の熱伝達効率を向上させることができ、
高性能、高発熱の半導体パッケージ対応した放熱構造を
とることができる。
According to the present invention, the heat transfer efficiency between the semiconductor package and the heat sink can be improved,
A heat dissipation structure corresponding to a semiconductor package with high performance and high heat generation can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施の形態1における半導体パッケージの放熱
構造を示す斜視図
FIG. 1 is a perspective view showing a heat dissipation structure of a semiconductor package according to a first embodiment.

【図2】実施の形態1における半導体パッケージの放熱
構造の断面図
FIG. 2 is a sectional view of a heat dissipation structure of the semiconductor package according to the first embodiment;

【図3】実施の形態1における放熱構造のばね手段の要
部を示す拡大断面図
FIG. 3 is an enlarged sectional view showing a main part of a spring means of the heat radiation structure according to the first embodiment.

【図4】半導体パッケージの構造の一例を示す断面図FIG. 4 is a cross-sectional view illustrating an example of the structure of a semiconductor package.

【図5】従来の半導体パッケージにおける放熱構造の一
例を示す断面図
FIG. 5 is a sectional view showing an example of a heat dissipation structure in a conventional semiconductor package.

【図6】従来の半導体パッケージにおける放熱構造の他
の一例を示す断面図(a)熱伝導シートの断面図 (b)放熱構造の断面図
FIG. 6 is a cross-sectional view showing another example of a heat dissipation structure in a conventional semiconductor package. FIG.

【符号の説明】[Explanation of symbols]

1 半導体パッケージ 2、51 半導体チップ 4、56 配線基板 6、60 熱伝導性シート 7、57 ヒートシンク 10、58 熱伝導性グリス DESCRIPTION OF SYMBOLS 1 Semiconductor package 2, 51 Semiconductor chip 4, 56 Wiring board 6, 60 Thermal conductive sheet 7, 57 Heat sink 10, 58 Thermal conductive grease

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 7/20 H05K 7/20 D Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H05K 7/20 H05K 7/20 D

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体チップを実装する配線基板と、前記
半導体チップの周囲を取巻く弾性を有する熱伝導体と、
半導体チップの上表面に塗布した熱伝導性グリスと、前
記熱伝導性グリスと対向するヒートシンクと、前記ヒー
トシンクと前記配線基板との間に設けたばね手段とより
なることを特徴とする半導体パッケージの放熱構造。
A wiring board on which a semiconductor chip is mounted; an elastic heat conductor surrounding the semiconductor chip;
Heat dissipation of a semiconductor package, comprising: heat conductive grease applied to an upper surface of a semiconductor chip; a heat sink facing the heat conductive grease; and a spring means provided between the heat sink and the wiring board. Construction.
【請求項2】熱伝導体の厚みが、半導体チップの背の高
さよりも厚いことを特徴とする請求項1に記載の半導体
パッケージの放熱構造。
2. The heat dissipation structure of a semiconductor package according to claim 1, wherein the thickness of the heat conductor is greater than the height of the semiconductor chip.
【請求項3】配線基板の筐体底面に設けたボスを基準と
して、配線基板とヒートシンクの間にばね手段を設けた
ことを特徴とする請求項2に記載の半導体パッケージの
放熱構造。
3. The heat dissipation structure for a semiconductor package according to claim 2, wherein a spring means is provided between the wiring board and the heat sink with reference to a boss provided on the bottom surface of the housing of the wiring board.
JP2000056795A 2000-03-02 2000-03-02 Heat dissipating structure of semiconductor package Pending JP2001244394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000056795A JP2001244394A (en) 2000-03-02 2000-03-02 Heat dissipating structure of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000056795A JP2001244394A (en) 2000-03-02 2000-03-02 Heat dissipating structure of semiconductor package

Publications (1)

Publication Number Publication Date
JP2001244394A true JP2001244394A (en) 2001-09-07

Family

ID=18577682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000056795A Pending JP2001244394A (en) 2000-03-02 2000-03-02 Heat dissipating structure of semiconductor package

Country Status (1)

Country Link
JP (1) JP2001244394A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100921370B1 (en) * 2001-12-27 2009-10-14 폴리마테크 컴퍼니 리미티드 Apparatus and method for cooling electronic components and thermally conductive sheet and method for producing thermally conductive sheet for use therewith
JP2010194894A (en) * 2009-02-25 2010-09-09 Brother Ind Ltd Electronic component heat radiation structure, manufacturing method therefor, and liquid delivery device
DE102010017814A1 (en) 2009-07-14 2011-02-03 Denso Corporation, Kariya-City Electronic control unit
US7903425B2 (en) 2006-06-27 2011-03-08 Lenovo (Singapore) Pte. Ltd. Integrated circuit chip thermal solution

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100921370B1 (en) * 2001-12-27 2009-10-14 폴리마테크 컴퍼니 리미티드 Apparatus and method for cooling electronic components and thermally conductive sheet and method for producing thermally conductive sheet for use therewith
US7903425B2 (en) 2006-06-27 2011-03-08 Lenovo (Singapore) Pte. Ltd. Integrated circuit chip thermal solution
JP2010194894A (en) * 2009-02-25 2010-09-09 Brother Ind Ltd Electronic component heat radiation structure, manufacturing method therefor, and liquid delivery device
DE102010017814A1 (en) 2009-07-14 2011-02-03 Denso Corporation, Kariya-City Electronic control unit
US8243454B2 (en) 2009-07-14 2012-08-14 Denso Corporation Electronic control unit

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