JP2001244335A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the semiconductor device which make it possible to obtain a good contact performance by minute contact. SOLUTION: An interlayer insulating film 15 is formed on a semiconductor substrate 11 on which a transistor is formed, and on the top of the interlayer, wiring 18 is formed. As for contact hole 16 for connecting the wiring 18 to a diffused layer 14, an aspect ratio is 3 or higher, and a polycrystalline silicon layer 17 is buried in this contact hole 16 flatly. The polycrystalline silicon layer 17 consists of a first deposition layer of the polycrystalline silicon, which adsorbs impurity, and a second deposition layer of polycrystalline silicon layer, which is heat treated to make impurity distribution uniform ahead of etching back by CDE.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement in a wiring contact portion having a high aspect ratio.

[0002]

2. Description of the Related Art In recent semiconductor integrated circuits, the diameter of wiring contacts has become smaller and the aspect ratio has become larger with the miniaturization of elements, resulting in problems such as poor contact and increase in contact resistance. The aspect ratio of the contact hole refers to the ratio of the depth to the diameter of the contact hole. When the aspect ratio is increased, the contact plug burying property is reduced, so that a contact failure occurs.

On the other hand, in order to prevent the occurrence of junction leak or the like due to etching of the interlayer insulating film, a method of burying polycrystalline silicon or the like in a fine contact hole formed in the interlayer insulating film is usually adopted. Specifically, after forming a contact hole in the interlayer insulating film, a polycrystalline silicon layer is deposited and etched back to bury the polycrystalline silicon in the contact hole. After that, a metal wiring is formed.

[0004]

However, when polycrystalline silicon is buried in the contact hole, a step is often formed on the surface of the buried layer. In particular, when the impurity concentration distribution of the buried polycrystalline silicon layer is non-uniform, a CDE (Chemical Dry Etchi) is used.
Since the etching rate of the polycrystalline silicon is not uniform in the etch-back step by the ng) method, a large step is formed. When a step occurs in the buried contact layer, various inconveniences occur. This will be described with reference to FIGS.

FIGS. 10 to 13 show a state in which a contact hole 2 is formed in an interlayer insulating film 1 and a polycrystalline silicon layer 3 is buried therein. For example, FIG. 10 shows a state in which the etch back amount of the polycrystalline silicon layer 3 is insufficient and the upper surface of the polycrystalline silicon layer 3 protrudes from the upper surface of the insulating film 1. In this case, when the wiring 5 is formed via the barrier metal 4, the polycrystalline silicon layer 3 penetrates the wiring 5 when the wiring 3 is thin. In this case, the wiring resistance becomes large.

On the contrary, the example shown in FIG. 11 is a case where the amount of etch back of the polycrystalline silicon layer 3 is too large. In this case,
The step on the side wall of the contact hole becomes large, the coverage of the barrier metal 4 becomes insufficient, and a contact failure of the wiring 5 occurs. If the step due to the non-uniformity of the etch-back of the polycrystalline silicon layer 3 is large, the window width with respect to the optimum amount of the etch-back for avoiding the failure modes shown in FIGS. 10 and 11 becomes narrow, resulting in a decrease in the contact yield.

FIG. 12 shows that two types of insulating films 1 are used for the interlayer insulating film 1.
a and 1b show the case of a laminated structure. Such a structure is often used to improve the burying property and flatness of the interlayer insulating film 1, but a coarse film having a high etching rate is particularly used for the first insulating film 1a. In this case, if the etch back amount of the polycrystalline silicon layer 3 buried in the contact hole 3 is large, the first-layer insulating film 1a may move in the lateral direction as shown in the drawing when wet etching is performed as a pretreatment for forming the barrier metal. Etched. This causes a short circuit between adjacent contacts, and makes it impossible to arrange contacts at a fine pitch.

FIG. 13 shows a polycrystalline silicon layer 3 to be embedded.
1 shows a case where a seam (cavity) is formed. If the contact hole 2 has a high aspect ratio of, for example, 3 or more, it is difficult to fill the contact hole 2, and the formation of such a seam 6 cannot be avoided. When such a seam 6 exists, the seam 6 is exposed even if the amount of the etch back of the polycrystalline silicon layer 3 is slightly too large. When the seam 6 is exposed, the etching of the polycrystalline silicon layer 3 proceeds at a stretch, and a situation occurs in which the polycrystalline silicon layer does not remain in the contact hole 2.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of obtaining good contact performance with fine contacts, and a method of manufacturing the same.

[0010]

A semiconductor device according to the present invention comprises a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a contact hole having an aspect ratio of 3 or more formed in the insulating film. And a wiring formed on the insulating film and electrically connected to the semiconductor substrate via the polycrystalline silicon layer. Features.

According to the present invention, the polycrystalline silicon layer is formed in the contact hole having a large aspect ratio of 3 or more with a surface step of 3.
It is embedded in a flat state of 0 nm or less. Such flatness of the buried polycrystalline silicon layer can be achieved by selecting burying conditions that eliminate the nonuniformity of the etch-back amount caused by the nonuniformity of the impurity distribution of the polycrystalline silicon layer. When the polycrystalline silicon layer is buried with good flatness in this manner, the polysilicon wiring does not penetrate through the wiring as shown in FIG. 10 and the disadvantage due to the deep etching of the side wall as shown in FIG. 11 or FIG. Is also eliminated. Further, the window width of the etch-back amount determined by the failures shown in FIGS. 10 and 11 becomes wider.
Also, when a seam is formed as shown in FIG.
A polycrystalline silicon burying layer that does not expose the seam can be obtained.

The present invention also provides a step of forming an insulating film on a semiconductor substrate, a step of forming a contact hole in the insulating film, a step of embedding a polycrystalline silicon layer in the contact hole, Forming a wiring so as to be electrically connected to the semiconductor substrate via a contact layer, wherein the step of embedding the polycrystalline silicon layer comprises the step of:
Depositing a second polycrystalline silicon layer to which no impurities are added so as to overlap the first polycrystalline silicon layer; and depositing a first polycrystalline silicon layer and a second polycrystalline silicon layer. A heat treatment step of diffusing the impurity into the polycrystalline silicon layer; and etching back the second polycrystalline silicon layer and the first polycrystalline silicon layer by chemical dry etching so that the upper surface becomes flat. And leaving a hole in the hole.

It is not preferable to embed impurity-doped polycrystalline silicon in a single deposition step in a contact hole having a high aspect ratio because it takes too much deposition time. On the other hand, if a polycrystalline silicon layer not doped with an impurity is deposited in one deposition step and then the impurity is to be doped, the aspect ratio is particularly 3 or more and the diameter is 250 n.
It is difficult to sufficiently diffuse impurities into the inside of a contact hole as small as m or less. Therefore, in the method of the present invention, two-stage polycrystalline silicon deposition is performed.

At this time, the non-uniformity of the impurity concentration distribution of the polycrystalline silicon layer causes the non-uniformity of the etch-back amount in the subsequent etch-back step by CDE. Therefore, in the present invention, heat treatment is performed after the deposition of the two polycrystalline silicon layers to make the impurity distribution uniform, and then etchback by CDE is performed. Thereby, the polycrystalline silicon layer can be embedded in the contact hole without any step.

The present invention further comprises a step of forming an insulating film in the semiconductor substrate, a step of forming a contact hole in the insulating film, a step of embedding a polycrystalline silicon layer in the contact hole, Forming a wiring so as to be electrically connected to the semiconductor substrate via a contact layer, wherein the step of embedding the polycrystalline silicon layer comprises the step of: Depositing a crystalline silicon layer, depositing a second polycrystalline silicon layer to which no impurities are added over the first polycrystalline silicon layer, and depositing the second polycrystalline silicon layer and the first polycrystalline silicon layer. Etch back the crystalline silicon layer by chemical dry etching with conditions set so that the etching rate is not affected by the impurity concentration,
Leaving the contact hole in the contact hole so that the upper surface becomes flat.

As described above, even if the impurity concentration distribution of the polycrystalline silicon layer in the contact hole has non-uniformity, the CDE is set so as not to be affected by the impurity concentration.
, The polycrystalline silicon layer can be embedded in the contact hole without any surface step.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. A gate electrode 13 is provided on a semiconductor substrate 11 via a gate insulating film 12.
Are formed, and a source / drain diffusion layer 14 self-aligned with the gate electrode 13 is formed, thereby completing a MOS transistor.

Substrate 11 on which MOS transistors are formed
An interlayer insulating film 15 is deposited thereon, and a metal wiring 18 is formed thereon. A contact hole 16 is formed in the interlayer insulating film 15, and a polycrystalline silicon layer 17 is buried in the contact hole 16. Contact hole 6
In this embodiment, the aspect ratio is 3 or more, for example, 4. The diameter of the contact hole 6 (the diameter in the minor axis direction in the case of an elliptical shape) is 250 nm or less. Sub μm
It is inevitable to use such a fine contact hole 6 having a high aspect ratio in order to highly integrate the fine element. The metal interconnection 18 is
Is connected to the diffusion layer 14 via the.

FIG. 2 shows that a barrier metal 19 is actually provided at the interface between the wiring 18 and the polysilicon layer 17 in FIG. 1 as shown in FIG. When the metal wiring 8 is a tungsten film, TiN or the like is used as the barrier metal 19. If the impurity concentration of the buried polycrystalline silicon layer 17 is low at the center in the radial direction of the contact hole 16 and high at the periphery, the etching amount in the periphery in the etch-back process is large, so that a large step is formed on the upper surface. . In this embodiment, the step D on the upper surface is suppressed to 30 nm or less by improving the embedding condition.

The planar shape of the contact hole 16 may be a circle as shown in FIG. 3A or an elliptical shape as shown in FIG. 3B.

A specific manufacturing process for obtaining the contact structure shown in FIGS. 1 and 2 will now be described. FIG. 4 (a)
(D) are an example of the manufacturing process. Here, a step of burying the polycrystalline silicon layer 17 in the contact hole 17 by a double damascene method and burying a tungsten wiring as the wiring 18 is shown.

As shown in FIG. 4A, RIE (React) which is anisotropic dry etching
The contact hole 16 and the wiring groove 21 overlapping with the contact hole 16 are formed by using Ion Etching. Thereafter, a polycrystalline silicon layer 17 is deposited as shown in FIG. Specifically, the polycrystalline silicon layer 17 includes a first polycrystalline silicon layer 17a and a second polycrystalline silicon layer 17b.
Of a laminated structure. Impurities are adsorbed to the first polycrystalline silicon layer 17a after the deposition. Alternatively, impurities may be doped simultaneously with the deposition of the first polycrystalline silicon layer 17a. The second polycrystalline silicon layer 17b is a film not doped with impurities.

The reason why such two-stage film deposition is performed is to diffuse impurities to the inside of the contact hole 16. That is, even if a polycrystalline silicon layer is deposited in one step and impurities are to be doped thereafter, it is difficult to deeply diffuse the impurities into a small-diameter contact having a high aspect ratio, and a low-resistance contact cannot be obtained. Also, in the method of doping impurities simultaneously with the film deposition, the film deposition rate becomes slow, which is a practical problem.

However, unless heat treatment is performed, the impurity concentration distribution of the polycrystalline silicon layer 17 buried in the contact hole 16 will not be uniform. In this embodiment, a heat treatment is performed prior to the next etch-back step to remove impurities adsorbed on first polycrystalline silicon layer 17a into first and second polysilicon layers 17a.
Is thermally diffused into the polycrystalline silicon layer 17b to uniform the impurity concentration inside the contact hole.

Thereafter, etch back is performed by CDE, and a polycrystalline silicon layer 17 is buried in the contact hole 16 as shown in FIG. As described above, since the impurity concentration distribution of the polycrystalline silicon layer 17 is previously made uniform, the in-plane uniformity of the etch-back by CDE is improved, and the step on the upper surface of the embedded polycrystalline silicon layer 17 is 30 nm. The following can be small.

Thereafter, as shown in FIG. 4C, a tungsten (W) layer is deposited via the barrier metal 19, and the tungsten layer is etched back to bury the tungsten wiring 18 in the wiring groove 21.

As described above, according to this embodiment, the upper surface can be made substantially flat by making the impurity concentration of the polycrystalline silicon layer embedded in the fine contact hole having a large aspect ratio substantially uniform. Therefore, FIG.
As shown in FIG. 1, there is no occurrence of wiring penetration of polysilicon. Further, the inconvenience caused by the deep etching of the contact side wall as shown in FIG. 11 or FIG. 12 is also solved. In addition, since the surface flatness is improved, FIG.
The window width of the etch-back amount for avoiding the defective mode of FIG. 11 and the defective mode of FIG. 11 is increased. Further, in the case of a contact hole having a high aspect ratio, a seam is often formed in the buried polycrystalline silicon layer as shown in FIG. 13, but according to this embodiment, polycrystalline silicon burying that does not expose the seam is used. Will be possible.

Another contact embedding step will be described with reference to FIGS. In the above embodiment, FIG.
In the step (b), the impurity distribution was made uniform by heat treatment. On the other hand, in this embodiment, the heat treatment is not performed, and instead, the etching condition by CDE is set so as not to be affected by the impurity concentration distribution. Etching back by CDE with the etching conditions set in this way is performed, and the polycrystalline silicon layer 17 is buried in the contact hole 16 as shown in FIG. Thereafter, as shown in FIG. 4C, a tungsten wiring 18 is buried.

According to this embodiment, the polycrystalline silicon layer 17 has a surface step of 30 nm as in the previous embodiment.
The contact hole 16 can be embedded in the following substantially flat state. Also in the case of this embodiment, the impurity of the first polycrystalline silicon layer 17a is changed to the second polycrystalline silicon layer 1a.
A heat treatment step for diffusing the tungsten 7b is necessary, and may be performed, for example, after the tungsten wiring 18 is buried.

Next, an embodiment in which the present invention is applied to a NAND type EEPROM will be described with reference to FIGS. FIG. 5 is an equivalent circuit of a cell array of the NAND type EEPROM. A plurality of stacked-gate memory cells MC are connected in series to form a NAND cell unit. One end of the NAND cell unit is connected to the bit line BL via the select gate transistor SG1, and the other end is also connected to the common source line S via the select gate transistor SG2.
L. The control gates of the memory cells MC arranged in the row direction are commonly connected to a control gate line (word line) CG.

FIG. 6 shows a cross-sectional structure of the NAND cell unit along the bit line BL direction. FIG. 7 shows a layout near the bit line contact. 6 and 7 show a state where the tungsten (W) buried wiring 41 is formed before the aluminum (Al) wiring to be the bit line BL is formed. The cell array is formed in a p-type well of the silicon substrate 31. The memory cell MC has a floating gate 33 formed on a substrate 31 with a tunnel insulating film 32 interposed therebetween, and a control gate 35 formed on the floating gate 33 with an insulating film 34 interposed therebetween. Source / drain diffusion layers 36 are formed in the control gate 35 in a self-aligned manner. The floating gate 33 is separated for each memory cell MC, and the control gate 35 is a control gate line CG formed continuously.

The surface on which the memory cells MC are formed is covered with an interlayer insulating film 37. In this interlayer insulating film 37, a contact hole 38 for the diffusion layer 36 and a wiring burying groove 39 are formed by the damascene method, and the polycrystalline silicon layer 40 and the tungsten wiring 41 are buried.
The aluminum (Al) bit line is disposed on the tungsten wiring 41 via an interlayer insulating film so as to connect the tungsten wiring 41 of each bit line contact portion, as indicated by the dashed line in FIG. .

Polycrystalline silicon layer 4 in contact hole 38
The step described with reference to FIGS. 4A to 4D is used for the step of burying 0, and the upper surface of the buried polycrystalline silicon layer 40 has flatness with almost no steps. As shown in FIG. 7, a large number of bit line contacts are formed in a line at the pitch of the bit lines BL. In order to secure the space between adjacent contacts and arrange the bit line contacts at a fine bit line pitch, in the example of FIG. 7, the planar shape of the contact hole 17 is changed to an ellipse in which the contact arrangement direction is a short axis. And

In a NAND type EEPROM, the channel resistance and diffusion layer resistance of a plurality of memory cells enter the bit line in series when reading data, so that the series resistance of the bit line is high and the bit line current is originally small. In particular, when the contact resistance of the bit line increases, the bit line current further decreases, and good read characteristics cannot be obtained. In addition, since the bit line contacts are arranged in a line at a fine pitch as shown in FIG. 7, there is no room for increasing the contact diameter, and since the memory cell has a stacked gate structure, the interlayer insulating film becomes thick. In addition, the bit line contact has to be as fine as 3 or more in aspect ratio and 250 nm or less in diameter.

According to the present invention, a contact hole having a high aspect ratio is formed without increasing the diameter of the upper end opening as described above, and a contact having a small diameter and a low resistance can be obtained. Therefore, the present invention is applied to a NAND type EEPROM.
The effect of applying to the M bit line contact is great.

The present invention is not limited to the above embodiment.
For example, although the embodiments described so far show a structure in which a metal wiring is brought into contact with a diffusion layer of a substrate, the present invention can be applied to other contact structures. For example, FIG. 9 shows a case where the present invention is applied to a portion where a metal wiring 18 is brought into contact with a gate electrode 42 of a MOS transistor 41 formed on a semiconductor substrate 40. FIG. 10 shows a case where the present invention is applied to a via contact portion for interconnecting multilayer wirings. That is, the MOS transistor 41 formed on the semiconductor substrate 40 is covered with the first interlayer insulating film 51, on which the first-layer metal wiring 53 is formed. The same structure as that of the embodiment of FIG. 1 is applied to the contact portion of the second-layer metal wiring 18 to the first-layer metal wiring 53.

In each of FIGS. 9 and 10, excellent contact characteristics can be obtained by using the same step as that of the previous embodiment for the step of embedding the polycrystalline silicon layer 17 in the contact hole 16.

[0038]

As described above, according to the present invention, a polycrystalline silicon layer is buried in a contact hole having a high aspect ratio with good flatness in consideration of an etch-back process, thereby providing good contact performance with fine contact. , And an excellent effect can be obtained particularly when applied to a highly integrated semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a contact structure according to an embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a contact portion according to the embodiment.

FIG. 3 is a diagram showing a contact hole shape according to the embodiment.

FIG. 4 is a cross-sectional view showing an example of a contact embedding step of the embodiment.

FIG. 5 is a NAND EEPROM according to another embodiment;
Is an equivalent circuit.

FIG. 6 is a view showing a sectional structure of the NAND type EEPROM.

FIG. 7 is a diagram showing a layout of the NAND type EEPROM.

FIG. 8 is a sectional view showing another example of the contact structure according to the present invention.

FIG. 9 is a sectional view showing another example of the contact structure according to the present invention.

FIG. 10 is a cross-sectional view showing a conventional contact structure.

FIG. 11 is a cross-sectional view showing a conventional contact structure.

FIG. 12 is a cross-sectional view showing a conventional contact structure.

FIG. 13 is a cross-sectional view showing a conventional contact structure.

[Explanation of symbols]

11: semiconductor substrate, 14: diffusion layer, 15: interlayer insulating film,
16 contact holes, 17 (17a, 17b) polycrystalline silicon layer, 18 metal wiring.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kenji Matsuzaki 800, Nakaryumiya, Yonoichi, Mika 800 Zhongryu Palace F-term in Toshiba Yokkaichi Plant Co., Ltd. QQ59 QQ73 QQ80 VV16 WW01 XX02 5F083 EP02 EP23 EP32 EP76 JA39 JA40 KA05 LA12 LA21 MA06 MA16 MA20 PR03 PR33 PR39

Claims (4)

[Claims] A semiconductor substrate, an insulating film formed on the semiconductor substrate, and a contact hole with an aspect ratio of 3 or more formed in the insulating film are buried so that a step on the upper surface is 30 nm or less. A semiconductor device comprising: a polycrystalline silicon layer; and a wiring formed over the insulating film and electrically connected to the semiconductor substrate via the polycrystalline silicon layer. 2. The semiconductor device according to claim 1, wherein the diameter of said contact hole is 250 nm or less. A step of forming an insulating film on the semiconductor substrate; a step of forming a contact hole in the insulating film; a step of embedding a polycrystalline silicon layer in the contact hole; Forming a wiring so as to be electrically connected to the semiconductor substrate via the semiconductor substrate. The step of embedding the polycrystalline silicon layer, the method comprising: Depositing a layer, depositing a second polysilicon layer to which impurities are not added over the first polysilicon layer, and a first polysilicon layer and a second polysilicon layer A heat treatment step of diffusing the impurity into the second layer; and etching back the second polycrystalline silicon layer and the first polycrystalline silicon layer by chemical dry etching. The method of manufacturing a semiconductor device characterized by a step of leaves in the contact hole such that the flat. A step of forming an insulating film on the semiconductor substrate; a step of forming a contact hole in the insulating film; a step of embedding a polycrystalline silicon layer in the contact hole; and forming the contact layer on the insulating film. Forming a wiring so as to be electrically connected to the semiconductor substrate through the semiconductor device, wherein the step of embedding the polycrystalline silicon layer comprises the step of: Depositing a second polycrystalline silicon layer to which no impurity is added, overlying the first polycrystalline silicon layer; and depositing the second polycrystalline silicon layer and the first polycrystalline silicon layer. Is etched back by chemical dry etching in which the etching rate is not affected by the impurity concentration, so that the upper surface becomes flat. The method of manufacturing a semiconductor device characterized by a step of leaving the Ntakuto hole.