JP2001244333A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor integrated circuit device which improves a manufacturing margin in an wiring process and eliminates a large area pad exclusively used for connecting wires between a substrate and a semiconductor chip, by easily realizing a complete flatness of the surface of a substrate and semiconductor chip when arranging the semiconductor chip in a groove provided in a substrate such as a wafer. SOLUTION: A thick dielectric film is accumulated on a wafer surface after forming a groove in the wafer and arranging a semiconductor chip in the groove. Then, the dielectric film on the wafer surface is polished with the known CMP technique to realize complete flatness easily. As ruggedness of the wafer surface can be made smaller than a focal depth of an optical system in photolithography, a margin for focusing can be made large, and respective optional points of the first semiconductor chip and the second semiconductor chip can be connected accurately with a photolithographic technique. This method makes it possible to connect wires without using a large area pad exclusively used for connecting wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a plurality of semiconductor integrated circuits having different functions and a plurality of semiconductor chips having different functions being mixed. The present invention relates to a method for manufacturing a semiconductor integrated circuit device such as a multichip module.

[0002]

2. Description of the Related Art Conventionally, this kind of semiconductor integrated circuit device has
A plurality of semiconductor chips having different functions, such as a CPU, a RAM, a ROM, and a gate array, are mixedly mounted on a single wafer or substrate to realize a desired system as a single module.

[0003] For example, "June 1989, IEE
EE Transactions on Components Hybrids and Manufacturing Technology, Vol. 12, No. 2, June 1989 (I
EEE TRANSACTIONS ON COMPO
NENTS, HYBRIDS, AND MANUFAC
TURING TECHNOLOGY, VOL. 12,
NO. 2, JUNE 1989) "on pages 185 to 194 show an example of a multi-chip module in which semiconductor chips are mixedly mounted on a substrate made of a silicon wafer. In this document, first, a groove having substantially the same size as a semiconductor chip is formed on a main surface of a substrate by a known etching technique. next,
When embedding a semiconductor chip in this groove, each of the semiconductor chip main surface and the substrate main surface is arranged downward with respect to a flatness adjusting substrate such as a glass plate, and the main surface height is adjusted. In this state, a fixing material is injected into a groove between the substrate and the semiconductor chip to fix the semiconductor chip. Next, an insulating film is deposited on the substrate, and wiring connection is performed between wiring connection pads arranged on the main surface of the semiconductor chip and the main surface of the substrate using a known wiring forming process, A method for manufacturing a multi-chip module has been proposed.

[0004] However, the above-mentioned conventional method has the following disadvantages.

A first problem is that when arranging a semiconductor chip in a groove provided in a substrate, it is difficult to secure flatness between the main surface of the substrate and the main surface of the semiconductor chip.

The reason is that a flatness adjusting substrate is used to adjust the height of the main surface of the substrate and the semiconductor chip, and the main surfaces of the substrate and the semiconductor chip are respectively adjusted with respect to the flatness adjusting substrate. This is because the flatness is adjusted by arranging it downward. Therefore, when the main surface of the substrate or the semiconductor chip has irregularities, the flatness of both may not be realized, and the semiconductor chip may be arranged at an angle.

The second problem is that wiring is connected between the chips via the wiring connection pads, so that the parasitic capacitance at the wiring connection pad portion is increased, the power consumption during signal propagation is increased, and high-speed operation is performed. Is difficult.

[0008] The reason is that the wiring connection between the substrate and the semiconductor chip cannot be performed with high precision, and it is necessary to secure a manufacturing margin by using a dedicated pad having a large area for performing the wiring connection. It is.

A third problem is that a dedicated area for arranging wiring connection pads is required, and the size of the multichip module is increased.

[0010] The reason is that the wiring connection between the substrate and the semiconductor chip cannot be performed with high accuracy, and it is necessary to secure a manufacturing margin by using a dedicated pad having a large area for performing the wiring connection. It is.

A fourth problem is that the wafer on which the wiring connection pads are arranged is used only for wiring connection, and the size of the multi-chip module cannot be reduced.

[0012] The reason is that the wiring connection cannot be performed with high precision, so that it is necessary to use a dedicated wafer for performing the wiring connection in order to form a multi-chip module.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to increase the manufacturing margin in the wiring step and to mix semiconductor chips having different functions. It is to provide productivity improvement.

Another object of the present invention is to reduce the power consumption of a semiconductor integrated circuit device which does not require a flatness adjustment substrate, wiring connection pads, and a wiring connection wafer, and incorporates semiconductor chips having different functions. Another object of the present invention is to provide high speed and small size.

Another object of the present invention is to provide a high-performance semiconductor integrated circuit device in which a semiconductor chip having an active element or a passive element manufactured by an optimum method is mounted and semiconductor chips having different functions are mounted. It is in.

[0016]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, in a first aspect of the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of digging a groove in a wafer on which a first semiconductor chip is formed, and disposing a second semiconductor chip in the groove are provided. A step of, after arranging the second semiconductor chip in the groove, a step of covering the surface of the wafer with an insulating film, a step of planarizing the surface of the wafer covered with the insulating film, and a step of: And a step of connecting the second semiconductor chip with a conductor. The second aspect is a step of connecting the second semiconductor chip to the wafer on which the first semiconductor chip is formed, The semiconductor chip is characterized in that it is manufactured by different manufacturing steps, and the third aspect is a step of digging a plurality of grooves in a wafer on which the first semiconductor chip is formed, The second semiconductor And a step of depositing an insulating film on side walls and a bottom of the groove, and a step of disposing an insulating film on the side wall and the bottom of the groove. And disposing the second semiconductor chip in a groove in which a film is deposited. In a fifth aspect, the inside of the first semiconductor chip is wired with a conductor. A sixth aspect is characterized in that the sixth aspect includes a step of wiring and connecting the inside of the second semiconductor chip with a conductor. According to a seventh aspect, in the step of flattening the wafer surface, CMP (Chemica) is used.
This is characterized by flattening by a (Mechanical Polishing) technique.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: digging a groove in a wafer on which a first semiconductor chip is formed; and arranging a second semiconductor chip in the groove. After arranging the second semiconductor chip in the groove, covering the surface of the wafer with an insulating film, planarizing the wafer surface covered with the insulating film,
Connecting the semiconductor chip and the second semiconductor chip with a conductor.

With the above configuration, the unevenness of the wafer surface can be made smaller than the depth of focus of the optical system in photolithography, so that a large margin for focusing can be obtained, and the first semiconductor chip and the second semiconductor chip can be used. Wiring can be accurately connected between the arbitrary portions by using photolithography technology. Therefore, wiring connection can be performed without using a wiring connection pad having a large area.

Further, since the connection between chips and the wiring inside the chip can be formed in the same wiring step, the manufacturing process can be shortened.

Further, since the first semiconductor chip and the second semiconductor chip can be formed halfway in different manufacturing steps,
For example, it is possible to form sensitive active or passive devices that exhibit characteristic fluctuations due to processes using high temperatures and active or passive devices that need to be manufactured using high temperatures in separate manufacturing processes. In the case where these two types of active elements or passive elements are mixed, deterioration of sensitive active elements or passive elements can be prevented, and a high-performance semiconductor integrated circuit device can be realized.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Next, a first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a plan view for explaining a method of manufacturing a semiconductor integrated circuit device as a first specific example of the present invention.

In a plurality of first semiconductor chips 2 formed on the surface of the wafer 1, a second semiconductor chip 3 is embedded in a desired region of the first semiconductor chip 2, and the first semiconductor chip 3 is formed by a known wiring technique. By performing wiring connections between the semiconductor chip 2 and the second semiconductor chip 3, inside the first semiconductor chip 2, and inside the second semiconductor chip 3, the second semiconductor chip 3 is connected to the first semiconductor chip 2. In a semiconductor integrated circuit device.

FIGS. 2A to 2D are cross-sectional views showing a main part of a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. As shown in FIG. 2A, a first active element (Metal Oxide) including, for example, a gate electrode 4, a diffusion layer region 5, and an element isolation region 6 is formed on a wafer 1 constituting a first semiconductor chip 2. Semiconduc
After forming a tor transistor (hereinafter, referred to as a MOS transistor), an insulating film 7 is deposited on the wafer 1. Next, as shown in FIG. 2B, the photoresist 9 in the region 8 where the second semiconductor chip 3 is arranged is removed by using a known photolithography technique. Next, as shown in FIG. 2C, the insulating film 7 and the wafer 1 are etched by a known etching technique using the photoresist 9 as a mask to form a groove 10. The desired depth of the groove 10 can be formed by adjusting the etching time. Also, the opening width of the groove 10 can be formed to a desired size, for example, the opening is slightly larger than the second semiconductor chip 3. Next, FIG.
As shown in FIG. 1D, a gate electrode 12 of the second semiconductor chip, a diffusion layer region 13 of the second semiconductor chip, and a second semiconductor chip element isolation region 14 are formed on a substrate 11 of the second semiconductor chip. After the second active element (MOS transistor) to be formed is formed by a manufacturing method different from that of the first active element (MOS transistor), an insulating film 15 is deposited, cut into a desired size, and cut into a desired size. To form Next, a fixing member 16 for fixing the chip is attached to the back surface of the second semiconductor chip 3. As the fixing material, for example, a heat-resistant synthetic resin such as an epoxy resin that can withstand the temperature used in a known wiring technique is used.

FIG. 3 is a plan view for explaining an alignment method when arranging the second semiconductor chip 3 in the groove 10 of the first semiconductor chip 2. As shown in FIG. 3, the first semiconductor chip 2
Alignment patterns 17 are arranged on four sides around the upper groove 10, and alignment patterns 18 are arranged on four sides on the second semiconductor chip 3. As the alignment pattern, for example, a line pattern or the like formed by the gate electrode 4 is used. By arranging the second semiconductor chip 3 in the groove 10 by using the alignment pattern as described above, it is possible to reduce the amount of misalignment of the second semiconductor chip 3 to about 1 μm or less.

FIGS. 4 to 6 are cross-sectional views showing the main parts of the manufacturing method after the second semiconductor chip 3 is buried in the groove 10. As shown in FIG. 4A, after the second semiconductor chip 2 is fixed in the groove 10, an insulating film 19 having good embedding property is deposited on the surface of the wafer 1. The deposited film thickness of the insulating film 19 is
The adjustment is performed according to the thickness of the second semiconductor chip 3. next,
As shown in FIG. 4B, a known CMP (Chemic) is used.
The surface of the wafer 1 having high flatness is formed while polishing the insulating film 19 on the surface of the wafer 1 by using an al mechanical polishing technique, and the insulating film 19 is polished to a desired thickness. Regarding the flatness, the unevenness of the insulating film 19 on the surface of the wafer 1 can be reduced to about 0.10 μm or less. As described above, the unevenness on the surface of the wafer 1 can be made equal to or less than the depth of focus of the optical system of the apparatus used in the known photolithography technology, and the margin for focusing at the time of pattern formation using the photolithography technology can be increased. Next, as shown in FIG. 4C, in order to form a contact for wiring connection in a desired region, the photoresist in the contact formation region 20 is removed by a photolithography technique, and the photoresist 6 is used as a mask. The insulating film 19 is etched to form a contact hole 21 in the insulating film 19. Next, as shown in FIG. 5E, a contact 22 is formed by embedding a conductive material in the contact hole 21. Next, as shown in FIG. 5 (f), after a conductive material 23 is deposited on the surface of the wafer 1, as shown in FIG. 6 (g), the first inside of the first semiconductor chip 2 is formed by photolithography. The photoresist in the region where the wiring and the first wiring inside the second semiconductor chip 3 and the first wiring between the first semiconductor chip 2 and the second semiconductor chip 3 are formed is removed. Using the photoresist as a mask, the conductive material is etched to form a first wiring 25 inside the first semiconductor chip 2 and a first wiring 26 inside the second semiconductor chip 2 made of the conductive material, and a first semiconductor chip. The first wiring 27 between the second semiconductor chip 3 and the second semiconductor chip 3 is formed. Next, as shown in FIG. 6I, an insulating film 28 is deposited. Here, the formation up to the first wiring is shown, but the second wiring is formed.
Subsequent wiring can be formed by the same manufacturing process. (Second Specific Example) Next, a second specific example of the present invention will be described in detail with reference to FIG.

FIGS. 7A to 7C are cross-sectional views showing a main part of a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. Until the groove 10 is formed, the same manufacturing method as in the first specific example is used. As shown in FIG.
After the formation, an insulating film 29 is deposited on the surface of the wafer 1 and the grooves 10 are formed.
An insulating film 29 is formed on the side wall and the bottom of the substrate. Next, the second semiconductor chip 3 in a chip state is diced in advance in this groove. In the subsequent steps, wirings are formed as in the first embodiment of the present invention. As described above, the insulating film 29 is formed on the side walls and the bottom of the groove 10 of the first semiconductor chip 2, and the second semiconductor chip 3 is buried in the groove 10.
Can be electrically separated from each other, and the first semiconductor chip 2
Between the first semiconductor chip 3 and the second semiconductor chip 3 via the substrate.

[0029]

The first effect is that it is possible to easily realize high-precision flatness, and that even if the surface of a semiconductor chip or a substrate to be mounted has irregularities, it is not affected by such irregularities.

The reason is that the flatness is realized while polishing the insulating film using the CMP technique, and the accuracy of the flatness can be relatively easily increased.

The second effect is that, since a wiring connection pad having a large area required for securing a manufacturing margin is not required, the capacitance of the pad portion can be reduced, and low power and high speed operation can be achieved. The point is that the chip size can be reduced by the wiring connection pad arrangement area.

The reason is that the surface of the insulating film after chip embedding is flattened by using the CMP technology, so that when forming a pattern by the photolithography technology, the unevenness of the insulating film surface can be reduced to a depth of focus or less. This is because, since the pattern can be formed with high accuracy, a wiring connection pad having a large area for securing a margin during pattern formation is not required.

The third effect is that noise propagation through the substrate between the first semiconductor chip 2 and the second semiconductor chip 3 can be prevented.

The reason is that an insulating film is formed on the side walls and the bottom of the groove of the first semiconductor chip 2 and the second semiconductor chip 3 is buried in the groove, so that the second semiconductor chip 3 is formed of the insulating film. Can be separated.

A fourth effect is that active elements or passive elements of the first semiconductor chip 2 and the second semiconductor chip 3 can be formed by optimal manufacturing steps.

The reason is that the first semiconductor chip 2 and the second semiconductor chip 2
Semiconductor chip 3 can be formed halfway in different manufacturing steps, so that, for example, a sensitive active element or a passive element that exhibits characteristic fluctuation by a step using a high temperature, and an active element or a passive element that needs to be manufactured using a high temperature. Passive elements can be formed in separate manufacturing processes,
This is because when these two types of active elements or passive elements are mixed, deterioration of sensitive active elements or passive elements can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a method of manufacturing a semiconductor integrated circuit device according to a first specific example of the present invention.

FIG. 2 is a sectional view showing a main part of a method for manufacturing a semiconductor integrated circuit device according to a first specific example of the present invention.

FIG. 3 is a plan view for explaining a method of manufacturing a semiconductor integrated circuit device according to a first specific example of the present invention, which illustrates an alignment method when arranging a second semiconductor chip 3 in a groove of the first semiconductor chip; It is.

FIG. 4 is a cross-sectional view showing a main part of the manufacturing method after the second semiconductor chip 3 is buried in the groove in the method of manufacturing the semiconductor integrated circuit device according to the first specific example of the present invention.

FIG. 5 is a continuation process of FIG. 4;

FIG. 6 is a continuation process of FIG. 5;

FIG. 7 is a sectional view showing a main part of a method for manufacturing a semiconductor integrated circuit device according to a second specific example of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Wafer 2 1st semiconductor chip 3 2nd semiconductor chip 4 Gate electrode 5 Diffusion layer area 6 Element isolation area 7 Insulating film 8 2nd semiconductor chip arrangement area 9 Photoresist 10 Groove 11 Second semiconductor chip substrate 12 Gate electrode of second semiconductor chip 13 Diffusion layer region of second semiconductor chip 14 Element isolation region of second semiconductor chip 15 Insulating film of second semiconductor chip 16 Fixing material 17 Alignment on first semiconductor chip 2 Pattern 18 Alignment pattern on second semiconductor chip 3 19 Insulating film 20 Insulating film after CMP 21 Contact hole forming region 22 Contact hole 23 Contact 24 Conductor material 25 First wiring region in first semiconductor chip 26 Second First wiring region in semiconductor chip 27 First semiconductor chip and second semiconductor chip During the first
Wiring area 28 First wiring in first semiconductor chip 29 First wiring in second semiconductor chip 30 First between first semiconductor chip and second semiconductor chip
Wiring 31 Insulating film

Claims (7)

[Claims] A step of digging a groove in a wafer on which a first semiconductor chip is formed; a step of arranging a second semiconductor chip in the groove; and a step of arranging the second semiconductor chip in the groove. A step of covering the surface of the wafer with an insulating film, a step of flattening the wafer surface covered with the insulating film, and a step of connecting the first semiconductor chip and the second semiconductor chip with a conductor. A method for manufacturing a semiconductor integrated circuit device, comprising at least: 2. The semiconductor integrated circuit device according to claim 1, wherein the wafer on which the first semiconductor chip is formed and the second semiconductor chip are manufactured by different manufacturing steps. Production method. 3. A step of digging a plurality of grooves in a wafer on which a first semiconductor chip is formed, and a step of arranging a plurality of second semiconductor chips in the plurality of grooves, respectively. The method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. The method according to claim 1, further comprising: depositing an insulating film on a side wall and a bottom of the groove; and arranging the second semiconductor chip in the groove on which the insulating film is deposited. Item 4. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 3. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of wiring and connecting the inside of said first semiconductor chip with a conductor. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of wiring and connecting the inside of said second semiconductor chip with a conductor. 7. The step of flattening the wafer surface,
CMP (Chemical Mechanical P
7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the surface is flattened by an applying technique.