JP2001243167A - Ide bus peripheral device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IDE bus peripheral device such that even when the device is connected as a slave device to a host computer without connected master devices, the device is identified as a master device by the host computer by means of IDE bus peripheral identification of the same previous host computer, and is operated as the master device. SOLUTION: The IDE bus peripheral device comprises an IDE interface part 135 having a transmission part 139, a slave command reception part 137, a response monitor part 138, a jumper 132 to set as a master or a slave, a recording medium 134 to store information data, and a CPU 133 that executes transmission/reception of signals between a host computer through an IDE interface part 135, reads the setting of the jumper 132, controls a read/write of the information data stored in the recording medium 134, and executes processing depending on the command issued by the host computer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IDE bus peripheral device and, more particularly, to a host computer which recognizes an IDE bus peripheral device in a state where a master device is not connected to a host computer and only a slave device is connected. is there.

[0002]

2. Description of the Related Art IDE is an interface capable of connecting a maximum of two peripheral devices to a host computer, a first device being a master and a second device being a slave. ID connected to host computer
The CPU reads the setting of the jumper set as the master or the slave by the CPU.
It recognizes itself as a master or a slave.

FIG. 3 is a block diagram showing a configuration of a conventional IDE bus peripheral device. In FIG. 3, reference numeral 302 denotes an IDE interface connected to the host computer;
2 is a jumper to set as master or slave, 1
34 is a storage medium for storing information data, 301 is for sending and receiving signals to and from the host computer via the IDE interface 302, reading the setting of the jumper 132, taking in and out the information data stored in the storage medium 134, and issuing the host computer. CPU that performs processing according to the command to be executed
It is.

FIG. 2 is a flowchart showing a procedure for recognizing an IDE bus peripheral device of a host computer. FIG.
At the time of system startup such as power-on, the host computer issues an Identify command to the master device in order to search for the master device (201), and confirms whether there is a response signal to the command (202).

In the confirmation of the response signal to the command (202), if the master device is an ATA drive such as a hard disk, the master device transmits data such as a drive name and drive information to the host computer as a response signal to the command. . Also, if the master device is C
In the case of an ATAPI drive such as a D-ROM, the master device transmits to the host computer as a response signal that the command has not been supported and has ended with an error.

When the host computer receives the response signal from the master device, the host computer determines that a master device is present (203), and terminates the master device search process (220). Next, the host computer searches for slave devices (2
21) to end IDE bus peripheral device recognition (21).
1).

On the other hand, when the host computer checks (202) whether or not there is a response signal to the command, if there is no response signal from the master device, the host computer sends the response to the command.
Whether the number of issued tify commands exceeds the number of retries
(204) Confirm. The number of retries is the number of times a host computer repeatedly issues a command for safety in consideration of the fact that the host computer cannot receive a response signal of the command for some reason, even though the master device actually exists. It is set to two or more times.

When confirming the number of times the Identify command has been issued to the master device (204), if the number of times the Identify command has been issued to the master device does not exceed the number of retries, the host computer repeatedly sends the Iden to the master device.
Issue a tify command (201). On the other hand, the master device
If the number of times the ntify command has been issued exceeds the number of retries, the host computer determines that the master device does not exist (205) and does not execute the slave device search processing (221), and recognizes the IDE bus peripheral device. Is ended (211).

After completion of the recognition of the IDE bus peripheral device,
The host computer issues a command for controlling the device to the recognized IDE bus peripheral device, but does not issue a command for controlling the device to the unrecognized IDE bus peripheral device. The unrecognized IDE bus peripheral does not operate at all.

[0010]

In a state where only the slave device is connected without connecting the master device to the host computer, the host computer operates the IDE device.
There is a problem that the bus peripheral device recognition does not recognize the actually connected slave device. In addition, many users do not understand how to set the IDE bus peripheral device as a master or a slave, so that the above problem occurs frequently.

The present invention has been made in view of the above-described problems, and when the power of the host computer is turned on, the host device is connected to the host computer to which the master device is not connected as a slave device. By the same host computer IDE bus peripheral device recognition method, the host computer recognizes the device as a master device,
It is an object of the present invention to provide an IDE bus peripheral device that operates as a master device thereafter.

[0012]

According to another aspect of the present invention, there is provided an IDE bus peripheral device comprising: a master command receiving unit for receiving a command for a master device;
A slave command receiving unit for receiving a command for the slave device, a response monitoring unit for monitoring that an interrupt signal is asserted, and a transmitting unit for transmitting a signal to a host computer, and an IDE interface unit connected to the host computer A jumper to be set as a master or a slave; a storage medium for storing information data; transmitting and receiving signals to and from the host computer via the IDE interface unit; reading the jumper settings; And a CPU that controls data input and output and performs processing according to commands issued by the host computer.

[0013]

(First Embodiment) FIG. 1 is a block diagram showing a configuration of an IDE bus peripheral device according to a first embodiment. In FIG. 1, reference numeral 135 denotes an IDE interface unit connected to the host computer, which is configured as follows. That is, 136 is a master command receiving unit that receives a command issued by the host computer to the master device, 137 is a slave command receiving unit that receives a command issued by the host computer to the slave device, and 138 is an interrupt signal (INTRQ signal) 139 is a response monitoring unit that monitors the assertion of, and a transmission unit that transmits a signal to the host computer.

Reference numeral 132 denotes a jumper set as a master or a slave; 134, a storage medium for storing information data;
33 transmits and receives signals to and from the host computer via the IDE interface unit 135, reads the setting of the jumper 132, performs control to insert and remove information data stored in the storage medium 134, and processes according to commands issued by the host computer. CPU that performs

Next, the operation of the IDE bus peripheral device in which the jumper setting is connected as a slave to a host computer to which no master device is connected will be described with reference to FIGS. 1 and 2. The host computer issues a first Identify command to the master device to search for the master device at the time of system startup such as power-on (201).

Next, in the present IDE bus peripheral device, the master command receiving section 136 receives the first Identify command and outputs the command to the CPU 133. The response monitor unit 138 outputs a monitoring result having no response signal to the first Identify command to the CPU 133. The jumper 132 transfers the slave setting data to the CPU 133.
Output to The CPU 133 includes a master command receiving unit 136.
Does not respond to the first Identify command because the destination of the command output from is different from the slave that is the setting of the jumper 132. Further, the CPU 133 determines that the master device is not connected to the host computer based on the monitoring result from the response monitor unit 138, and thereafter, responds to the command for the master device received by the master command receiving unit 136, The slave command receiving unit 137 determines not to respond to the command for the slave device received by the slave command receiving unit 137.

Next, the host computer executes the first Id
When checking whether there is a response signal to the entify command (202), since the response signal is not received,
Check if the number of issued entify commands exceeds the number of retries (204). Here, since the number of retries is set to two or more, the host computer issues a second Identify command to the master device (201).

Next, in the IDE bus peripheral device, the master command receiving section 136 receives the second Identify command and outputs it to the CPU 133. The CPU 133 executes a process according to the second Identify command, and outputs a response signal to the transmitting unit 139. The transmitting unit 139 performs the second Identi
Sends a response signal to the fy command to the host computer.

Next, the host computer executes the second Id
When confirming whether there is a response signal to the entify command (202), since the response signal transmitted by the transmitting unit 139 is received, it is determined that the master device exists (203), and the search process of the master device (202) is performed. finish.

Next, the host computer issues an Identify command to the slave device to search for the slave device (206). In the present IDE bus peripheral device, the slave command receiving unit 137 receives the above Identify command and outputs it to the CPU 133. The CPU 133 does not respond to the command for the slave device received by the slave command receiving unit 137. In addition, since the CPU 133 does not respond to the command for the slave device thereafter,
The host computer identifies the slave device
No command response signal is received. Therefore, the host computer determines that there is no slave device (210), and ends the IDE bus peripheral device recognition (211).

The host computer recognizes the IDE bus peripheral device as a master device by the host computer recognition of the IDE bus peripheral device, and does not recognize the slave device. The IDE bus peripheral device operates as a master device by executing processing in accordance with a command issued by the host computer to the master device.

As described above, the IDE bus peripheral device according to the first embodiment of the present invention includes the IDE interface unit 135.
In addition, the provision of the master command receiving unit 136, the slave command receiving unit 137, the response monitoring unit 138, and the transmitting unit 139 results in violation of each standard of IDE peripheral devices such as ATA and ATAPI. Even when the host device is connected as a slave device to a host computer to which no master device is connected, the host computer can recognize the device as a master device and operate as a master device.

[0023]

As is apparent from the above description, claim 1
According to the invention described in the above, a master command receiving unit for receiving a command for the master device, a slave command receiving unit for receiving a command for the slave device, a response monitoring unit for monitoring that an interrupt signal is asserted, and a host computer An IDE interface unit connected to the host computer, a jumper set as a master or a slave, a storage medium for storing information data,
Send and receive signals to and from the host computer via the DE interface, read the jumper settings,
A CPU for controlling the transfer of information data stored in the storage medium and performing processing in accordance with a command issued by the host computer;
Even when connected as a slave device to a host computer to which no master device is connected, which is a violation of each standard of IDE peripheral devices such as TAPI, the host computer recognizes the device as a master device and operates as a master device. The effect that can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an IDE bus peripheral device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure for recognizing an IDE bus peripheral device of a host computer.

FIG. 3 is a block diagram showing a configuration of a conventional IDE bus peripheral device.

[Explanation of symbols]

 132 Jumper 133, 301 CPU 134 Storage medium 135 IDE interface section 136 Master command receiving section 137 Slave command receiving section 138 Response monitor section 139 Transmitting section 302 IDE interface

Claims (1)

[Claims] 1. A master command receiving unit for receiving a command for a master device, a slave command receiving unit for receiving a command for a slave device, a response monitoring unit for monitoring that an interrupt signal is asserted, and a signal to a host computer An IDE interface unit connected to the host computer, a jumper set as a master or a slave, a storage medium for storing information data, and a signal transmission between the host computer and the host computer via the IDE interface unit. A CPU for performing transmission / reception, reading the setting of the jumper, controlling the insertion / removal of information data stored in the storage medium, and performing processing according to a command issued by a host computer. Bus peripherals.