JP2001243063A - Ｓｉｍｄ命令をエミュレートする方法及び装置 - Google Patents

Ｓｉｍｄ命令をエミュレートする方法及び装置

Info

Publication number
JP2001243063A
JP2001243063A JP2001025784A JP2001025784A JP2001243063A JP 2001243063 A JP2001243063 A JP 2001243063A JP 2001025784 A JP2001025784 A JP 2001025784A JP 2001025784 A JP2001025784 A JP 2001025784A JP 2001243063 A JP2001243063 A JP 2001243063A
Authority
JP
Japan
Prior art keywords
exception
sse
instruction
register
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001025784A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001243063A5 (https=
Inventor
Patrick Knebel
パトリック・クネベル
Kevin David Safford
ケビン・デイビッド・サフォード
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2001243063A publication Critical patent/JP2001243063A/ja
Publication of JP2001243063A5 publication Critical patent/JP2001243063A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30116—Shadow registers, e.g. coupled registers, not forming part of the register space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2001025784A 2000-02-02 2001-02-01 Ｓｉｍｄ命令をエミュレートする方法及び装置 Pending JP2001243063A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/496844 2000-02-02
US09/496,844 US6820190B1 (en) 2000-02-02 2000-02-02 Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions

Publications (2)

Publication Number Publication Date
JP2001243063A true JP2001243063A (ja) 2001-09-07
JP2001243063A5 JP2001243063A5 (https=) 2006-11-30

Family

ID=23974401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001025784A Pending JP2001243063A (ja) 2000-02-02 2001-02-01 Ｓｉｍｄ命令をエミュレートする方法及び装置

Country Status (2)

Country Link
US (1) US6820190B1 (https=)
JP (1) JP2001243063A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010152919A (ja) * 2001-12-20 2010-07-08 Intel Corp プロセッサに関するロード／移動及び複製命令
JP2011248820A (ja) * 2010-05-31 2011-12-08 Nec Computertechno Ltd 情報処理装置及びマイクロ命令処理方法
JP2018507453A (ja) * 2014-12-23 2018-03-15 インテル・コーポレーション 命令フローを最適化するチェックを実行するための装置および方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7941647B2 (en) * 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8121828B2 (en) 1999-01-28 2012-02-21 Ati Technologies Ulc Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US7206921B2 (en) * 2003-04-07 2007-04-17 Intel Corporation Micro-operation un-lamination
US7451294B2 (en) * 2003-07-30 2008-11-11 Intel Corporation Apparatus and method for two micro-operation flow using source override
US7213136B2 (en) * 2003-07-30 2007-05-01 Intel Corporation Apparatus and method for redundant zero micro-operation removal
US9703562B2 (en) * 2013-03-16 2017-07-11 Intel Corporation Instruction emulation processors, methods, and systems
US11461106B2 (en) 2019-10-23 2022-10-04 Texas Instruments Incorporated Programmable event testing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2911278B2 (ja) * 1990-11-30 1999-06-23 松下電器産業株式会社 プロセッサ
US5546599A (en) * 1994-03-31 1996-08-13 International Business Machines Corporation Processing system and method of operation for processing dispatched instructions with detected exceptions
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US5764971A (en) * 1996-12-11 1998-06-09 Industrial Technology Research Institute Method and apparatus for implementing precise interrupts in a pipelined data processing system
US6233671B1 (en) * 1998-03-31 2001-05-15 Intel Corporation Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
US6085312A (en) * 1998-03-31 2000-07-04 Intel Corporation Method and apparatus for handling imprecise exceptions
US6038652A (en) * 1998-09-30 2000-03-14 Intel Corporation Exception reporting on function generation in an SIMD processor
US6321327B1 (en) * 1998-12-30 2001-11-20 Intel Corporation Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations
US6330657B1 (en) * 1999-05-18 2001-12-11 Ip-First, L.L.C. Pairing of micro instructions in the instruction queue
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010152919A (ja) * 2001-12-20 2010-07-08 Intel Corp プロセッサに関するロード／移動及び複製命令
US8539202B2 (en) 2001-12-20 2013-09-17 Intel Corporation Load/move duplicate instructions for a processor
US8650382B2 (en) 2001-12-20 2014-02-11 Intel Corporation Load/move and duplicate instructions for a processor
US9043583B2 (en) 2001-12-20 2015-05-26 Intel Corporation Load/move and duplicate instructions for a processor
JP2011248820A (ja) * 2010-05-31 2011-12-08 Nec Computertechno Ltd 情報処理装置及びマイクロ命令処理方法
JP2018507453A (ja) * 2014-12-23 2018-03-15 インテル・コーポレーション 命令フローを最適化するチェックを実行するための装置および方法

Also Published As

Publication number Publication date
US6820190B1 (en) 2004-11-16

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