JP2001237840A - Minimum cell interval control method and minimum cell interval controller for atm unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller for an ATM unit that can maintain a minimum cell interval of cells from a host device via an SAR-LSI and a physical layer LSI (PHY). SOLUTION: The minimum cell interval controller in the ATM unit 1 where cells generated by cell generating circuits 11, 12 are sent to an ATM network 3, is provided with a plurality of storage means 17 that temporarily stores cells and corresponds to the number of contracted lines and with a control section 15 that controls write/read of the cells to/from the storage means. The control section is provided with a reception control section 153 that stores the received cells into the storage means in the unit of VPs or VCs requiring shaping, a transmission control section 154 that transmits the cells stored in the storage means to an ATM channel at an interval more than the minimum cell interval, and a bus arbitration circuit 156 that arbitrates the cells so that only one cell is sent to the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
In an ATM communication device connected to an M line, a minimum cell interval control method and an ATM communication device for an ATM communication device in which generated cells are transmitted to the ATM line while maintaining a minimum cell interval (peak cell rate) of the ATM line. The minimum cell interval control device.

[0002]

2. Description of the Related Art AT for connecting a data terminal to an ATM line
In the case of the M communication device, the ATM line is connected to a virtual channel (Vi
rtual Channel: A method of contracting in units of VC (share link service) or a virtual path (Virtua
l Path: A contract is made according to a method of contracting (megalink service) in units of VP. In these contracts, a transmission band is assigned to each ATM line in advance, and information is not transferred beyond the transmission band assigned when the connection on the ATM line is set.

An LSI (generally SAR) for generating cells for disassembling a commercially available data unit into a plurality of cells or assembling a plurality of cells into one data unit.
(Segmentation and Reassembly Sublayer:
(Assembled sublayer). The SAR-LSI generates cells, but often cannot freely control the cell interval (transmission band) (generally referred to as VC shaping). Even if there is a SAR-LSI that can freely control the cell interval,
There are many cases where an AR-LSI has a plurality of ports and shaping must be performed on cells for the plurality of ports (generally called VP shaping), and the minimum cell interval can be accurately determined (about 1 kbyte / s). Until) Controllable LSIs are not generally commercially available.

The operation of a conventional ATM device will be described with reference to FIGS. Since the present invention is directed to the direction of outputting to the ATM network, the prior art will be referred to only in this direction.

[0005] As shown in FIG. 4, the ATM device 1 has a cell disassembly / assembly sublayer (SAR-LSI) 11-1, 1.
1-2), the cell termination LSI 12, and the ATM line 31
Physical layer LSI (P
HY) 13, and the outputs of the cell disassembly / assembly sublayers (SAR-LSI) 11-1 and 11-2) and the cell termination LSI 12 are transmitted via the common bus 14 to the physical layer LSI (PHY) 13. Is input to Cell disassembly / assembly sublayers (SAR-LSI) 11-1 and 11-2 are terminals 51-1 and 5-1 having a constant bit rate (CBR).
1-2. The cell termination LSI 12 is a CLA
Connected to D terminal 52.

The data from the terminal 51-1 is converted into cells in the cell disassembly / assembly sublayer 11-1 and output to the common bus 14 as cellized data D1. Data from the terminal 51-2 is formed into cells in the cell disassembly / assembly sublayer 11-2 and output to the common bus 14 as cellized data D2. C terminated in cell termination LSI 12
The data D3 cellized by the LAD terminal 52 is transmitted to the common bus 1
4 is output. Cellular data D1, on the common bus 14,
D2 and D3 are arranged in different time slots, and are connected to the ATM network 3 via the physical layer LSI (PHY) 13.
Is output as D4 to the line 31.

The unit of shaping is set for each terminal (A
TM network) and cell data D1, D2,
When each of the D3s receives a shaping constraint (VC shaping) separately, as shown in FIG. 5, the SAR-LS
Cellular data D1 output from I11-1 is, for example, VC at substantially equal intervals t1a, t1b, t1c, t1d.
1 and the cell data D2 output from the SAR-LSI 11-2 have substantially equal intervals t2a and t2b.
For example, the cellized data D3 output on the VC2 and output from the cell termination LSI 12 has substantially the same interval t3.
For example, a is output on the VC3 at a (the above is the case 1).
As described above, if the cellized data D1, D2, and D3 are output on the respective VCs at substantially equal intervals, the AT
No particular problem occurs on the M line 31.

However, generally available SAR-L
The SI may not always output cells at regular intervals. The actual form of the line contract with the ATM network is shown in FIG.
Each V for which the VC shape is performed as shown in FIG.
Instead of contracting the line in C units, it is common to take the form of contracting the transmission band in VP units by grouping multiple transmission lines in consideration of the cost of the line contract transmission band with the network. is there.

The case where data D1 and D2 are combined into one transmission band contract (VP1) and data D3 is combined into one transmission band contract (VP2) (case 2) will be described with reference to FIG.

In a transmission bandwidth contract, if the average cell interval for the contracted rate is Tav, the allowable value of cell delay variation tolerance (CDVT) of the ATM network is Tcdvt, and the cell interval is t4, Tav −
It is required that t4 ≧ Tcdvt be satisfied. That is,
The cell interval t4 is obtained by subtracting the CDVT value Tcd from the average cell interval Tav.
It is required to be less than or equal to the value obtained by subtracting vt (minimum cell interval).

When data is transmitted to a transmission line having such a request, even if the data D1, D2, and D3 are respectively output at equal intervals, the cells C1a, C1a, When C2a is continuous, there are cases where the cell interval t4 cannot satisfy the above condition.

If the ATM cells C1a and C1a
2a, the cell C violating this minimum cell interval
2a is discarded as a peak cell rate (hereinafter, referred to as PCR) violation indicating the upper limit of the transmission rate that can be transmitted on the ATM connection, and the cell cannot be transferred normally.

This discarding of cells is performed in the same manner as in FIG. 5 except for the cell intervals t1a, t1b, t1c, t1d, t2a, t2b
Occurs when the minimum cell interval of each line contract transmission band is not satisfied.

In the above-mentioned conventional SAR-LSI, it is not possible to control the minimum cell interval with the required accuracy. Therefore, it is necessary to increase the network transmission bandwidth in order to relax the condition regarding the minimum cell interval. However, there is a drawback that the line usage fee increases.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended to maintain a minimum cell interval of cells coming from a higher-level device via a SAR-LSI or a physical layer LSI (PHY). It is an object of the present invention to provide a control device for an ATM device.

[0016]

SUMMARY OF THE INVENTION The present invention relates to an ATM device for a SAR-LSI or a physical layer LSI (PHY).
Means for analyzing header information of a cell coming from a higher-level device via a host and transferring it to a corresponding FIFO (first-in first-out memory); a register for setting a group requiring shaping; a register for setting a minimum cell interval of the group; PHY
Arbitration circuit when there are a plurality of FIFOs to be transmitted.

According to the present invention, there is provided a minimum cell interval control method in an ATM device for transmitting cells from a cell generation circuit to an ATM (asynchronous transfer mode) line, wherein a minimum cell for each VP or VC unit requiring shaping (self-rate regulation) is provided. A circuit for setting the interval is provided, and the minimum cell interval in the ATM device is controlled so as to output the cell while maintaining the minimum cell interval so as not to exceed the transmission band of the line contract.

According to the present invention, there is provided a minimum cell interval control method in an ATM device for transmitting cells from a cell generation circuit to an ATM (asynchronous transfer mode) line, wherein a minimum cell for each VP or VC unit requiring shaping (self-rate regulation) is provided. A circuit for setting the interval and a bus arbitration circuit for selecting cells from one of the plurality of cell transmission circuits and transmitting them in a bus form are provided, and only one cell is transmitted on one bus at the same time. At the same time, the minimum cell interval in the ATM device is controlled so as to output cells while maintaining the minimum cell interval so as not to exceed the transmission band of the line contract.

According to the present invention, there is provided a minimum cell interval control device in an ATM device for transmitting a cell generated by a cell generation circuit to an ATM network, a plurality of storage means corresponding to the number of line contracts for temporarily storing cells, A control unit that controls writing and reading to and from the storage unit; a reception control unit that distributes received cells to the storage unit and stores the cells; and a control unit that stores cells stored in the storage unit as minimum cells. A transmission control unit for transmitting data to the ATM line at intervals longer than the interval is provided.

According to the present invention, there is provided a minimum cell interval control device in an ATM device for transmitting a cell generated by a cell generation circuit to an ATM network, comprising: a plurality of storage means corresponding to the number of line contracts for temporarily storing cells; A control unit that controls writing and reading to and from the storage unit, wherein the control unit distributes and stores received cells to the storage unit for each VP unit or VC unit that requires shaping; A transmission control unit for transmitting the cells stored in the storage means to the ATM line at intervals equal to or longer than the minimum cell interval;
A bus arbitration circuit that arbitrates so that only one cell is transmitted on the bus is provided.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described with reference to FIGS.

As shown in FIG. 1, the ATM according to the present invention
The device 1 includes a plurality of cell disassembly / assembly sublayers (SAR-
LSI) 11-1 and 11-2, and cell termination LSI 12
Physical layer LSI (PHY) 13 on the ATM network side,
A common bus (Utopia bus) 14, a control circuit 15,
It comprises a plurality of FIFOs 17. Cell disassembly
Assembly sublayer (SAR-LSI) 11-1, 11-2
, A cell termination LSI 12, and a physical layer LSI (PH
Y) 13 and the common bus 14 work similarly to the ATM device shown in FIG.

The control circuit 15 controls writing and reading of cells to be transmitted to the ATM network to and from the FIFO, and includes a bus interface 151 and a header analysis unit 152.
, FIFO reception control unit 153, FIFO transmission control unit 155, bus arbitration circuit 156, clock generation unit 15
7 are provided.

The bus interface 151 is a common bus 1
4 interface.

The header analyzer 152 extracts a header from the cell received by the bus interface 151 and analyzes the contents of the header.

The FIFO reception control unit 153 specifies the FIFO in which the cell is to be written according to the contents of the header, and
Controls writing of data to the IFO.

The FIFO transmission control unit 155 reads out the cells written in the FIFO at a predetermined timing,
The FIFO is controlled so as to output to the M network side physical layer LSI (PHY) 13.

The bus arbitration circuit 156, when receiving a plurality of FIFO read requests from the FIFO transmission control unit, reads a predetermined cell at a predetermined timing and performs arbitration so as to transmit the read cell to the common bus.

The clock generation circuit 157 generates, for example, a 20 MHz reference clock used for FIFO reading or the like.

The FIFO 17 serves as a buffer for temporarily storing cells, and is provided with at least the number of groups for performing shaping (the number of contract units with the ATM network).
This example shows a case where the number of groups to be shaped is “3”.

The detailed configuration of the FIFO reception control section 153 will be described with reference to FIG.

The FIFO reception control section 153 includes three shaping group setting registers 1531-1 to 1531-3.
And three AND circuits 1534-1 to 1534-3. In this description, the three shaping group setting registers 1531-1 to 1531-3 respectively correspond to the first shaping group setting register 1531-1.
1, the second shaping group setting register 1531-2,
An individual device is identified by being called a third shaping group setting register 1531-2. AND circuit 1534, counter 1551 in FIG. 3, minimum cell interval setting register 15
52, an AND circuit 1553, and a FIFO transmission signal generation circuit 1554 similarly identify the individual devices by adding the first to third characters at the top, and add -n after the code.

Each shaping group setting register 1
531-1 to 1531-3 have the same configuration. The shaping group setting register 1531 includes a plurality of header value setting units 1532 and an OR circuit 1533. The header value of a cell belonging to a specific shaping group is set in each header value setting unit 1532 by 4 bytes, and the header value analyzed by the header analysis unit 152 matches the header value set in the shaping group setting register 1531. Then, a write enable signal W for a predetermined FIFO is output.

The configuration of the FIFO transmission control unit 155 will be described with reference to FIG.

The FIFO transmission control unit 155 has three control units corresponding to the number of FIFOs. Each control unit includes a counter 1551, a minimum cell interval setting register 1552, and an AND circuit 1553. , FIF
An O transmission signal generation circuit 1554.

The counter 1551 is configured as, for example, a down counter, and a FIFO transmission signal generation circuit 1554
When the clock CLK is counted and reaches the value set in the minimum cell interval setting register 1552, a signal requesting permission of transmission is transmitted to the bus arbitration circuit 156. The minimum cell interval setting register 1552 is a register in which the minimum cell interval of cells continuously transmitted in the same shaping group is set.
The count value of the clock that becomes the minimum cell interval is set.

The AND circuit 1553 obtains a match between the empty flag (EF) signal indicating whether or not there is a signal in the FIFO sent from the FIFO 17 and the transmission permission signal 300 from the bus arbitration circuit 156, and performs FIFO matching. The transmission signal generation circuit 1554 is permitted to generate a transmission signal. EF
The signal is set to be "1" when data is in the FIFO.

The FIFO transmission signal generation circuit 1554 converts the FIFO transmission signal R to F when the transmission signal generation permission is given.
Output to IFO 17.

Next, the operation of this device will be described based on the case shown in FIG. Assuming that 1 Mbit / s (VP
I = 1), 0.5 Mbit / s (VPI = 2), 0.5
Three ATM lines of Mbit / s (VPI = 3) are AT
A contract is made with the M network (contract for each VP), and each ATM line is used for terminal A (VPI = 1) and for terminal B (VP
I = 2) and the setting method for each register when assigning to terminal C (VPI = 3) are described below.

The setting in the shaping group setting register 1531 of the FIFO reception control unit 153 is based on each VCI
The values are set to terminal A “100”, terminal B “200”, terminal C “3”.
00 ”, the header value setting unit 1532 of the first shaping group setting register 1531-1 stores“ VPI =
1, VCI = 100 ”is sent to the header value setting unit 1532 of the second shaping group setting register 1531-2 as“ VP ”.
I = 2, VCI = 200 "and" VPI = 3, VCI = 300 "are set in the header value setting unit 1532 of the third shaping group setting register 1531-3.
In this case, if there is an unused header value setting section register, an impossible value such as “VPI = 0” or “VCI = 0” is set as a default, so that the condition is satisfied only with the set value. Has become.

On the other hand, the setting in the minimum cell interval register 1552 of the FIFO transmission control unit 155 is performed as follows. .

Assuming that the CDVT (transfer delay variation allowable width) at 1 Mbit / s is 0.2 ms, 1 Mbit / s
/ S, the average cell interval Tave1M is Tave1M = 1 /
(1M / 8 * 53) = 424 μs.

In this case, the minimum cell interval Tmin1M is Tm
in1M = 424 μs−0.2 ms = 224 μs, and V
Once a cell with PI = 1 is transmitted, at least 22 until the next transmission
It is necessary to transmit at intervals of 4 μs.

Therefore, when CLK = 1 MHz, the cycle is 1
μs, the minimum cell interval register 1552 stores 10
Hexadecimal is set to “224”. The counter 1551 is a down counter, and the FIFO transmission signal generation circuit 15
The request is not output to the bus arbitration circuit 156 while the set value of the minimum cell interval register 1552, for example, “224” is counted after the transmission signal R from 54 rises.

Even if the data is in the FIFO and the EF becomes "1", the permission from the bus arbitration circuit 156 does not return, so the transmission signal generation circuit 1554 generates the transmission signal after at least 224 counts. When a signal to be permitted arrives and a cell is transmitted once, an interval is left at least until the next cell transmission of 224 counts.

The bus arbitration circuit 156 outputs the transmission signal R
Arbitration is performed so that even if a plurality of requests are simultaneously received from the counters 1551-1, 1551-2, and 1553-1, only one permission is output at a time so that two or more R1, R2, and R3 are not output simultaneously.

Next, the setting of the minimum cell interval setting register 1552 at 0.5 Mbit / s will be described. 1Mb
CDVT is 0.2 ms as in the case of it / s. 0.
Average cell interval Tave0.5M at 5 Mbit / s is Ta
ve0.5M = 1 / (0.5M / 8 * 53) = 848 μs
Becomes

In this case, the minimum cell interval Tmin 0.5M
Is Tmin 0.5M = 848 μs−0.2 ms = 648
μs, and cells with VPI = 2 and VPI = 3 have a minimum of 6
It is necessary to transmit at intervals of 48 μs. Therefore CL
When K = 1 MHz, the cycle is 1 μs, so that “648” is set in the minimum cell interval registers 1552-2 and 1552-3 in decimal. Subsequent operations are 1 Mbit /
Same as in s.

Next, case 2 shown in FIG. 6 will be described. In this case, two FIFOs 17 are required.
Suppose a contract with the ATM network (contract per VP) is 1 Mbi
t / s (VPI = 1), 0.5 Mbit / s (VPI =
2) are prepared for terminal A and terminal B (V
PI = 1) and assigned to terminal C (VPI = 2).

The shaping group setting register 1 in this case
The setting method of 531 is as follows.
00, terminal B “200” and terminal C “300”, the first header value setting unit 1532 of the first shaping group setting register 1531-1 stores “VPI = 1, VCI
= 100 ”, and“ V ”is stored in the second header value setting unit 1532 of the first shaping group setting register 1531-1.
PI = 1, VCI = 200 "and" VPI = 2, VCI = 300 "are set in the header value setting unit 1532 of the second shaping group setting register 1531-2. In this example, the third shaping group setting is performed. The header value setting section register 1532 of the register 1531-3 stores “VPI = 0, V
Impossible values such as CI = 0 ”are defaulted,
It is considered unused.

The setting method for the minimum cell interval setting register 1552 of the FIFO transmission control unit 155 is the same as that for 1 Mbit / s and 0.5 Mbit / s in case 1, and the first minimum cell interval setting register 1552- 1 is “224” in the second minimum cell interval setting register 155.
“648” is set in 2-2.

When the VPI is fixed but the number of VCIs is large in the unit of shaping, the header value setting section 1532 can specify only the VPI and set the VCI to be unconditional. By doing so, it is possible to reduce the amount of hardware of an enormous set value register.

In the embodiment described above, the FIFO 17, the shaping group setting register 1531, the counter 155
1. Three minimum cell interval setting registers 1552 are provided, respectively. However, by adding FIFOs and registers to satisfy the required device specifications, the device can be realized even in a configuration in which the number of terminals is increased. A is possible
It is limited by the available transmission band of the TM line.

[0054]

As described above, according to the present invention, A
Even if the TM line is contracted to the theoretically necessary ATM network side speed depending on the terminal speed, the data from a plurality of SAR-LSIs and cell termination LSIs when outputting to the ATM network is
This makes it possible to prevent cell discarding due to CR violation, eliminates the need for an extra transmission band contract, and improves cost merit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an ATM device employing a minimum cell interval control device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a FIFO transmission control unit of the control circuit shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of a FIFO reception control unit of the control circuit shown in FIG.

FIG. 4 is a block diagram illustrating a configuration of a conventional ATM device.

FIG. 5 is a diagram illustrating a cell transmission interval (case 1).

FIG. 6 is a diagram illustrating a cell transmission interval (case 2).

[Explanation of symbols]

 Reference Signs List 1 ATM device 3 ATM network 11 Cell disassembly / assembly sublayer (SAR-LSI) 12 Cell termination LSI 13 Physical layer LSI (PHY) 14 Common bus (Utopia bus) 15 Control circuit 17 FIFO 151 Bus interface 152 Header analysis unit 153 FIFO Reception control circuit 155 FIFO transmission control circuit 156 Bus arbitration circuit 157 Clock generation circuit 1531 Shaping group setting register 1532 Header value setting unit 1533 OR circuit 1534 AND circuit 1551 counter 1552 Minimum cell interval setting register 1553 AND circuit 1554 FIFO transmission signal generation circuit

Claims (4)

[Claims] 1. A method of controlling a minimum cell interval in an ATM device for transmitting a cell from a cell generation circuit to an ATM (asynchronous transfer mode) line, comprising the steps of: setting a minimum cell interval for each VP or VC unit requiring shaping (self-rate regulation). ATM that provides a setting circuit and outputs cells with the minimum cell interval kept so as not to exceed the transmission bandwidth of the line contract
A method for controlling a minimum cell interval in a device. 2. A method for controlling a minimum cell interval in an ATM device for transmitting a cell from a cell generation circuit to an ATM (asynchronous transfer mode) line, comprising the steps of: setting a minimum cell interval for each VP or VC unit requiring shaping (self-rate regulation). A circuit for setting, and a bus arbitration circuit for selecting cells from one of the plurality of cell transmission circuits and transmitting the selected cells in a bus form, and simultaneously transmitting only one cell on one bus, A minimum cell interval control method in an ATM device which outputs cells while maintaining a minimum cell interval so as not to exceed a transmission band of a line contract. 3. A minimum cell interval control device in an ATM device for transmitting a cell generated by a cell generation circuit to an ATM network, comprising: a plurality of storage means corresponding to the number of line contracts for temporarily storing cells; A control unit for controlling writing and reading to and from the storage unit, wherein the control unit distributes received cells to the storage unit and stores the cells; and stores the cells stored in the storage unit at least the minimum cell interval. A provided with a transmission control unit for transmitting to the ATM line at intervals of
The minimum cell interval control device of the TM device. 4. A minimum cell interval control device in an ATM device for transmitting a cell generated by a cell generation circuit to an ATM network, comprising: a plurality of storage means corresponding to the number of line contracts for temporarily storing cells; A control unit for controlling writing and reading to and from the storage means, wherein the control unit converts received cells into VP units or VCs which need shaping.
A reception control unit for distributing and storing cells in the storage unit for each unit, a transmission control unit for transmitting cells stored in the storage unit to the ATM line at intervals of a minimum cell interval or more, and transmitting only one cell to the bus A minimum cell interval control device of an ATM device provided with a bus arbitration circuit for arbitrating.