JP2001237710A - Binary number conversion circuit of binarized decimal number - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert individual digits of a binarized decimal number into a binary number at high speed by using a conversion table and to simultaneously add them in parallel by a three input two output addition circuit tree to perform addition processing at a high speed. SOLUTION: The binary number conversion circuit 1 of a binarized decimal number is provided with a binarized decimal data register 10 for storing a binarized decimal number which is to be converted, conversion tables 11 to 18 for storing the binary numbers corresponding to the numerical values of 1 to 9 of the respective digits of the binarized decimal number, a three input two output addition circuit tree 20, which simultaneously reads and partially adds the binary numbers corresponding to the whole digits of the binarized decimal number from the conversion tables 11 to 18, partial sum storage resisters 21 and 22 for storing two outputs partially added by the three input two output addition circuit tree, a binary addition circuit 30, which binary-adds the partial addition outputs of the partial sum registers and a binary data register 40 storing the output of a binary addition circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary conversion of a binary-coded decimal number, and in particular, reads a conversion constant from a table storing binary numbers of each digit of the binary-coded decimal number and adds the conversion constant with a three-input two-output addition circuit tree. And speeding up.

[0002]

2. Description of the Related Art In a conventional decimal-to-binary conversion circuit for converting each digit, there is a method shown in FIG. This is because the selector 51 cuts out the binary-coded decimal sequence stored in the binary-coded decimal data register 52 by one digit (4 bits) from the upper bit by the selector 51 and a binary adder (three-input adder) 54 Of the binary register 55, in which the output of the binary adder 54 obtained in the previous cycle is stored, and the shifter 53 multiplies the output by 8 (3 bit shift) and 2 times (1 bit shift). ) Then the second input and the third
By inputting to each input and performing binary addition, 10
This is a system for performing binary-to-binary conversion. The three-bit shift and the two-bit shift correspond to an operation of increasing the digit of binary-coded decimal by 10 times. The above method is used every cycle,
Since one digit of the binary number is cut out and added to the result of the previous cycle while performing digit alignment and then converted to a binary number, the total cycle required to convert to a binary number is only the number of digits of the binary coded decimal number. This is necessary, and there is a problem that the processing time increases when the number of binary coded decimal numbers to be converted is large.

Further, in a decimal-to-binary conversion circuit for every two digits, there is a method shown in FIG. This decimal-to-binary conversion circuit is a binary-to-binary 1 that selectively selects two binary-coded decimal numbers.
A 0-ary data selector 61, a binary-coded decimal data register 62 for storing a binary-coded decimal number, and a 3-input 2-output adder (CSA: Ca) for separately outputting a sum and a carry
An adder (rry save adder) 63, a three-input two-output adder 64, a two-input adder 65, and a binary data register 66 for storing the binary number of the output of the two-input adder 65. In this method, two digits of a decimal number are cut out every cycle, and the result of the previous cycle is multiplied by 100 (64 times +3).
(2 times + 4 times) the upper digit of the 2-digit binary coded decimal number to be converted to 10 times (8 times + 2 times), and the lower digit as it is (1 time), and adding it to the binary number Because of the conversion, the total number of cycles required to convert to a binary number is (number of decimal digits) / 2 minutes. Although it has twice the performance as compared with the above-described processing for every single digit, if the number of binary coded decimal numbers to be converted is large, this also has a problem that the processing time becomes long.

Further, according to Japanese Patent Application Laid-Open No. S59-177646, there is provided a conversion means for selecting one digit of a binary-coded decimal number and converting the data into binary data. Has been described in which a dedicated memory for storing .alpha. Is read and converted and added digit by digit. In the present invention, the conversion is speeded up by reading the binary form data from the memory, but the speedup is not sufficient because the conversion and addition are performed digit by digit.

[0005]

In the case where the number of digits of the binary coded decimal number is large, the conventional technique requires a long processing time for conversion. This is for converting binary coded decimal numbers one digit at a time or two digits at a time. Therefore, binary evolution 10
By reading a table that stores a binary number of each digit of a decimal number, each digit of a binary-coded decimal number is converted into a binary number at a high speed, and the three-input two-output addition circuit tree is added simultaneously in parallel to increase the speed.

An object of the present invention is to reduce the conversion processing time by using a conversion table for converting eight digits of a binary-coded decimal number at a time and a 3-input / 2-output addition circuit tree.

[0007]

SUMMARY OF THE INVENTION Therefore, according to the present invention,
In a conversion circuit for converting a binary-coded decimal number into a binary number,
A binary-coded decimal data register for storing a binary-coded decimal number of a converted numeric value, a conversion table for storing, for each digit, a binary number corresponding to each digit from 1 to 9 of the binary-coded decimal number; A three-input two-output addition circuit tree for simultaneously reading out and partially adding binary numbers corresponding to all digits of a binary-coded decimal number from a conversion table, and a partial sum storing two partially added two outputs of the three-input two-output addition circuit It is characterized by comprising a storage register, a binary addition circuit for performing binary addition on the partial addition output of the partial sum register, and a binary data register for storing the output of the binary addition circuit.

Further, in a conversion circuit for converting a binary-coded decimal number into a binary number, a binary-coded decimal data register for storing a binary-coded decimal number of a value to be converted, and a digit from 1 to 9 of each digit of the binary-coded decimal number A conversion table for storing a binary number corresponding to the numerical value of each digit, and a three-input two-output adding circuit tree for simultaneously reading out and partially adding binary numbers corresponding to all the digits of the binary-coded decimal number from the conversion table. A three-input two-output addition circuit, comprising: a binary addition circuit for binary-adding two outputs obtained by partially adding the tree; and a binary data register for storing an output of the binary addition circuit.

[0009] Further, the conversion table includes a binary code corresponding to each of the most significant digit to the least significant digit of the binary-coded decimal number.
A binary number is stored, accessed by a binary coded decimal value of each digit, and the binary number is read.

[0010] Further, the three-input two-output addition circuit tree has two
The bit width of all the digits of the evolved decimal number is made the same as the bit width of the most significant digit, and the binary number of each digit is partially added in parallel by connecting a three-input two-output addition circuit in multiple stages, and the sum component and It is characterized in that two of the carry component are output.

Further, the three-input two-output addition circuit tree has two
The bit width of each digit of the evolved decimal number is set to the effective bit width of each digit, and the binary number of each digit is partially added in parallel by connecting a three-input / two-output addition circuit in multiple stages, so that a sum component and a carry component are obtained. Is output.

Further, the partial sum storage register comprises a partial sum storage register corresponding to a sum component of the partial sum and a partial sum register corresponding to a carry component of the partial sum.

[0013]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment. Referring to FIG. 1, binary evolution 1
The 0-ary binary conversion circuit 1 includes a binary-coded decimal data register 10 for storing a binary-coded decimal number 000, and a binary-coded 1
The conversion table 11 for the first digit to the eighth digit for storing the binary number of each digit of the 0-digit number and the conversion table 18 for the eight digits and the binary numbers output from the conversion tables 11 to 18 are added in parallel and multistage by adding three inputs and two outputs. A partial sum (1) storage register 21 and a partial sum (2) storage register for respectively storing a three-input two-output addition circuit tree 20, a sum component 210 and a carry component 301 output from the three-input two-output addition circuit tree 20 22 and
Binary addition of the outputs of the partial sum (1) storage register 21 and the partial sum (2) storage register 22 to output a binary number 2
A binary addition circuit 30 and a binary data register 40 for storing an output of the binary addition circuit are provided.

The operation of this embodiment will be described with reference to FIG. 1. Binary-coded decimal data 000 to be converted is input to binary-coded decimal data register 10. Bit data 101, 102, 103, 104 for each digit (one digit is 4 bits) from the most significant digit of the binary-coded decimal data register
105, 106, 107, and 108 are input to the corresponding conversion tables 11, 12, 13, 14, 15, 16, 17, and 18, and a binary number 20 multiplied by 10 to the nth power (n = 0 to 7)
1, 202, 203, 204, 205, 206, 20
7 and 208 are output from the respective conversion tables.
(The first digit conversion table 11 is 10 7 times, the second digit conversion table 12 is 10 6 times, and the third digit conversion table 13
Is the fifth power of 10; the fourth digit conversion table 14 is the fourth power of 10; the fifth digit conversion table 15 is the third power of 10; the sixth digit conversion table 16 is the second power of 10; Table 1
7 is a power of 10 and the 8th digit conversion table 18 is 0 of 10
Outputs a multiplied binary number. ) All the bits 201 to 208 obtained by converting each digit into a binary number multiplied by 10 to the power of n are input to the three-input two-output addition circuit tree 20 in parallel with all bits, and partial sums 210 and 211 are obtained. Two partial sums 2 composed of the sum component and the carry component
10 and 211 are stored in the partial sum storage registers 21 and 22. Outputs 300 and 30 of partial sum storage registers 21 and 22
1 is input to the two inputs of the binary adder 30, and the added output 400 of the binary adder 30 is input to the binary data register 40 to obtain a binary converted from a binary-coded decimal number.

Referring to FIGS. 3A to 3H showing the conversion tables 11 to 18 of the respective digits,
The first digit from the top of the evolutionary decimal data is multiplied by 10 7, 2
Digit 10 times 6 times, 3rd digit 10 5 times, 4th digit 10 4 times, 5th digit 10 3 times, 6th digit 10 2 times, 7 This shows that the table outputs a binary number whose first digit is 10 times and the eighth digit is 10 times.
An 8-digit decimal number can be converted into a binary number at a time by adding all the bits of the binary number output from this table in parallel.

Next, the operation of this embodiment will be specifically described with reference to FIG. FIG. 4 is a diagram for explaining the operation of converting the binary-coded decimal data "12345678" into binary data and the operation of each component circuit based on FIG. 8-byte binary-coded decimal data 0 to be converted
00 is loaded into the binary-coded decimal data register 10.
Next, 10 digits are set for each digit from the most significant digit (one digit is 4 bits).
1, 102, 103, 104, 105, 106, 10
Conversion table 1 corresponding to 4-bit data 7 and 108
1, 12, 13, 14, 15, 16, 17, 18 and 27-bit binary data 20 multiplied by 10 n
1, 24-bit data 202, 20-bit data 20
3, 17-bit data 204, 14-bit data 20
5, 10-bit data 206, 7-bit data 207,
The 4-bit data 208 is output from each conversion table. The output data 201 to data 208
Are input in parallel to the three-input two-output addition circuit tree 20 to obtain two partial sums 210 and 211 of a sum component and a carry component. The two partial sums are stored in the partial sum storage registers 21 and 22.
To be stored. Output 30 of partial sum storage registers 21 and 22
0 and 301 are added by the binary adder 30, and the addition result 400
Get. By storing the addition result in the binary data register 40, the 8-digit binary-coded decimal can be converted into a binary number at a time. From the above description, the binary-coded decimal data “12345678” is converted to the binary data “1011110”.
The speed of the operation for converting to "001100100100110" is realized.

Next, a second embodiment will be described. FIG.
, The binary conversion circuit 2 of the binary-coded decimal system is different from the first embodiment in that a 3-input 2-output addition circuit tree is provided except for the partial sum (1) register 21 and the partial sum (2) register 22. A modification in which the two outputs 20 are directly input to the binary addition circuit 30 is performed. Obviously, by omitting the timing of storing the partial sum (1) register 21 and the partial sum (2) register 22, the speed can be further increased as compared with the first embodiment.

Further, the conversion tables 11 to 18 may use the effective bit width of the binary value of each digit as the data length, or the effective bit width of the binary value of the highest digit may be used as the data length of all digits. Obviously, the data length can be modified to reduce the number of gates of the 3-input / 2-output addition circuit tree 30.

[0019]

As described above, according to the present invention, by converting 8-digit binary-coded decimal data into binary data at a time, the conventional operation cycle of converting one digit or two digits at a time can be realized. Since conversion into a binary number can be performed in two cycles or one operation cycle, there is an effect of improving the conversion speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram illustrating binary values stored in the conversion tables of FIGS. 1 and 2;

FIG. 4 is a diagram illustrating the operation of the first embodiment.

FIG. 5 is a diagram illustrating a conventional technique.

FIG. 6 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 binary-coded decimal binary conversion circuit 2 binary-coded decimal binary conversion circuit 10 decimal data register 11 to 18 conversion table 20 3-input / 2-output addition circuit tree 21 partial sum (1) storage register 22 partial sum ( 2) Storage register 30 Binary adder 40 Binary data register

Claims (6)

[Claims] 1. A conversion circuit for converting a binary-coded decimal number to a binary number, comprising: a binary-coded decimal data register for storing a binary-coded decimal number of a value to be converted; A conversion table for storing a binary number corresponding to each digit of each digit, and a three-input two-output addition circuit tree for simultaneously reading out and partially adding binary numbers corresponding to all digits of a binary-coded decimal number from the conversion table. A partial sum storage register for storing two outputs obtained by partial addition of the three-input two-output addition circuit; a binary addition circuit for performing binary addition on the partial addition output of the partial sum register; and an output of the binary addition circuit. A binary data register, comprising: a binary conversion circuit for converting a binary number into a decimal number. 2. A conversion circuit for converting a binary-coded decimal number to a binary number, comprising: a binary-coded decimal data register for storing a binary-coded decimal number of a value to be converted; and a digit from 1 to 9 for each digit of the binary-coded decimal number. A conversion table for storing a binary number corresponding to each digit of each digit, and a three-input two-output addition circuit tree for simultaneously reading out and partially adding binary numbers corresponding to all digits of a binary-coded decimal number from the conversion table. The two outputs obtained by partially adding the three-input two-output addition circuit tree are represented by 2
A binary conversion circuit for converting a binary number to a decimal number, comprising: a binary addition circuit for performing binary addition; and a binary data register for storing an output of the binary addition circuit. 3. The conversion table stores a binary number corresponding to each of a most significant digit to a least significant digit of a binary-coded decimal number, accesses the binary-coded decimal number using a binary-coded decimal value of each digit, and 3. A binary conversion circuit according to claim 1, wherein said binary number is read. 4. The three-input two-output addition circuit tree, wherein the bit width of all the digits of the binary-coded decimal number is the same as the bit width of the most significant digit, and the binary number of each digit is added to the three-input two-output number. 3. The binary conversion circuit according to claim 1, wherein the circuits are connected in multiple stages and partial addition is performed in parallel to output two of a sum component and a carry component. 5. The three-input two-output addition circuit tree, wherein the bit width of each digit of the binary-coded decimal number is set to an effective bit width of each digit, and the binary number of each digit is multi-staged by a three-input two-output addition circuit. 3. The binary conversion circuit according to claim 1, further comprising: a partial conversion circuit for performing partial addition in parallel to output a sum component and a carry component. 6. The partial sum storage register comprises: a partial sum storage register corresponding to a sum component of the partial sum; and a partial sum register corresponding to a carry component of the partial sum. Item 2. The partial sum register according to Item 1.