JP2001236182A - Data reproducing device or data storing and reproducing device and its controlling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To construct a data reproducing device making reusing easy, a data storing and reproducing device and a data reproducing and controlling method or a data reproduction and storage controlling method in the case of reusing an interface with a host and a backup storage in another system. SOLUTION: Each time the end of data transfer is decided on the basis of a transfer control signal from a host device, an error detecting means stops the data transfer to the host device through a transfer requesting means in the case of disagreement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproduction apparatus, a data reproduction storage apparatus, a data reproduction control method, and a data reproduction storage control method. The present invention relates to a data reproducing apparatus or a data reproducing storage apparatus having an interface with the means, and a technique which can be transferred to a reproducing apparatus recorded on a medium such as an optical disk using the same.

[0002]

2. Description of the Related Art As a removable storage device such as a personal computer, a CD (Compact Disc) -ROM (Re-
ad Only Memory) drive or DVD (Digital
Versatile Disc) -ROM drive is used.

In such a drive, a CD-ROM or a D-ROM
Processing of the signal read from the VD-ROM is performed by a data reproduction device or a data reproduction storage device, for example,
Read channel, servo, CD-ROM decoding, DVD decoding,
Functional blocks such as a host interface, a temporary storage unit, and a system control microcomputer are configured as a data reproduction device or a data reproduction storage device.

[0004] As an interface with a host of a CD-ROM or DVD-ROM drive, for example, ATAPI (AT Attac technology) described in "ATA / ATAPI technology" issued by Trikeps Corporation.
hment Packet Interface) is widely used. This interface includes registers such as a task file register that can be read / written by both the host and the user.

Also, data transfer corresponding to a command from the host is performed. UDMA (U
ltra Direct Memory Access) is standardized and 33M
It achieves a transfer rate of words / second (66 Mbytes / second).

To realize such high-speed data transfer, the data processing capability of a temporary storage means such as a DRAM for temporarily storing data, the data processing capability of a temporary storage means control means for controlling the data, Bus arbitration is important.

[0007] Regarding UDMA, various transfer states are changed depending on the states of the host and the device.

Here, an example is given. Considering the case of outputting data to the host, when the device side has no data to output to the host and stops generating the data strobe signal, it is in the device pause state, and the host side cannot receive data from the device. When the host negates the ready signal and requests the device to stop generating the data strobe, the host is in the pause state.

Negating the ready signal output by the device itself and requesting the host to terminate the data transfer is called device termination. Conversely, the host terminates the data transfer to the device. Requesting is called host termination.

At present, the reading speed of the above-mentioned CD-ROM drive has been improved from the standard speed to 40 times or more, and
-The read speed of ROM drives is also improving.

In order to increase the reading speed, the data processing capacity of a temporary storage means such as a DRAM for temporarily storing the above data and the data processing capacity of a temporary storage means control means for controlling the data are considered. In addition to the improvement in speed, it is necessary to increase the speed of the system control microcomputer that controls the entire control and to reduce the load.

On the other hand, ATAPI may be used for interfaces other than the optical disk drive due to its widespread use. For example, a recording / reproducing system in which an optical disk is replaced by a semiconductor storage device such as a flash memory, or an AV (Audio V
isual) A system for recording / reproducing data can be considered.

When the ATAPI unit is reused in a different system, the temporary storage means such as the DRAM and the control means are not always the same, and the same data processing capability is not always obtained. For example, in a reproduction system that performs error correction, there is a possibility that error correction may be performed on the temporary storage means, and the data processing time allocated to ATAPI processing is reduced, so that the data processing capacity is also reduced.

To cope with this, the capacity of a temporary data storage means (hereinafter, FIFO: First-In First-Out) for ATAPI to input / output data to / from the host is increased.
It is conceivable to start data transfer after sufficiently storing data in the FIFO, but that would increase the circuit scale.

[0015]

The problem to be solved by the present invention is as follows: (1) Although the data transfer is not completed during the data transfer, the host terminates the data transfer (hereinafter referred to as host Terminating).

When the user wants to restart the data transfer, reset the data transfer and restart the data transfer. When the data transfer is completed, the error detection code CRC (CRC: Cyclic Redu
ndancy Check) is calculated on both the host side and the device side (apparatus side).
It is necessary to compare the C calculation result with the CRC calculation result calculated by the device itself and output the comparison result.

Similarly, when the host termination occurs a plurality of times during the data transfer and the data is divided and the data transfer is performed, the device performs the CRC calculation for the number of times the host termination occurs and the CRC calculation output from the host. It is necessary to compare the result with the result and update the result in an error register (means for holding a result indicating that an error has occurred).

When the interface with the host device is reused in a system having a different system configuration such as a magnetic disk reproducing device other than the optical disk reproducing device, the operation performed by the host at the end of data transfer and the operation desired by the user are different. .

For example, whether or not the transfer status check (check whether or not data transfer is normally performed) performed by the host at the end of data transfer is performed every time,
When the host termination occurs a plurality of times during the data transfer, whether or not the data transfer restart processing is automatically performed is given.

Therefore, when the interface with the host device is reused for a different system configuration, and when the data transfer is performed in a plurality of times, the options that can be executed by the user are expanded according to the system configuration, and the system is changed to a different system. The challenge is also to adapt.

(2) If there is no transferable data in the temporary storage means, the device stops generating the data strobe signal until the transferable data is stored in the temporary storage means. This is called a device pause. Depending on the interface standard, a new signal line exchange with the host occurs when the device pause is performed, so that it takes time to resume data transfer, leading to a reduction in the data transfer rate.

Therefore, when the interface with the host device is applied to a system having a different system configuration such as a magnetic disk reproducing device other than the optical disk reproducing device, a device pause may occur depending on the system. There is a problem. This problem can be solved by increasing the capacity of the temporary storage means FIFO of the first interface means for temporarily storing data to be output to the host, but causes a problem of an increase in circuit scale. Therefore, it is an object of the present invention to increase the versatility of this interface and to support different systems.

(3) When the interface means for the temporary storage means is reused for a different system, the temporary storage means such as DRAM and the control means for the data reproduction apparatus or the data reproduction storage apparatus are the same. Not exclusively. Therefore, it is an object of the present invention to enable reuse of an interface according to a temporary storage unit to be used and a unit for controlling the temporary storage unit.

(4) During the data transfer to the host, the host interrupts the data transfer (host pause), and there is no response after that, or a device pause occurs on the device side. For example, when the microcomputer does not perform a response after checking the transfer state after a predetermined time, it is possible to end the data transfer by resetting and initializing.

However, disconnection without complying with the communication protocol of the interface with the host is not preferable because the behavior of the host cannot be predicted and the register must be reset. Therefore, it is an object of the present invention to terminate data transfer normally without forcibly resetting on the user side.

(5) Interface ATAPI UDMA communication speed is standardized to 66 MB / s, and five modes are defined according to the transfer rate. For example, when the operating frequency of a system using a data reproducing apparatus or a data reproducing storage apparatus capable of handling up to 66 MB / s is lowered from f (f: a positive real number) to f / 2, the cycle of the data strobe is naturally The w clock (w: natural number) is 2w clock, and when the maximum value of the standard value is w clock, it is a violation of the standard.

Therefore, the modes that can be supported by the system are limited, and a system configuration that can operate even when the operating frequency is lowered is constructed.

As described above, it is an object of the present invention to construct a system in which interface options such as ATAPI used for a recording / reproducing system and the like have a wider range of user options according to the system, and to facilitate reuse.

[0029]

The outline of the invention disclosed in the present invention will be described.

(1) When a host termination occurs and data is divided and transferred, a data transfer setting means that can be set from outside is provided to enable automatic restart of data transfer and reduce the burden of user setting. To reduce. If the automatic transfer is not performed, a flag is provided for notifying that the host termination has occurred to the microcomputer that controls the entire system.

Further, it is performed for each divided data transfer.
The comparison result of the CRC calculation is set in the flag every time, and when the data transfer is completed, the result of the comparison is updated to the error register, and the CRC is set in the divided data transfer.
Indicates that a comparison error has occurred.

Thus, the microcomputer can recognize that the host termination has occurred, and when a comparison error occurs during the divided transfer, stop the data transfer restart and do not perform useless data transfer. As a result, the data transfer rate can be improved, and it is possible to cope with changes in the system configuration and host operation to be built according to the result.

(2) The amount of data that can be transferred to the host and stored in the FIFO is monitored, and if the amount of transferable data falls below a predetermined value, the transfer rate is reduced, that is, the minimum width of the cycle of the data fetch signal. Is set to be wider than before the predetermined value falls, thereby lowering the data transfer rate.

At this time, the transfer rate of the data fetch signal is set lower than the worst data transfer rate of the temporary storage means control means.

(3) The FIFO is controlled by a data request and a data acknowledgment for each word to the temporary storage means, and burst transfer of a predetermined length can be realized. The burst length is made variable, and the number of requests set on the device side and the amount of transferable data in the FIFO are monitored to change the burst length and make requests.

When the remaining data amount to be transferred becomes equal to or less than a predetermined burst length, the data transfer is performed without waste by setting the data amount as the burst length.

(4) Even if there is no response from the host or device during data transfer, the device has a register capable of forcibly executing device termination from the outside, so that data transfer according to the communication protocol of the interface can be performed. The data transfer can be terminated according to a control signal for termination or a procedure for exchanging data.

(5) The data capture signal output from the interface with the host corresponds to five transfer rates of modes 0 to 4 of ATAPI UDMA (mode 4 has the highest data transfer rate).

It is assumed that the minimum period of the data strobe standard in mode 4 is w and that in mode 2 is 2w.

If the operating frequency f is halved to f / 2, the period of the mode 4 data fetch signal is doubled to 2w,
Mode 4 cannot be supported, but mode 2 w can be supported.

Therefore, when it is desired to lower the operating frequency to 1/2 and operate the system at the transfer rate of mode 2, the setting on the firmware side is set to mode 4 and the operation is performed in a pseudo manner at the period of the mode 2 data fetch signal. By doing so, a system configuration that can operate even if the operating frequency is lowered is constructed.

The problem is solved by the above means. Next, a detailed description will be given.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a data reproducing apparatus or a data reproducing and storing apparatus according to the first to twelfth embodiments of the present invention.

In FIG. 1, reference numeral 101 denotes a storage medium for reproduction, 102 denotes a pickup for reading data recorded on the storage medium 101, and 103 denotes a read channel. Reference numeral 104 denotes reproduced data, reference numeral 105 denotes a unit for demodulating the reproduced data, and reference numeral 106 denotes a temporary storage unit for temporarily storing input data. 10
Reference numeral 7 denotes a unit for performing error correction, and reference numeral 108 denotes a data bus between the temporary storage unit 106 and each processing unit.

Reference numeral 109 denotes output means for outputting data after demodulation and correction processing, and reference numeral 110 denotes a host interface, which is ATAPI in this embodiment. Reference numeral 111 denotes a temporary storage means control means for controlling data between each processing means and the temporary storage means 106. Reference numeral 112 denotes an interface with the data reproducing apparatus or a microcomputer 113 which controls the entire data reproducing and storing apparatus, and a microcomputer interface. It is. 114 is a host, 115 is a host 1
IDE (Integr
ated Device Electronics) bus or ATA bus. Further, although not shown, it also has a DVD authentication unit and an audio output unit.

Hereinafter, the flow of the signal processing of FIG. 1 will be described by taking the case of reproducing a DVD disc as an example.

In FIG. 1, a signal recorded on an optical disk 101 is read by a pickup 102, and a signal 104 digitally converted by a read channel 103 is subjected to 8-16 demodulation by demodulation means 105. 8-16 demodulation is 16
The bit input is converted into predetermined 8 bits, and a table conversion may be performed. If necessary, deinterleaving and sync detection are performed. During CD playback, CD audio decoding (not shown) and CD-ROM
, A sync detection circuit, a descrambling and a header detection circuit are used.

The demodulated data is stored in temporary storage means 106 by temporary storage means control means 111.
Temporary storage means 106 has a pointer indicating an address, is an internal I / O register arranged in the address space of microcomputer 112, is initialized by the user, and thereafter performs a ring buffer operation.

A predetermined amount of data (for example, DV
In the case of D, when one block (182 × 208 bytes) is accumulated, the temporary storage control means instructs the error correction circuit to start operation, and performs error correction processing (decoding). DV
In the case of D, the Reed-Solomon product code is corrected.

The error correction means 107 is provided in the temporary storage means 10
6 is performed on the data on the DVD, and if there is an error, after error correction, the
Perform C check and obtain data. The general processing flow of error correction includes a syndrome operation, an error determination, an Euclidean algorithm, a chain search, an error numerical operation, and a correction. In the syndrome operation, a series of input codes is read from the temporary storage means, and coefficients of a syndrome polynomial are calculated. If the coefficients of the syndrome polynomial are all zero, there is no error in the input code. If there is an error, first, an error locator polynomial and an error numerical polynomial are calculated from the syndrome polynomial by the Euclidean algorithm, and then the root of the error locator polynomial is found by a chain search to find the location of the error. Can be Based on these, an error value is calculated and a correction process is performed.

When the error correction of the predetermined data is performed, a decoding completion interrupt is generated and the microcomputer 113 is notified. When the decoding of a predetermined amount of data is completed, the microcomputer 113 sets a predetermined internal I / O register of the host interface 110 and instructs data output. In accordance with this, the host interface 110 issues a data output request to the temporary storage means control means 111. The temporary storage control unit 111 receives the data output request at a predetermined timing, and from the temporary storage 106,
Output means 109, host interface 110 (FIFO
), And data is output to the host 114 via the IDE bus 115 (or ATA bus).

The host interface 110 is capable of interfacing with a host such as a personal computer. In this embodiment, the description will be given using ATAPI as an example of the interface. About ATAPI, March 1996
It is described in "ATA / ATAPI technology" issued by Trikeps. Through the host interface 110, command input, status output, and data input / output are performed.

The host interface 110 performs data transfer between the temporary storage means 106 and the host 114 through the internal FIFO of the host interface 110 to input and output data.

The output means 109 performs descrambling processing to cancel the scramble processing applied to the data, and outputs the data to the host interface means. Also, the temporary storage means control means 111
Performs arbitration of an input / output request to the temporary storage means 106 and performs this bus control.

The above operation is continued until the command is completed or the next command is input.

The above is realized by a known technique.

The first to fourth embodiments of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

In the ATAPI, which is cited as an example of a host interface in the present invention, a process called host termination, in which the host requests and terminates data transfer regardless of data transfer completion / incomplete, is defined in the interface standard. ing.

When the data transfer is completed, an error detection code (CRC) based on the transfer data is calculated on both the host side and the device side, and the CRC calculation result input from the host is calculated on the device side. It is stipulated that the CRC operation results calculated by the device itself are compared.

Further, it is stipulated that when the data transfer is completed, the host checks whether or not the data transfer has been normally completed and checks the status.

For a system having a different system configuration such as a magnetic disk reproducing device different from the optical disk reproducing device,
Applying the above first interface means, when such host termination occurs a plurality of times during data transfer, that is, when the data transfer is divided into a plurality of times, the host or user performs the data transfer at the end of the data transfer The operation differs depending on the system configuration.

For example, whether the status check performed by the host at the end of data transfer is performed every time,
When a host termination occurs during data transfer, whether or not the data transfer restart process is automatically performed is mentioned. Accordingly, an object is to realize a data reproduction device or a data reproduction storage device according to an operation performed by a host or a user when data transfer is performed in a plurality of times due to occurrence of host termination a plurality of times. .

Therefore, the present invention is realized by providing data transfer setting means which can be set from the outside so that the user can select whether or not to automatically restart the data transfer at the end of the data transfer.

First, the case of automatically restarting the data transfer will be described.

When it is desired to complete the data transfer to the end, it is necessary to restart the data transfer from the terminated point, and it is necessary for the user to monitor the amount of untransferred data and reset the transfer. Performing the resetting process on the side increases the burden on the user. FIG. 3 shows a timing chart in the case where the data transfer is performed to the host and the host terminates the data transfer and restarts the transfer.

First, description will be made on the upper part of FIG.

When terminating the data transfer on the host side during the data transfer, the hdmardy- signal is negated first, and then the stop signal is asserted to inform the device that the data transfer is to be terminated. Then, the device negates the dmarq signal in response to the host's data transfer end request,
The data transfer is terminated by stopping the generation of the strobe signal. The host receives the negation of the dmarq signal, and assumes that the device has recognized the end of the data transfer, and can capture the CRC operation result for the transferred data (transferable data transferred on the IDE bus) at the rising edge of dmack-. Output at an appropriate timing to end the data transfer.

When the user recognizes that the data transfer has been completed even though the data transfer has not been completed,
The amount of remaining data to be transferred is estimated, and data transfer is reset to start data transfer. When resetting the data transfer, the device asserts the dmarq signal and requests the host to restart the data transfer. If the host can resume data transfer, the host performs dmack-signal assertion, hdmardy-signal assertion, and stop signal negation in order (the order of hdmardy-and stop may be reversed), and the device side Signal that you are ready to resume data transfer. In response, the device again dstr
Start generating the obe signal and resume data transfer. As described above, since there is an interval between the end of the data transfer and the restart of the data transfer, there are two problems, that is, a decrease in the transfer rate and a user's setting burden.

If the host frequently causes host termination during data transfer, it is necessary for the user to estimate the remaining data transfer amount and reset the data transfer each time, thereby further reducing the data transfer rate. Is clear.

Accordingly, FIG. 4 shows a block configuration for preventing an increase in the burden on the user and a decrease in the data transfer rate.

Reference numeral 401 denotes a signal output from the FIFO state monitoring means 202 for notifying the amount of transferable data in the FIFO (remaining data transfer amount).
I / F signal 404 output from the device to the device, 401
Is a transfer state determining means for determining the current transfer state from the signal of The host termination detection signal 405 is output from the transfer state determination unit 402 and is input to the host I / F signal generation unit 406. 4
07 is an I / F signal output from the device to the host.

Next, a case where the data transfer is automatically restarted on the device side (lower view in FIG. 3) will be described in conjunction with FIG.
3 is the same as the upper part of FIG. 3 up to the point where the host negates the dmack- signal. Here, the transfer state determination unit 406 determines whether the information 401 from the FIFO and the I /
When recognizing the occurrence of host termination due to incomplete data transfer from the F signal 404, it notifies the host I / F signal generation means 406 to reassert the dmarq signal.

According to the above method, it is possible to quickly restart data transfer without user intervention.

As described above, when host termination occurs during data transfer, data transfer is automatically restarted, so that even if the host generates host termination during data transfer, the user side can obtain the remaining data. There is no need to monitor the transfer amount and reset the transfer, and the data transfer can be realized without the burden on the user.

Next, a case where the data transfer is not automatically restarted will be described.

As described above, for each data transfer performed in a divided manner, an error detection code (CRC) based on the transfer data is calculated on both the host side and the device side.
It is necessary to compare the error detection code input from the host with the error detection code calculated by the device itself.

However, when the data reproducing device or the data reproducing storage device is reused, depending on the host and the system configuration, a status check is performed for each divided data transfer or a CRC error occurs during the data transfer. Occurs, it is necessary to stop the data transfer.

Accordingly, means for coping with this will be described with reference to FIGS.

Reference numeral 501 denotes a C for performing a CRC operation on all transfer data 503 output from the device to the host 502.
RC operation means 504 is the operation result. 5
Reference numeral 05 denotes a CRC calculation result obtained by the host performing a CRC calculation using the transfer data 503. 506 is the two C
Compare the RC calculation results, and if they do not match, compare error signal 5
07, and 508 and 509 for setting the comparison error signal.
2. Reference numeral 510 denotes a signal for clearing error information of the CRC error setting means 2, reference numeral 511 denotes a signal indicating that a CRC error has occurred during data transfer, and reference numeral 512 denotes a signal for the host to check the state after the end of the data transfer. A register and a status check register.

The CRC comparison error signal 507 output from the CRC calculation result comparison means 506 is set in the CRC error setting means 1 and 2 respectively. CRC
Even if an error is set once, when the next data transfer is automatically restarted, the error setting means 2 outputs the error information by the signal 510 (using the host interface signal) for clearing the error information of the CRC error setting means 2. Is cleared. On the other hand, once the CRC error information is set, the CRC error set means 1 is not cleared until cleared by the user. In short, C
The RC error set register 2 stores the CR at the end of each data transfer.
The CRC error set register 1 reflects the result of the C operation comparison, and the CRC error set register 1 reflects the CRC error generated during data transfer. The status check register 512, which is checked by the host 502 when the data transfer is completed, includes the CRC error setting means 1
Error data is set. In addition, the host termination detection signal 405 output from the transfer state determination unit 402 in FIG. 4 allows the user to recognize that the data transfer has ended due to the occurrence of host termination. Therefore, even when an error occurs in the host termination during the data transfer, the user or the host can check the status every time the transfer is completed.

Thus, when the user detects a CRC error at the end of the data transfer before the data transfer is completed, the data transfer can be restarted from the beginning without waiting for the completion of the data transfer, and the data transfer rate can be improved. Leads to.

As described above, the versatility of the system configuration can be provided, the options of the processing by the user can be expanded, and the operation according to the system to be constructed can be performed.

Next, a fifth embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

When reproducing a DVD, the signal read by the pickup is output from the host interface through the processing of the demodulation means, error correction means, output means, and temporary storage means as described above.

Further, the time until each processing unit can read data from the temporary storage unit and the maximum waiting time for temporary storage unit access are determined according to the frequency and access time of each processing unit access request to the temporary storage unit.

In addition, priority setting, access method of temporary storage means (such as burst data transfer in which one means continuously uses the data bus exclusively with temporary storage means, etc.), and other processing means The maximum waiting time differs depending on the access frequency and the like.

Therefore, when the access frequency and access time of the processing means other than the host interface increase, the data transfer rate from the temporary storage means control means to the host interface decreases.

Considering that this host interface portion is reused for another system, if the data processing capability of the temporary storage means control means for the host interface is reduced, there is a possibility that data cannot be transferred continuously to the host. Comes out. This is the state of the device pause described above. Depending on the interface standard, when a device pause state occurs, it takes time until data transfer is restarted due to the newly generated signal line exchange with the host, which leads to a reduction in the data transfer rate.

Therefore, when the interface means with the host device is applied to a system having a different system configuration such as a magnetic disk reproducing device other than the optical disk reproducing device, a device pause may occur depending on the system. is there. In addition, the behavior of the host varies widely, and some hosts may perform host termination when a device pause occurs.

This problem can be solved by increasing the capacity of the temporary storage means FIFO of the first interface means for temporarily storing data to be output to the host, but the problem of an increase in circuit scale Invite. Therefore, it is an object of the present invention to make it possible to reuse an existing interface circuit without modifying the circuit.

FIG. 2 is a block diagram showing a configuration for solving this problem. 201 is an internal FIFO which is a means for the host interface 110 to temporarily store data.
Reference numeral 202 denotes FIFO monitoring means for monitoring the state of the internal FIFO. Reference numeral 203 denotes an internal FIFO internal data remaining amount notification signal.
4 outputs a switching signal 205. Reference numeral 206 denotes a strobe generating unit 1 used for normal transfer, and reference numeral 207 denotes a strobe generating unit 2 for generating a strobe used when the amount of transferable data in the internal FIFO becomes small. A selector 208 selects each strobe signal, and outputs a data strobe signal 209 that is actually used as an interface with the host.

The FIFO status monitoring means 202 has an internal FI
The amount of data that can be transferred by the FO 201 is monitored, and when the amount of data falls below a predetermined value, the internal FI
It notifies that there is little data that can be transferred in the FO. In response, the strobe switching means 204 outputs a strobe switching signal 205 to the selector 208. The selector 208 uses the strobe generated by the strobe generating means 1 as a data strobe signal with the host when the transferable data remaining in the FIFO is equal to or greater than a predetermined value. Is smaller than a predetermined value, that is, the strobe switching means 2
04 switches the strobe switching signal 205 to the selector 208
When the data is output to the host, the strobe generating means 2 is used as a data strobe signal with the host.

At this time, the data transfer rate is reduced by making the minimum width of the data strobe cycle output from the data strobe generation means 2 wider than before the predetermined value falls below. The transfer rate of the data strobe output from the temporary storage means is set to a lower transfer rate than the worst data transfer rate of the control means. Also adaptable.

Next, a sixth embodiment of the present invention will be described with reference to FIG.

When the interface with the temporary storage means is reused, the temporary storage means such as DRAM and the temporary storage means control means are not necessarily the same. Therefore, the FIFO control is controlled by a data request and a data acknowledgment word by word, a burst transfer of a predetermined length can be realized, and the burst length is made variable.
Request can be made from ATAPI side. Furthermore, by monitoring the total number of data transfer requests and the remaining amount of the FIFO and changing the burst length and requesting them, various temporary storage means (EDODRA
M (Extended Data Output DRAM), Synchronous DRAM (Dyn
amic Randam Access Memory), SRAM (Static Randam Acc
ess Memory) and the specification change of the temporary storage means control means. An example for realizing this is shown in FIG.

Reference numeral 601 denotes a host interface internal FIFO.
602 is information indicating the state of the FIFO, which has been output to the FIFO state monitoring means 603. Output from the FIFO state monitoring means 603 is a signal 604 indicating the remaining amount of the FIFO. The data length 607 to be transferred is set from the microcomputer 605 to the data request / burst length output unit 606. The data request / burst length output means 606 also outputs the fixed burst length 608 used in the system. The fixed burst length 608 is a signal output in synchronization with the data request signal, and is a signal for indicating how many bytes of data are transferred for one data request. This fixed burst length 608 can be changed according to the temporary storage means used and the temporary storage means control means 609 for controlling the temporary storage means.

Data request / burst length output means 6
Reference numeral 06 denotes a data request signal 6 using the input three signals, (1) a signal 604 indicating the remaining amount of the FIFO, (2) a data length 607 to be transferred, and (3) a fixed burst length 608.
10 and a burst data amount (burst length) 611 for the data request.

Data request / burst length output means 6
06 is the data length 607 to be transferred and the fixed burst length 60
The burst length 611 is determined by comparing the sizes of the burst lengths. If the data length 607 to be transferred is smaller, the data length 607 to be transferred is set to the burst length 611; otherwise, the fixed burst length 608 is set to the burst length 611.

For example, when the data length 607 to be transferred is larger than the fixed burst length 608, the fixed burst length 608 is sequentially subtracted from the data length 607 to be transferred, and the remainder becomes smaller than the fixed burst length 608. , And outputs the remainder as a burst length 611.

Thus, when the interface with the temporary storage means is reused, even if the temporary storage means such as a DRAM or the temporary storage means control means is changed, the specification or logic of the temporary storage means control means may be increased. In addition, it is possible to correspond to a page mode or a hyper page mode of various temporary storage means EDODRAM, synchronous DRAM, SRAM and the like.

Next, a seventh embodiment of the present invention will be described with reference to FIG.

During the data transfer to the host, the host stops the data transfer (host pause), and if there is no response after that, or a device pause occurs on the device side, and the data transfer is stopped by the host. In the case where the transfer is not performed, for example, if the microcomputer checks the transfer state after a predetermined time and determines that there is no response, it is possible to terminate the data transfer by resetting and initializing.

However, if the reset is forcibly performed during data transfer, the behavior of the host cannot be predicted due to the reset of the task file, and the host may malfunction. In addition, the registers need to be reset, which puts an extra load on the user.

In short, in any case, it is not preferable to forcibly stop the handshake with the host without following the procedure of exchanging a control signal or data for terminating ATAPI. Thus, means for solving this problem is shown in FIG.

A host 701 outputs an I / F signal 703 from the host I / F signal generation means 702 to the host. Reference numeral 704 denotes a data transfer end request unit, which receives a data transfer end request command 706 output from the microcomputer 705 and outputs a data transfer end request signal 707 to the host I / F signal generation unit 702.

Actually, the data transfer end requesting unit 704 outputs the I / F signal output from the host I / F signal generating unit 702.
A bit (register) for controlling the / F signal,
By setting this control bit by the user, a data transfer end request is made (the dmarq signal is negated).

Therefore, even when the ATAPI side does not respond during data transfer or when there is no response from the host side or the device side,
A register for executing forced device termination is provided so that the microcomputer can request device termination. This allows ATAPI to be reset without resetting the data transfer even if the data transfer is terminated by the host and there is no response from the host, or if the data transfer is terminated by the device for some reason.
It is possible to end the data transfer by an end procedure according to the standard.

Next, an eleventh embodiment of the present invention will be described.

The communication speed of UDMA of the interface ATAPI is standardized up to 66 MB / s.
Two modes are defined. It is assumed that the relationship between the data strobe cycle and the mode is defined by the following standard.

Mode 0: Data strobe cycle, 8w (max) Mode 1: Data strobe cycle, 6w (max) Mode 2: Data strobe cycle, 4w (max) Mode 3: Data strobe cycle, 3w (max) Mode 4: Data strobe cycle, 2w (max) Depending on the use of a system using a data reproducing device or a data reproducing storage device, it is necessary to operate at a different operating frequency due to problems such as specifications of the corresponding system configuration and power consumption. Need arises.

Therefore, what happens when the operating frequency is lowered will be considered.

When the operating frequency of the data reproducing apparatus or the system using the data reproducing and storing apparatus is reduced from f (f: a positive real number) to g (g: a positive real number, where f> g), one clock Since the period is f / g times, for example, if the period of the data strobe in mode 4 is designed to be 2w (w: real number), when the operating frequency is reduced from f to g, f / g 2w · (f / g), which is the maximum of the standard value
When the value is 2w, since (f / g)> 1, 2w ·
(f / g)> 2w, violating the standard.

Here, the operating frequency of the system is changed from f to g.
When the data strobe cycle is reduced to: mode 0: data strobe cycle, 8w → 8w · (f / g) mode 1: data strobe cycle, 6w → 6w · (f / g) mode 2: data strobe cycle, 4w → 4w · (f / g) Mode 3: Data strobe cycle, 3w → 3w · (f / g) Mode 4: Data strobe cycle, 2w → 2w · (f / g) All are violations of the standard.

Here, attention is paid to the standard values of the data strobe cycle of mode 4 and the data strobe cycle of mode 2 when the operating frequency is lowered.

The data strobe period when the operating frequency is reduced to g is 2w · (f / g).

When the operating frequency is f, the data strobe cycle is 4w.

Therefore, even if 2f / g does not exceed 2, that is, even if the operating frequency is reduced to half, since the data strobe standard of mode 2 is satisfied, mode 2 can be handled. Mode 1 and mode 0 can be similarly handled.

That is, the data transfer is performed as the UDMA mode 2 by setting the firmware side to the mode 4 and operating in the data strobe cycle of the mode 2 in a simulated manner.

Therefore, the mode that can be operated is limited by limiting the modes that can be supported by the system and by setting the mode so that the period of the data strobe when the operating frequency is lowered does not exceed the standard value of the mode before the operating frequency is lowered. We proposed a new data system configuration.

As described above, by solving the above-mentioned problems, the interface means such as the ATAPI used in the recording / reproducing system is constructed so that the user's options can be expanded according to the system, and the reuse can be easily performed. did.

[0122]

As described above, according to the present invention, in the interface means such as the ATAPI used for the recording / reproducing system, the data transfer setting means which can be set externally when the data is divided and transferred is provided. By enabling automatic restart of data transfer, reducing the burden on user settings, and providing a flag to the microcontroller that indicates that host termination has occurred, it is possible to respond to changes in the system configuration and host operation that are built. Becomes possible,
By changing the width of the data strobe signal to the host and suppressing the occurrence of device pauses, the versatility of the system is improved, it can be adapted to different systems, the burst length is variable, and the total number of requests and FIFO on the device side
By monitoring the amount of data that can be transferred within the host and requesting it by changing the burst length, it is possible to handle various types of temporary storage means such as DRAM by performing data transfer without waste. Even if there is no response from the device, the device has a register that allows the user to forcibly execute device termination at an arbitrary timing, thereby exchanging control signals or data for terminating data transfer according to the interface's communication protocol. Data transfer can be completed according to the above procedure, and operation is possible by setting the mode so that the data strobe cycle when the operating frequency is lowered does not exceed the standard value of the mode before the operating frequency was lowered. We proposed a new system configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of digital signal reproduction.

FIG. 2 is a block diagram for performing data transfer without causing a device pause.

FIG. 3 is a timing chart of data transfer.

FIG. 4 is a block diagram for solving an increase in user burden and a decrease in data transfer rate.

FIG. 5 is a block diagram showing a configuration for solving an increase in user burden in a status check.

FIG. 6 is a block diagram illustrating a configuration of a temporary storage control unit that can respond to a specification change;

FIG. 7 is a block diagram showing a configuration for enabling the end of data transfer.

[Explanation of symbols]

101: storage medium to be reproduced; 102: pickup for reading data; 103: read channel; 104: reproduced data; 105: means for demodulating reproduced data;
06: Temporary storage means, 107: Error correction means, 1
08 data bus, 109 output means, 110 host interface, 111 temporary storage means control means, 1
12 microcomputer interface, 113 microcomputer controlling the whole, 114 host, 115 IDE bus, 2
01 ... Internal FIFO, 202 ... FIFO monitoring means, 20
3 internal FIFO remaining amount notification signal, 204 strobe switching means, 205 switching signal, 206 strobe generation means 1, 207 strobe generation means 2, 208
Selector, 209... Data strobe signal with the host,
401: a signal for notifying the remaining amount of FIFO, 402: transfer state determining means, 403: host, 404: an I / F signal output to the device, 405: host termination detection signal, 406: host I / F signal generating means, 407 ...
I / F signals output from the device to the host, 501 ...
CRC calculation means, 502: host, 503: transfer data, 504: CRC calculation result 1, 505: CRC calculation result 2, 506: CRC comparison error output means, 507: comparison error signal, 508: CRC error setting means 1, 509... CRC error setting means 2, 51
0: signal for clearing error information, 511: signal indicating that a CRC error has occurred during data transfer, 512: register for status check, 601: FIFO inside the host interface, 602: information indicating the state of the FIFO, 60
3 ... FIFO state monitoring means, 604 ... Signal indicating the remaining amount of FIFO, 605 ... Microcomputer, 606 ... Burst length output means,
607: data length to be transferred, 608: fixed burst length,
609: temporary storage means control means, 610: data request signal, 611: burst length, 701: host, 70
2: Host I / F signal generation means, 703: I to the host
/ F signal, 704... Data transfer end requesting means, 705.
Microcomputer, 706 ... data transfer end request command, 707 ...
Data transfer end request signal.

Continued on the front page (72) Inventor Eiji Ikeda 1410 Inada, Hitachinaka-shi, Ibaraki F-term in Digital Media Products Division, Hitachi, Ltd. (Reference) 5B001 AA04 AB01 AD06 5B065 BA03 CE05 CE23 EA01 EA21 5B083 AA05 BB01 BB03 CC03 CE01 DD10 EE11 GG04 5D044 BC03 CC04 DE68 HL01

Claims (12)

[Claims] A host device for generating a transfer control signal for the transfer data and calculating an error detection code for the transfer data; a storage unit for temporarily storing the transfer data; Monitoring means for monitoring the amount of data; calculating means for calculating an error detection code for the data transferred to the host device; error detecting means for detecting a mismatch from the calculation result of the calculating means and the calculation result from the host device Accumulating means for accumulating and displaying the mismatch from the detecting means, transfer terminating means for terminating data transfer based on a transfer control signal from the host device, and a transfer request for outputting a data transfer restart request signal to the host device. Each time the end of data transfer is determined based on a transfer control signal from the host device, if there is a mismatch in the error detection means, Through the request means, the data reproducing apparatus or the data reproducing storage apparatus characterized by stopping the data transfer to the host device. 2. The data reproducing apparatus or the data reproducing storage apparatus according to claim 1, wherein the transfer requesting means restarts the transfer based on information output from the monitoring means. 3. The data reproducing apparatus according to claim 1, wherein the transfer requesting means restarts the transfer based on information output from a data reproducing apparatus or a microcomputer controlling the entire data reproducing and storing apparatus. Or a data reproduction storage device. 4. The transfer request means according to claim 1, wherein whether or not a transfer request is made can be selected according to the setting of a control bit that can be set from outside the data reproduction device or the data reproduction storage device. A data reproduction device or a data reproduction storage device characterized by the above-mentioned. 5. A host device for inputting / outputting transfer data, a storage means 2 for storing data to be output to the host device and occupying a data bus during data transfer, and a plurality of words for transferring the transfer data to the storage means 2 collectively. Request means for making a request, the request means making a data request each time with a fixed-length word number, and when the remaining data transfer amount to be transferred to the host device becomes equal to or less than the fixed-length word number, A data reproducing device or a data reproducing and storing device, wherein the remaining data amount is a burst length and a request is made to the storage means 2. 6. A host device for generating a transfer control signal for transfer data, storage means 1 for temporarily storing transfer data, monitoring means for monitoring a transferable data amount in the storage means 1, Signal generation means for generating a data capture signal for the host device, wherein the signal generation means increases the minimum width of the signal period when the amount of transferable data output from the monitoring means falls below a predetermined value. A data reproducing device or a data reproducing storage device, wherein when the amount of transferable data output from the monitoring means exceeds a predetermined value, the cycle of the expanded signal is restored. 7. A communication protocol for data transfer with a host device includes a procedure for exchanging a control signal or data for starting data transfer, a procedure for exchanging a control signal or data for data transfer, and a procedure for terminating data transfer. In a data reproduction device or a data reproduction storage device, the data transfer procedure is terminated based on a transfer setting means that can be set from the outside and a transfer control signal from a host device. A transfer control means for setting a predetermined value in the transfer setting means, outputting a data transfer end request signal from the transfer end means, and controlling the data transfer to end the transfer according to the communication protocol of the interface. A data reproducing device or a data reproducing storage device, wherein the data reproducing device or the data reproducing storage device is terminated according to a procedure of the exchange. 8. The data reproducing apparatus or the data reproducing storage apparatus according to claim 7, wherein the first interface means is configured on one semiconductor device. 9. A host device for generating a transfer control signal for transfer data and a storage unit for temporarily storing the transfer data, wherein the storage unit is monitored, and when a transferable data amount falls below a predetermined value. The minimum width of the data capture signal to the host device is
A data reproduction control method or a data reproduction storage method, characterized in that when the amount of transferable data output from the monitoring means exceeds a predetermined value, the period of the expanded signal is returned to its original value. Control method. 10. A host device for inputting / outputting transfer data, and data to be output to the host device are stored, and a storage means 2 occupying a data bus during data transfer requests data transfer to the storage means 2. In this case, a data transfer request is made for multiple words at once, and the above request is made each time with a fixed-length word.If the remaining amount of data transferred to the host becomes less than the fixed-length word, A data reproduction control method or a data reproduction storage control method, characterized by outputting the remaining data amount as a burst length. 11. A communication protocol for data transfer with a host device includes a procedure for exchanging a control signal or data for starting data transfer, a procedure for exchanging a control signal or data for data transfer, and a procedure for terminating data transfer. The procedure of the exchange of control signals or data is specified.
In the data reproducing device or the data reproducing storage device, a predetermined value is set in the transfer setting means that can be set from the outside, a transfer end request is made, and the data transfer is performed by exchanging a control signal or data for terminating the transfer according to the communication protocol of the interface. A data reproduction control method or a data reproduction storage control method. 12. In a host device having a mode setting corresponding to a plurality of data transfer rates as a communication protocol and a data reproduction device or a data reproduction storage device according to the communication protocol, the operating frequency of the data reproduction device or the data reproduction storage device is reduced. If the data transfer rate of the mode at the time of operation does not match the data transfer rate of the same mode defined in the standard, select a mode that matches the data transfer rate of the mode at the time of lowering the operating frequency and operate it. Characteristic data reproduction control method or data reproduction storage control method.