JP2001235726A - Method for driving liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving method permitting to drive a liquid crystal while applying a reset voltage of a relatively large absolute value generating Frederiks transition. SOLUTION: As a 7-level driving method, two kinds of potentials (foe example, ±Vb) are set for applying an ON-selection voltage or an OFF-selection voltage to a liquid crystal as a data potential of a column electrode signal Yn; two kinds of potentials (for example, ±Vr) are set respectively for applying a positive or a negative reset voltage to the liquid crystal for a reset period T1 as a data potential of a row electrode signal Xm; two kinds of potentials (for example, ±2Vb) are set respectively for applying a positive or a negative selected voltage to the liquid crystal for a reset period T3 as a selected potential; and as a non-selected voltage, a middle potential (for example, 0V) between the two kinds of selected voltages is set for a delay period and a non-selected period. Thus, the liquid crystal can be driven by using the potentials at 7 levels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a liquid crystal display device using a chiral nematic liquid crystal having two metastable states. More specifically, the present invention relates to a driving method for improving the writing speed. Further, the present invention relates to a driving method capable of compensating for a driving voltage caused by variation in a threshold value of a liquid crystal unique to a liquid crystal panel, or compensating for a temperature of the driving voltage. Further, the present invention relates to a driving method capable of improving a voltage imbalance between two types of driving waveforms and forming an IC of a driving circuit.

[0002]

2. Description of the Related Art Driving a liquid crystal having bistability using a chiral nematic liquid crystal has already been disclosed in Japanese Patent Publication No. 1-51818. Also, a method of switching between the two metastable states and the like are described.

However, the driving method described in Japanese Patent Publication No. 1-51818 is not practical and has many problems.
For example, regarding the switching between two metastable states, the above publication discloses the following two methods.

One is to obtain two metastable states by the following driving method. That is, the voltage applied to the liquid crystal at 60 Hz and peak-to-peak 15 V is suddenly turned off by using a toggle switch, whereby 36
A 0 ° twist alignment state is obtained. Further, the voltage applied to the liquid crystal is slowly dropped for about one second using a variable voltage device, thereby obtaining a 0 ° uniform alignment state.

Another driving method is as follows.
When the high frequency of 1500 KHz is immediately applied to the liquid crystal after the low frequency electric field is turned off, a 360 ° twist alignment state is realized. When a high-frequency electric field of 1500 KHz is applied after a delay of about 1/4 second following the turn-off of the same low-frequency electric field, a uniform orientation state of 0 ° is obtained.

However, the former method is not practical at all and is merely a method for confirming a phenomenon in a laboratory. When we experimented with the latter method, it was found that if a high-frequency electric field is applied about 1/4 second after the low-frequency electric field is turned off, this will also be in a 360 ° twist orientation state and switch to two metastable states. could not.

[0007] Furthermore, Japanese Patent Publication No. 1-51818 has no description about a matrix display having the highest practicability and a high display capability at present, and does not disclose any driving method.

[0008] Therefore, we have previously filed Japanese Patent Application No. 4-2.
In 17932, a method for controlling the back flow generated in the liquid crystal cell and improving the above-mentioned disadvantage was proposed.
However, this proposal did not aim at shortening the writing time per one line of the matrix display. Therefore, in the embodiment of the above proposal, the writing time per one line of the matrix display is set to 400 μs,
For writing over 400 lines, a total of 160 ms (6.2
5 Hz) or more. This is not practical because it involves display flicker.

In general, variations in drive characteristics that occur in a manufacturing process of a liquid crystal display include a difference in drive characteristics depending on a location in one display and a difference in drive characteristics between respective displays due to a difference in a manufacturing lot. There is a difference. Therefore, in order to always use the entire liquid crystal display screen with the highest display quality, delicate drive voltage control according to the situation of each panel is required. In addition, even after the optimum adjustment is performed by some means, the driving condition causes a new fluctuation due to a change in the surrounding temperature, so that the adjustment according to the temperature change is further essential.

FIG. 49 shows the difference in the threshold value of the drive voltage within one panel. As described above, since the drive voltage changes with a slight difference in the alignment state or a change in the cell gap, it is necessary to optimally adjust the drive voltage in each panel in accordance with the worst point. FIG. 18 shows a change in drive voltage with respect to a change in temperature when matrix driving is assumed. The gradient to temperature is 0.
Although it is small at 02 v / ° C., the voltage fluctuation rate when the driving voltage at 25 ° C. is standard is 0.56% / ° C.
At 40 ° C., the variation width is as large as 19.6%. In actual use, it is desirable to compensate for this and obtain an optimal display.

In driving a liquid crystal having a memory property, it is necessary to apply a reset pulse having a relatively large absolute value to the liquid crystal in order to cause Freedericksz transition in the liquid crystal molecules. In this case, the voltage ratio between the scanning signal and the data signal during matrix driving is largely unbalanced. For this reason, this imbalance has the potential to be a major obstacle in forming a specific drive circuit and in making this circuit an IC.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal driving method capable of driving a liquid crystal while applying a reset voltage having a relatively large absolute value that causes Freedericksz transition to the liquid crystal.

Still another object of the present invention is to reduce the imbalance in voltage between a scanning signal and a data signal while applying a large reset voltage to a liquid crystal, to simplify the configuration of a driving circuit, and to realize an IC. Another object of the present invention is to provide a liquid crystal driving method that can cope with the above.

[0014]

According to the present invention, the following seven-level driving method can be used because a reset voltage having a relatively large absolute value is applied to the liquid crystal during the reset period T1.

As the seven-level driving method, for example, FIG.
(A) to FIG. 8 (D), the column electrode signal Yn
Are set as two kinds of potentials (for example, ± Vb) for applying an ON selection voltage or an OFF selection voltage to the liquid crystal. The data potential of the row electrode signal Xm is set in the reset period T1. Is a voltage for applying the positive or negative reset voltage to the liquid crystal, respectively.
Two kinds of potentials (for example, ± Vr) for applying the positive and negative selection voltages to the liquid crystal during the selection period T3 are set as the selection potentials.
2Vb) is set, and as the non-selection potential, an intermediate potential (for example, 0 V) between the two kinds of the selection potentials is set in the delay period and the non-selection period. Can drive liquid crystal.

The present invention more preferably employs a driving method including at least the following eight levels. That is, as the data potential of the column electrode signal, a positive and negative ON selection voltage and a positive and negative OFF
Four types of potentials for applying a selection voltage are set, and two types of potentials for applying the positive and negative reset voltages to the liquid crystal during the reset period as the reset potential of the row electrode signal, respectively. A potential is set, and two kinds of potentials for applying the positive and negative selection voltages to the liquid crystal are set in the selection period as the selection potential, and the delay period and the non-selection potential are set as the non-selection potential. In the non-selection period, two kinds of potentials for applying a bias potential to the four kinds of data potentials are set, and the liquid crystal is driven using at least eight levels of potentials.

The eight levels of potentials are transferred to the four levels (V1, V2, V3, V4: V1 <V2 <V3 <V) of the first group on the low voltage side.
4) and four levels of the second group on the high voltage side (V5, V6, V7,
V8: V4 <V5 <V6 <V7 <V8), and when the data potential of the column electrode signal is in the first group, the reset potential is selected from the second group. When the data potential of the column electrode signal is in the second group, the reset potential is selected from the first group, and in each of the periods other than the reset period, the data potential of the column electrode signal is the first group.
When in the group, each one potential is selected from the same first group, and when the data potential of the column electrode signal is in the second group, the potential is selected from the same second group. Preferably, one potential is selected for each.

With this arrangement, a large voltage difference does not occur between the voltage of the row electrode signal and the voltage of the column electrode signal.
A reset voltage having a relatively large absolute value exceeding 0 V and 1
A non-selection voltage near V can be applied to the liquid crystal.
This is preferable in configuring a drive circuit, particularly in implementing an IC.

Here, the potential V4 of the first group and the potential of the second
If the potential difference between the group and the group potential V5 is increased, the absolute value of the reset voltage applied to the liquid crystal during the reset period can be set large.

As shown in FIG. 32, in the k-th frame (k is an integer), the ON selection potential of the column electrode signal Xm is set to V5 of the second group, and the OFF selection potential is set to V7. The reset potential of the row electrode signal Yn is V1
Then, the selection potential is set to V8, and the non-selection potential is set to V6. In the (k + 1) th frame that follows, the ON selection potential of the column electrode signal Xm is set to V4 of the first group.
Then, the OFF selection potential is set to V2, the reset potential of the row electrode signal Yn is set to V8, the selection potential is set to V1, and the non-selection potential is set to V3. The liquid crystal can be AC driven.

As shown in FIG. 33, in the k-th frame (k is an integer), the ON selection potential of the column electrode signal Xm is set to V8 of the second group, and the OFF selection potential is set to V6. The reset potential of the row electrode signal Yn is V1
Then, the selection potential is set to V5 and the non-selection potential is set to V7. In the (k + 1) -th frame that follows, the ON selection potential of the column electrode signal Xm is set to V1 of the first group.
The OFF selection potential is set to V3, the reset potential of the row electrode signal Yn is set to V8, the selection potential is set to V4, and the non-selection potential is set to V2. The liquid crystal can be AC driven.

As shown in FIG. 34, the ON selection potential of the column electrode signal Xm in one frame period T is set to V4 and V5.
And the column pulse signal Xm is turned off.
The selection potential is set by an AC pulse of V2 and V7, and the reset potential of the row electrode signal Yn is set by an AC pulse of V8 and V1 in an order corresponding to this, and the selection potential is set to V
The non-selection potential is set by V3
And V6, and the voltage applied to the liquid crystal is inverted for each pulse to drive the liquid crystal in AC.

As shown in FIG. 35, the ON selection potential of the column electrode signal Xm within one frame period T is set by an AC pulse of V1 and V8, and the OFF selection potential of the column electrode signal Xm is set to V3 and V6. And the reset potential of the row electrode signal Yn is set to V8 in an order corresponding to this.
And V1 are set by an AC pulse, and the selection potential is set to V4 and V1.
5 and set the non-selection potential to V2 and V7.
, And the liquid crystal can be AC driven by inverting the polarity of the voltage applied to the liquid crystal for each pulse.

In the case of the driving method shown in FIGS. 32 and 34, V4−
By setting the relationship of V3 = V3-V2 = V7-V6 = V6-V5, substantially equal non-selection voltages can be set in the non-selection period T4.

In the case of the driving method shown in FIGS. 33 and 35, V3−
When the relationship of V2 = V2-V1 = V8-V7 = V7-V6 is set, substantially the same non-selection voltage can be applied to the liquid crystal in the non-selection period T4.

In the case of the driving method shown in FIGS. 34 and 35,
When the unit time corresponding to the selection period T3 is 1H, the pulse width of the signal FR for converting the row electrode signal and the column electrode signal into AC is 1H, and the phase of the signal FR is the same as that of the row electrode signal Yn. (1H / 2) for selection period
It can be shifted. The driving method in FIG. 36 is applied to the driving method in FIG. In this case, the row,
Although the number of inversions of the driving potential of the column electrode signal is halved as compared with FIG. 34, the number of inversions of the voltage waveform applied to the liquid crystal can be secured more.

Further, in the case of the driving method shown in FIGS. 34 and 35, the polarity of the voltage applied to the liquid crystal is inverted every unit time (1H) corresponding to the selection period T3, and the k-th frame (k is an integer) ) Is positive when the polarity is positive.
+1) the polarity at the beginning of the frame is negative, and
When the polarity at the beginning of the frame is negative, the (k +
1) Assuming that the polarity at the beginning of the frame is positive, the liquid crystal can be AC-driven by combining the polarity inversion every 1H and the polarity inversion every frame. The driving method in FIG. 37 is applied to the driving method in FIG.

When any of the driving methods shown in FIGS. 32 to 37 is adopted, each voltage of the first group and each voltage of the second group are set symmetrically in positive and negative directions with respect to the ground level. Then, it becomes suitable in circuit design.

In the above-described seven-level driving method and eight-level driving method, the delay period T2 is not necessarily included in one frame period T.
Is also applicable to the drive waveform shown in FIG. 3, that is, the drive waveform without the designation of the delay period T2.

[0030]

Next, an embodiment of the present invention will be described with reference to the drawings.

[Structure of Liquid Crystal Cell] The liquid crystal material used in each of the embodiments described below is a nematic liquid crystal (for example, ZLI-3329 manufactured by E. Merck) and an optically active agent (for example, E. Merck).
The helical pitch of the liquid crystal was adjusted to 3 to 4 μm by adding S-811). As shown in FIG. 1, a transparent electrode 4 pattern made of ITO was formed on upper and lower glass substrates 5 and 5, and a polyimide alignment film (for example, SP-740 manufactured by Toray Industries, Inc.) 2 was applied thereon. Then, a rubbing process was performed on each of the polyimide alignment films 2 in directions different from each other by a predetermined angle φ (φ = 180 ° in the embodiment) to form a cell. Spacers were inserted between the upper and lower glass substrates 5 to make the substrate spacing uniform, for example, the substrate spacing (cell spacing) was 2 μm or less.
Therefore, the ratio of the liquid crystal layer thickness / twisted pitch is 0.5 ±
0.2.

When liquid crystal is injected into this cell, liquid crystal molecules 1
Are several degrees, and the initial orientation is 1
An 80 ° twisted state results. This liquid crystal cell is sandwiched between two polarizing plates 7, 7 having different polarization directions shown in FIG.
An indicator was formed. 3 is an insulating layer, 6 is a flattening layer,
8 is a light-shielding layer between pixels, and 9 is a director vector of the liquid crystal molecules 1.

(First Embodiment) FIGS. 2A and 2
(B) shows two types of driving waveforms according to the first embodiment for driving the display shown in FIG. 1, respectively. The drive waveforms shown in each figure include a reset period T1, a delay period T2, a selection period T3, and a non-selection period T within one frame period T.
4 are included. FIG. 2A shows a drive waveform in which the polarity of the voltage charged in the liquid crystal cell is inverted for each frame period T to make an alternating current. FIG. 2B shows a driving waveform in which the polarity of the voltage charged in the liquid crystal is inverted for each pulse having a pulse width of (T3) / 2 to be converted into an alternating current. In each of the drawings, a reset voltage (reset pulse) 30 equal to or higher than a threshold value for causing Freedericksz transition in a nematic liquid crystal is applied during a reset period T1. In this embodiment, the reset voltage 30 has a peak value of ±
It is set to 30V. The reset period T2 is provided to delay the timing at which the selection voltage (selection pulse) 32 is applied to the liquid crystal cell in the selection period T3 after the reset voltage 30 is applied to the liquid crystal cell. In this embodiment, the delay voltage 31 is applied to the liquid crystal cell during the delay period T2.
For example, a voltage of 0 V is applied. The selection voltage 32 applied to the liquid crystal cell during the selection period T3 is a voltage selected based on a critical value that produces one of two metastable states of the nematic liquid crystal, for example, a 360 ° twist alignment state and a 0 ° uniform alignment state. It is. This selection voltage 32
In the case of the chiral nematic liquid crystal used in the first embodiment, if the peak value of the selection voltage 32 is 0 to ± 1 V,
A 360 ° twisted state is obtained. On the other hand, when a voltage of 2 V or more is applied to the liquid crystal cell as the selection voltage 32, 0
° Uniform orientation was obtained. In the non-selection period T4, a non-selection voltage 33 having an absolute value smaller than the selection voltage 32 is applied to the liquid crystal cell, and the state of the liquid crystal selected in the selection period T3 is maintained.

FIG. 3 shows a drive waveform as a comparative example. The drive waveform shown in FIG. 3 is based on the earlier application of the present applicant (U.S. Patent Application Nos. 08-059226 and 08-08
0993290). In the driving method of FIG. 3, the reset period T1,
2A and 2B in that a selection period T3 and a non-selection period T4 are provided, except that a delay period T2 is not provided. In other words, the driving method of the first embodiment shown in FIG. 2A and FIG. 2B is different from the driving method of FIG. Selection voltage 3
2 is greatly different from the driving method of FIG.

Table 2 summarizes the experimental results based on the driving method shown in FIG. 2A or 2B. Also,
Table 1 shows the results obtained by the driving method shown in FIG. 3 for comparison.
The display is a transmissive type with a backlight, and the on state corresponds to the 0 ° uniform orientation state in the light transmission state,
The off state is a light blocking state and corresponds to a 360 ° twist alignment state.

Here, in Tables 1 and 2, the duty ratio indicates (selection period T3) / (frame period T), the pulse width indicates the pulse width of the selection pulse, and the delay time indicates the length of delay period T2. Are respectively shown. Note that FIG.
In the case of the driving method of (A), the pulse width is T3, whereas in the case of the driving methods of FIGS. 2B and 3, the pulse width is (T3) / 2. In each of FIGS. 2A, 2B, and 3, the writing time per line matches the selection period T3. In each table, the on voltage indicates the value of the selection voltage 32 applied to the liquid crystal cell in order to bring the liquid crystal cell into the 0 ° uniform alignment state. The off voltage indicates the value of the selection voltage 32 applied to the liquid crystal cell in order to obtain a 360 ° twist alignment state.

[0037]

[Table 1]

[0038]

[Table 2]

As is clear from the comparison between Tables 1 and 2, when the selection voltage 32 is applied to the liquid crystal cell by inserting a certain delay time after the application of the reset voltage 30, switching of display is not possible in the driving method of FIG. Selection voltage 32 of possible pulse width
Is applied to the liquid crystal, the liquid crystal can be switched on / off. For example, the duty ratio in Table 1 = 1 /
240, pulse width = 50 μs, on / off voltage = 3 V
/ 0V, delay time = 0, display on / off
Switching is not possible. However, as shown in Table 2,
When the same selection voltage 32 is applied to the liquid crystal cell with a delay time of 50 μs or more, on / off switching becomes possible. In other words, this can reduce the writing time per line in a matrix type display from half the conventional method of 200 μs to one half.
This means that the time has been improved to 00 μs. When the on voltage is further increased from 3 V to 5 V with a delay time of 50 μs or more,
In response to a pulse having a pulse width of 25 μs, it was confirmed that writing per line could be reduced to 50 μs.

FIG. 4 shows the result of a dynamic simulation showing the behavior of the bistable liquid crystal used in the present invention, and the delay period T2.
And the relationship with the selection period T3. The horizontal axis represents time, the vertical axis represents the tilt of the molecule in the center of the liquid crystal cell, and the start point is when the reset pulse has expired.
According to this figure, after the liquid crystal molecules stand vertically (homeotropic alignment state), they slightly fall back (backflow), come back again, and the tilt advances toward 0 °. , And those that move in the 180 ° direction. The former is a transition to 0 ° uniform orientation state,
In the latter case, a twist is added in addition to the change of the tilt, so that the transition corresponds to a 360 ° twist orientation state. By the way, as is clear from this figure, the transition to the 0 ° uniform alignment state and the transition to the 360 ° twist alignment state immediately after the reset pulse 30 has expired, the same process called back flow of the liquid crystal. The behavior is exactly the same in passing through. That is, whether the alignment state of the liquid crystal becomes 0 ° or 360 ° depends on how to give a trigger (arrow in FIG. 4) after this backflow.

In the driving waveforms shown in FIG. 3 disclosed in the above-mentioned two earlier US patent applications, as shown in FIG. 4, the selection period T3 is set immediately after the reset period T1 has elapsed. Then, in the case of the driving method shown in FIG. 3, this selection period T3
Can be switched on / off as long as is extended to the timing at which a trigger should be applied after the backflow of the liquid crystal. In fact, according to Table 1, if the length of the selection period T3 is increased to 200 μs or 100 μs, the on / off of the liquid crystal can be switched. However, if the length of the selection period T3 is set to 50 μs, Cannot be switched on / off.

On the other hand, according to the driving method of FIGS. 2A and 2B relating to the driving method of the first embodiment, the delay period T2 is set between the reset period T1 and the selection period T3. By inserting and adjusting the time length of the delay period T2, regardless of the length of the selection period T3, the selection voltage 32 is applied to the liquid crystal at the timing when a trigger should be applied after the liquid crystal has caused a backflow. Can be applied. Therefore, as shown in Table 2, even if the time length of the selection period T3 is greatly reduced to 25 μs, the on / off state of the liquid crystal is changed.
Can be switched.

(Second Embodiment) A simple matrix type liquid crystal display shown in FIG. 5 was constructed using the liquid crystal cell shown in FIG. This liquid crystal display is of a transmission type in which a backlight 12 is arranged on the back of a liquid crystal cell 11. A scan drive circuit 13 is connected to the scan electrodes (row electrodes) of the liquid crystal cell 11, and the scan drive circuit 13 is controlled by a scan control circuit 15. On the other hand, a signal drive circuit 14 is connected to signal electrodes (column electrodes) of the liquid crystal cell 11, and the signal drive circuit 14 is controlled by a signal control circuit 16. A predetermined applied voltage is supplied from a potential setting circuit 17 to the scanning drive circuit 13 and the signal drive circuit 14. Further, a reference clock signal and a predetermined timing signal are supplied from the line sequential scanning circuit 18 to the scanning control circuit 15 and the signal control circuit 16. The temperature sensor 21 and the temperature compensation circuit 22 in FIG. 5 will be described later.

FIG. 6 is a diagram showing driving waveforms used for driving the simple matrix type liquid crystal display shown in FIG.
The difference from FIG. 2B is that the same bias voltage 34 as the non-selection voltage 33 is applied during the delay period T2 after the reset voltage 30. Voltage that would inevitably enter the In the driving waveform shown in FIG. 6, the length of the selection period T3 matches one horizontal scanning period (1H). The length of the delay period T2 is
T2 = (1H / 2) × n (n is an integer) in consideration of AC driving for each pulse having a pulse width of 1H / 2.

FIG. 7 is a graph showing a selection voltage range in which a 0 ° uniform orientation state and a 360 ° twist orientation state can be realized using the driving waveforms of FIG. The horizontal axis represents the delay time, and the vertical axis represents the pulse voltage applied to the liquid crystal. The reset voltage is 30 V, the duration is 1 ms, and the bias voltage is 1.3.
V, the pulse width of the selection pulse = 50 μs, that is, the writing time per line is 50 × 2 = 100 μs. The liquid crystal cell has the same configuration as that of the first embodiment, and has a cell gap d / pitch p = 0.6. From this figure, 3
The 60 ° twist orientation state (off in the display) can withstand the peak voltage of the selection voltage = 1.8 V, and the 0 ° uniform orientation state (on in the display) is 3.6 V or more with a minimum delay time of 200 μs. It was obtained that it could be switched. As a result, the drive waveform after reset is configured according to the 1/3 bias method, and the bias voltage and the o
The ff voltage is set to Vb = 1.3 V, respectively.
Assuming that the voltage is 3Vb = 3.9V, the writing speed 1
A simple matrix drive display of 200 to 240 rows can be obtained at 00 μs / line. When the driving waveform is configured according to the 1/3 bias method, the solid line in FIG.
The delay time may be selected in a range where the n voltage is lower than the on-selection voltage 3Vb indicated by the broken line in FIG.

FIGS. 8A to 8D show driving waveforms of each row, each column and each pixel of the matrix according to the 1/3 bias method. In the figure, Yn, Yn +
Reference numeral 1 denotes a scanning signal (row electrode signal) for driving each row electrode of the n-th row and the (n + 1) -th row. The scanning signals Yn and Yn + 1 are set to the reset potential of the peak value ± Vr in the reset period T1, and 0 in the delay period T2.
In the selection period T3, it is set to the selection potential of the peak value ± 2 Vb, and in the non-selection period T4, it is set to the non-selection potential of 0 V. Xm indicates the waveform of the data signal supplied to the m-th column electrode. The peak value of this data signal is ± Vb. When the phase of the data signal is opposite to the waveform of the scanning signal during the selection period T3, the liquid crystal cell is turned on. Drive. The difference signal Yn-Xm indicates a drive waveform applied to the liquid crystal of the pixel at the intersection of the n-th row electrode and the m-th column electrode. The difference signal Yn-Xm has a maximum peak value of ± (Vr + Vb) during the reset period T1 and a bias voltage 34 having a peak value of ± Vb during the delay period T2. In the selection period T3 shown in FIG. 8, the peak value is set to the selection voltage 32 for ON drive of ± 3 Vb, and in the non-selection period T4, the peak value is ± V.
The non-selection voltage 33 is set to b.

By combining the driving waveform of the second embodiment with a division matrix or multi-matrix method (Liquid Crystal Device Handbook-Nikkan Kogyo, p406), a 640 × 480 VGA-compatible display was realized.

As described above, in the first embodiment and the second embodiment, by applying the delay pulse after the reset pulse, high-speed writing as much as 50 μs / line, which is several times as large as that of the related art, can be performed. As a result, 640 × 400, 64
Matrix display with high needs such as 0 × 480 can be handled without the help of active elements. The liquid crystal display device to which the present invention is applied has a memory characteristic of several seconds as a basic characteristic, a contrast ratio of more than 100, a wide viewing angle of 60 ° above, 80 ° below, and 80 ° left and right. , And the optical response is as fast as 8 ms or less. For this reason, in addition to the fact that simple matrix driving is possible, a great contribution can be made to the realization of a low-cost and high-quality display device. In the above description, the transmission type is consistently described. However, if a characteristic having a contrast ratio of 100 or more is utilized, a reflection type display is also promising. Furthermore, if the optical response is less than 1 ms, the problem of flicker can be avoided, and a high-definition display with 1000 lines or more and a writing time of 0.1 s or less can be realized by utilizing the memory properties of the liquid crystal.

(Third Embodiment) FIGS. 9A and 9
(B) shows two types of drive waveforms according to the third embodiment used for driving the liquid crystal display shown in FIG. 1. FIG.
9 (A) and FIG. 9 (B) respectively show FIG. 2 (A),
As in FIG. 2B, an alternating drive method for inverting the polarity of the voltage charged in the liquid crystal cell for each frame or line is shown. 9 (A) or 9 (B) is different from the drive waveform according to the first embodiment of FIG. 2 (A) or FIG. 2 (B) in a period T3 following the delay period T2. Is the first selection period, an interval period T is provided between the first selection period T3 and the non-selection period T4.
5 and a second selection period T6. When the interval period T5 and the second selection period T6 are a pair of periods, in the driving waveforms of FIGS. 9A and 9B, the pair of periods is provided once. However, the present invention is not limited to this, and a pair of periods can be provided a plurality of times.

In FIG. 9A or 9B, the first and second selection periods T3 and T6 are set to the same length, respectively, and the selection voltage is applied to the liquid crystal cell in any of the periods T3 and T6. 32 is applied. In the interval period T5, the same bias voltage 34 as that in the delay period T2 is applied to the liquid crystal cell in consideration of matrix driving.

The result of applying the waveform of FIG. 9A or 9B is as follows. As a common condition,
The reset voltage was ± 25 V, the reset time was 1 ms, the delay time was 200 μs, and the bias voltage was ± 1.2 V.
At this time, when the on-selection voltage = ± 2.4 V, each pulse width is 1
When two pulses of 50 μs or three pulses each having a pulse width of 100 μs were applied, a 0 ° uniform orientation state was obtained. This was exactly the same as the result of applying one pulse with an on selection voltage of ± 2.4 V and a pulse width of 300 μs (the driving method in FIG. 2A or FIG. 2B). In addition, the interval between the two pulses (interval period T5) was extended up to 450 μs. Next, on selection voltage =
When the voltage was changed to ± 3.6 V, a 0 ° uniform orientation state was obtained with two pulses each having a pulse width of 50 μs. This too
ON selection voltage = ± 3.6 V and pulse width 100 μs 1
Pulse application (driving method of FIG. 2A or FIG. 2B)
Is equivalent to. In this case, the interval between the two pulses was extended up to 250 μs.

As described above, the present liquid crystal display has a very short cumulative pulse response effect, and is divided into a plurality of selection pulses having a short pulse width within a period of 1 ms to 2 ms after the reset pulse is turned off. What is necessary is just to apply. This will be described with reference to FIG. 4. The first and second selections are performed such that the last selection period T5 in one frame period T is set to the trigger timing after the backflow of the liquid crystal shown in FIG. The lengths of the periods T3 and T6, the length of the delay period T2, and the length of the interval period T5 may be adjusted. Then, within the period of 1 ms to 2 ms after the reset pulse off, it can be understood that the pulse can be divided into any number of pulses as long as the total pulse width does not change. When the effective voltage after the reset pulse is compared in each case where the peak voltage of the selection pulse applied to the liquid crystal is set to 2.4 V and 3.6 V during the period in which the cumulative pulse response effect occurs, 1.67V, and the latter is 1.88V. Therefore, it can be seen that the effective voltage can be made substantially constant when the number of selection pulses and the peak value of the pulse voltage are changed.

This is shown in FIGS. 10A to 10E.
This will be described with reference to FIG. In each of FIGS. 10A to 10E, the selection pulse (pulse width × peak voltage)
(The total area if there are a plurality of selection pulses) is the same. Therefore, as long as the above-described cumulative pulse response effect occurs, FIGS.
It can be seen that the effective voltage applied to the liquid crystal is constant in any case of driving 0 (E). Note that FIG.
Comparing the driving waveforms of FIGS. 10A to 10E in terms of the writing speed, the driving speeds in FIGS. 10A, 10D, and 10E are the same, but FIG. (B)
10C can achieve a writing speed twice as high as those described above, and a high duty can be achieved.

(Fourth Embodiment) FIGS. 11A to 11
(E) shows the driving waveform of the fourth embodiment in which the driving method of the third embodiment is applied to the pulse-reversal type AC driving of the matrix display shown in FIG. Yn, Yn + 1, Yn
+2 indicates a scanning signal supplied to the nth, (n + 1) th, and (n + 2) th row electrodes, respectively. In each scanning signal, a reset period T1, a delay period T2, a first selection period T3, an interval period T5, a second selection period T6, and a non-selection period T4 are provided within one frame period T. The lengths of the first and second selection periods T3 and T6 are the same, and each is one horizontal scanning period (1H). Also,
The length of the interval period T5 is 1H × m (m is an integer)
Is set to 2H in the case of FIG.

When the driving in this case is viewed from the matrix display of FIG. 12, rows C1, C2, C3, C1, C2, C3,
The selection of rows proceeds in a zigzag order, such as C4, C5, C6, C4, C5, C6. The data signal (Xm) on the column side transfers data at two times per line, and the voltage of the difference signal Yn-Xm of each signal on the row side and column side is applied to the liquid crystal.

We use this method to set two conditions of the reset voltage of the scanning signal = ± 25 V, the reset period = 1 ms, the delay period = 200 ± 100 μs, the selection voltage = ± 2.4 V, and the selection period = 50 μs. Under the condition that the data voltage of the data signal = ± 1.2 V, a simple matrix drive display with a duty ratio of 1/240 was realized. In this case, the frame frequency was 42 Hz, and no flicker occurred.
In addition, the above driving method is divided matrix or multi-matrix driving (Liquid Crystal Device Handbook-Nikkan Kogyo,
406 × 48
0 VGA compatible display.

As described above, according to the third and fourth embodiments, by applying the selection pulse after the reset pulse to the liquid crystal twice or more, it is possible to shorten the writing time of the simple matrix drive. In addition, a flickerless high-duty simple matrix drive is realized. At the same time, the drive voltage has been reduced, leading to lower power consumption.

Note that the cumulative pulse response effect when the selection pulse is applied to the liquid crystal a plurality of times is not necessarily the delay period T2 after the reset period T1 as in the third and fourth embodiments.
Is not limited to the setting. As shown in FIG. 13, a first selection period T3 is set immediately after the reset period T1 has elapsed, and a pair of an interval period T5 and a second selection period T6 is provided between the first selection period T3 and the non-selection period T4. May be repeated one or more times. In this case, the last selection period T within one frame period T
5 is set as the trigger timing after the back flow of the liquid crystal shown in FIG.
What is necessary is just to adjust the length of T6 and the length of the interval period T5.

(Fifth Embodiment) FIGS. 14A and 14
(B) shows two types of driving waveforms according to the fifth embodiment for driving the display shown in FIG. 1. FIG.
FIG. 14A shows a drive waveform for inverting the polarity of the voltage applied to the liquid crystal every frame, and FIG. 14B shows a drive waveform for inverting the polarity of the voltage applied to the liquid crystal every pulse. I have. The driving waveform in each figure is one frame T
Within the reset period T1, the delay period T2, and the selection period T3
And a non-selection period T4, which is the same as that of the first embodiment. However, the on-selection voltage or the off-selection voltage application period t for the selection period T3 (t = 2 × in the case of FIG. 14B). The difference is that the duty of (t / 2) is set to less than 100%.

FIG. 15 shows the result of applying the waveform of FIG. 14 (A) or FIG. 14 (B). The driving conditions were as follows: reset voltage = 20 V, reset time = 1 ms, delay time = 150 to 200 μs. In the figure, the horizontal axis represents the duty of the applied pulse width t with respect to the selection period T3.
The vertical axis indicates on (0 ° uniform orientation state) or off (360 ° twist orientation state) of the applied pulse.
Is the peak voltage at the time. As the pulse duty of the applied voltage is reduced to 50%, 33%, and 25%, the peak voltage increases to twice the route, three times the route, and two times the route. Therefore, the feature is that the effective values calculated within the selection period T3 are all equal. Also, the on voltage and o
Another feature is that the ratio of the ff voltage does not change even when the duty is changed. In the liquid crystal used for the measurement in FIG. 15, this ratio is about 5.

As described above, in driving the present liquid crystal display device, even if the duty of the total pulse width t of the selection pulse with respect to the selection period T3 is changed, the same display effect is obtained as long as the effective voltage within the selection period T3 does not change. It can be seen that it can be obtained. From this, it can be seen that the duty can be reduced to increase the peak voltage value of the selection pulse and facilitate the driving voltage accuracy of the circuit. It can also be seen that if the duty of the pulse is changed while the drive voltage is kept constant, the display effect that can change the effective value changes. That is, by changing the duty, it is possible to compensate for a slight difference in drive voltage due to the variation in the threshold value of the liquid crystal in the display panel as shown in FIG. In addition, since the threshold value of the liquid crystal varies depending on the temperature, by changing the duty,
Temperature compensation can be performed.

(Sixth Embodiment) FIGS. 16A to 16
(E) shows a drive waveform according to the sixth embodiment in which the drive waveform shown in FIG. 14 (B) is applied to AC drive of matrix display. In FIG. 16, Yn, Yn + 1, Yn
+2 indicates a scanning signal supplied to the nth, (n + 1) th, and (n + 2) th row electrodes, respectively. On-selection voltage or of for the selection period T3 of each scanning signal
The duty during the total application period t (= 2 × t / 2) of the f selection voltage is set to less than 100%. Xm indicates a data signal supplied to the m-th column electrode. The duty of the total period t of the data potential with respect to the selection period T3 of the data signal Xm is set to less than 100% similarly to the scanning signal. The difference signal Yn-Xm between the scanning signal and the data signal is applied to the liquid crystal. Also in this difference signal Yn-Xm, the duty of the application period t of the on selection voltage or the off selection voltage with respect to the selection period T3 is set to less than 100%. Therefore, both the selection voltage and the bias voltage are applied to the liquid crystal.
The voltage is applied as an intermittent pulse with a duty less than 100%.

We use this method to calculate the reset voltage =
± 25V, reset period = 1ms, delay period = 200μ
s, selection period = 100 μs, pulse selection time = 25 μs
× 2 (duty 50%), selection voltage = ± 4V, data voltage = ± 1V, 1/240 of duty ratio 1/240
Simple matrix drive display by the 5-bias method was realized. In this case, the frame frequency was 42 Hz, and no flicker occurred. In addition, by combining the above driving method with a divided matrix or multi-matrix driving (Liquid Crystal Device Handbook-Nikkan Kogyo, p406), a 640 × 480 VGA-compatible display can be obtained.

(Seventh Embodiment) FIGS. 17A to 17
(E) is another application example of the present invention to a matrix display. In FIG. 17, scanning signals Yn, Yn + 1, Yn +
2 have the same waveforms as the corresponding waveforms in FIG. On the other hand, the data signal Xm shown in FIG. 17 differs from the corresponding waveform in FIG. 16 in that the duty of the pulse width of the data potential for the selection period T3 is set to 100%. The voltage of the difference signal Yn-Xm is applied to the liquid crystal. The duty of the difference signal Yn-Xm in the on-selection voltage or the off-selection voltage application period t for the selection period T3 is set to less than 100%. Will be done. However, in the case of the seventh embodiment, a bias voltage is applied to the liquid crystal without interruption, and a selection voltage is applied thereto with a pulse duty of less than 100%.

Using this method, at an environmental temperature of 40 ° C., a reset voltage = ± 25 V, a reset period = 1 m
s, delay period = 200 μs, selection period = 100 μs, pulse selection time = 50 μs × 2 (duty 100%),
Under the conditions of the selection voltage = ± 4 V and the data voltage = ± 1 V, a simple matrix driving display by a 1/5 bias method with a duty ratio of 1/240 was realized. Also in this case, the frame frequency was 42 Hz, and no flicker occurred. next,
When the duty of the pulse width of the selection pulse for the selection period T3 is changed from 100% to about 74%, the effective voltage changes from 5V to 4.3V, and the temperature compensation from 40 to 5 ° C. in FIG. Was.

(Eighth Embodiment) FIGS. 19A to 19
(E) shows still another application example of the present invention to a matrix display. The scanning signals Yn, Yn + 1, Yn shown in FIG.
+2 indicates that the duty of the pulse width of the on-selection potential or the off-selection potential for the selection period T3 is 100%
It has become. On the other hand, in the data signal Xm, the duty of the pulse width t of the data potential for the selection period T3 is set to less than 100%. These difference signals Yn−
Xm is applied to the liquid crystal, and the difference signal Yn
Also at −Xm, the duty of the application period t of the on-selection voltage or the off-selection voltage for the selection period T3 is 10
Set to less than 0%. This method is on / o for liquid crystal
Since the ff voltage ratio is small, it is difficult to say that the effect is great.
The use of the 1/2 bias method is effective because the on waveform and the off waveform are the same as those in the third embodiment, and the bias voltage is intermittent.

(Ninth Embodiment) A circuit for varying the duty of the pulse width of the selection pulse for the selection period T3 and its operation will be described with reference to FIGS. FIG. 20 shows a clock signal CLK and a reset signal RE.
23 shows a circuit that outputs a scanning signal Yn having various potentials shown in FIG. 22 based on the selection signal S. As shown in FIG. 22, the scanning signal Yn is set to ± during the reset period T1.
Having a potential of V2, and as a selection pulse for the selection period T3, ±
It has a potential of V1 and has a potential of 0 V in other periods. Therefore, the scanning signal driving circuit shown in FIG.
As the scanning signal Yn, a first analog switch 70 that switches to a potential of -V1, a second analog switch 71 that switches to a potential of + V1, a third analog switch 72 that switches to a potential of + V2, and a potential of -V2 It has a fourth analog switch 73 for switching and a fifth analog switch 74 for switching to a potential of 0V. A monostable circuit 40, a 1/2 divider 46, and various logic gates 50 to 55, 60 to 64 are provided to switch and drive the analog switches 70 to 74.

The monostable circuit 40 receives the reference clock CLK, and generates a signal b which becomes high only for a time proportional to the time constant CR of the circuit. This monostable circuit 40 has a first
, A capacitor 42, a variable resistor 43, a resistor 44, and a second NOR circuit 45. The time constant of the monostable circuit 40 is determined by the capacitance value C of the capacitor 42 and the resistance value R of the variable resistor 43, and by changing the resistance value R of the variable resistor 43, the scanning signal will be described later. The duty of the pulse width of the selection pulse for the selection period T3 of Yn is variable.

The 1/2 divider 46 is connected to the reference clock CL
K is input to generate a signal a having a frequency half of the reference clock CLK, in other words, a signal a having a double cycle.

The first AND circuit 52 outputs the signals a and b
Are input by the first and second inverters 50 and 51 to generate a signal d shown in FIG. Further, the third AND circuit 54 receives the signal d and the selection signal S, and generates a signal e for switching the first analog switch 70. This signal e becomes high over the period corresponding to the pulse width of the selection pulse of the negative polarity in the selection period T3 of the scanning signal Yn shown in FIG.

The second AND circuit 53 comprises a signal a and a signal b
Is input by the second inverter 51 to generate a signal c shown in FIG. Further, the fourth AND circuit 55 receives the signal c and the selection signal S, and generates a signal f for switching and driving the second analog switch 71. This signal f is high only during a period corresponding to the pulse width of the positive selection pulse in the selection period T3 of the scanning signal Yn shown in FIG.

The first and second analog switches 70, 70
The signals e and f for driving the driving signal 71 determine the duty of the pulse width of the selection pulse for the selection period T3 of the scanning signal Yn. Further, the pulse width of each of the signals e and f is determined based on the signal b from the monostable circuit 40, and the time constant C of the monostable circuit 40 is determined.
It can be seen that by changing R, the duty of the pulse width of the selection pulse for the selection period T3 of the scanning signal Yn can be changed as a result.

The third to fifth analog switches 72 to 7 for switching potentials other than the selection pulse of the scanning signal Yn.
4 will be briefly described. The signal g for switching and driving the third analog switch 72 is generated by the fifth AND circuit 60 that receives the signal a and the reset signal RE. This signal g
Is high over a period corresponding to the period of the positive reset potential = + V2 in the reset period T1 of the scanning signal Yn shown in FIG.

A signal h for driving the fourth analog switch 74 is generated by a sixth AND circuit 61 which inputs a signal obtained by inverting the signal a by the first inverter 50 and a reset signal RE. This signal h is
In the reset period T1 of the scanning signal Yn shown in FIG.
It has become. The signal i for driving the fifth analog switch 74 is based on the signal b, the reset signal RE, and the selection signal S, based on the sixth AND circuit 61, the seventh AND circuit 62, the third NOR circuit 63, It is generated by the OR circuit 64. The signal i is high during the period in which the selection pulse is not output in the delay period T2, the non-selection period T4, and the selection period T3 of the scanning signal Yn shown in FIG.
It has become.

(Tenth Embodiment) The tenth embodiment changes the duty digitally and differs from the ninth embodiment in which the duty is continuously changed by changing the resistance value R. . FIG. 23 is a circuit diagram for outputting signals t1 and t2 for determining the pulse widths of the positive and negative selection pulses in the selection period T3 in the scanning signal Yn. FIG. 24 is a timing chart thereof.

In FIG. 23, as a circuit for generating the signals t1 and t2, a DIP switch 80, first and second magnitude comparators 81A and 81B, and first and second counters 82A and 82B are provided. .
The pulse width at which the signals t1 and t2 become high is set by, for example, a binary DIP switch 80. The DIP switch 80 is connected to, for example, first and second 4-bit magnitude comparators 81A and 81B. The first and second magnitude comparators 8
When the set value A set by the DIP switch 80 and the count number B of the first and second counters 82A and 82B match, the state of the terminal A = B is hi.
Change to gh. The first and second counters 82A and 82B are:
This counts the reference clock CLK shown in FIG. Signals CL1 and CL2 shown in FIG. 24 are input to the clear terminals CL of the first and second counters 82A and 82B. The signal CL1 is an output of the AND circuit 83 which receives the selection signal S and the signal a shown in FIG. On the other hand, the signal CVL2 is an output of the AND circuit 84 that inputs the selection signal S shown in FIG. 24 and a signal obtained by inverting the signal a by the inverter 83. Therefore, the first and second counters 82A and 82B are cleared when the signals CL1 and CL2 become high.

The signals t1 and t2 output from the A = B terminals of the comparators 81A and 81B become high over the period corresponding to the pulse width of the selection pulse in the selection period T3 of the scanning signal Yn shown in FIG. Therefore, the period in which the signals t1 and t2 are high is set to the DIP switch 8
By changing at 0, the duty of the pulse width of the selection pulse with respect to the selection period T3 of the scanning signal Yn can be changed stepwise by the reference clock CLK falling within the selection period T3. In the embodiment shown in FIG. 24, the set value A of the DIP switch 80 is 2, and a half (T3 / 2) of the selection period (T3 / 2) is the reference clock CLK.
The number is 8. Therefore, in the embodiment shown in FIG. 24, the duty of the pulse width of the selection pulse for the selection period T3 is 100 × (8−2) / 8 = 75%
It has become. As described above, in the tenth embodiment, the duty decreases as the set value of the DIP switch 80 increases, and conversely, the duty increases as the set value decreases.

(Eleventh Embodiment) The eleventh embodiment is different from the eleventh embodiment in that the on potential or the o potential during the selection period T3 of the data signal Xm is set.
The duty in the period of the ff potential is changed. FIG. 25 shows a data signal driving circuit 90 for outputting a data signal Xm to be supplied to the m-th column electrode, and FIG. 26 shows a timing chart thereof. The data signal driving circuit 90 outputs the potential −
A sixth analog switch 94 for outputting V3,
Seventh analog switch 95 for outputting potential V3
And an eighth analog switch 9 for outputting potential 0
6.

Further, each of the analog switches 94 to 9
6 are provided with logic gates 91 to 93 for switching driving. An eighth AND circuit 91 for switching and driving the seventh analog switch 95 is provided. The eighth AND circuit 91 outputs the data Dm in the m-th column.
And a signal obtained by inverting the signal b from the monostable circuit 40 shown in FIG. As shown in FIG. 26, the output signal j of the eighth AND circuit 91 becomes high over the period corresponding to the pulse width having the potential + V3 in the selection period T3 corresponding to one horizontal scanning period of the data signal Xm. I have. Also, the first
Ninth for switching and driving the analog switch 94 of FIG.
And an AND circuit 93 are provided. The ninth AND circuit 93 receives a signal obtained by inverting the data Dm by the third inverter 92 and an inverted signal of the signal b output from the second inverter 51, and generates a signal k. This signal k is high during the period corresponding to the pulse width having the potential -V3 in the selection period of the data signal Xm shown in FIG. The eighth analog switch 96 is switched and driven by a signal b from the monostable circuit 40 shown in FIG. As described above, the duty of the data potential with respect to the selection period of the data signal Xm depends on the time constant C of the monostable circuit 40 shown in FIG.
It can be changed based on R. As means for changing the duty of the data potential period with respect to the selection period of the data signal Xm, it is possible to digitally change the duty as in the tenth embodiment.

(Twelfth Embodiment) FIG. 27 is a block diagram of a matrix liquid crystal display device capable of changing the duty of the selection pulse width for the selection period T3. Display data required for display is temporarily stored in the memory 100, and transferred to the X driver 102 and the Y driver 103 via the display controller 101. Controller 101
Among them, there is a duty controller 107 that changes the pulse width duty of the X driver 102 or the Y driver 103 according to a signal from the temperature sensor 104 or the manual switch 106. The duty of the Y driver pulse is determined automatically or manually. The set value may be a continuous change as in the ninth and eleventh embodiments, or may be a step-like change as in the tenth embodiment.
As a result, the pulse train applied to the liquid crystal panel 108 is
It has a waveform that is compatible with the ambient temperature and that is easy to see.

As described above, in this embodiment, if the duty controller 107 is added to the display controller 101, the pulse duty applied to the liquid crystal can be changed continuously or stepwise within the selection period T3. The applied effective pulse voltage can be changed. As a result, it has become possible not only to absorb the variation in the driving voltage of each liquid crystal panel, but also to adjust the variation in the driving voltage due to the environmental temperature change without changing the power supply voltage. Also, if the user of the liquid crystal display body can also make an adjustment directly by using an external operation switch, it is possible to adjust the display to an optimum state for himself. Further, when the difference between the reset voltage and the data voltage is large in realizing a circuit and it is difficult to obtain the power supply voltage accuracy, the problem can be solved by reducing the pulse duty and increasing the peak value. Further, in the case of color display, even if the cell gap is different due to the difference in filter thickness in RGB and the threshold value is different, the pulse duty may be adjusted in accordance with the driving voltage of each of RGB.

Here, at least one of the scanning signals (row electrode signals) respectively supplied to the plurality of row electrodes is set to a value in which the duty of the selection potential with respect to the selection period is different from that of the other row electrodes. Can be. For example, by changing the above-described duty between the upper row electrode and the lower row electrode of the liquid crystal panel, it is possible to compensate for variations in threshold values different between the upper and lower sides of the liquid crystal panel. Also,
At least one of the data signals (column electrode signals) respectively supplied to the plurality of column electrodes may be set to have a different value of the duty of the data potential period with respect to the selected period from the other column electrode signals. For example, by changing the duty in the left and right columns of the liquid crystal screen, it is possible to compensate for variations in threshold values that differ between the left and right sides of the liquid crystal panel. Alternatively, when attention is paid to a column electrode signal supplied to one column electrode, a selection period corresponding to one pixel on a column electrode to which the column electrode signal is supplied and a selection period corresponding to another pixel are: The duty of the data potential period for each selection period can be set to a different value. By doing this, for each pixel on one line of the LCD screen,
Variations in different threshold values can be compensated for on the upper side and on the lower side.

The driving method for changing the duty can be similarly applied to the driving method of FIG. 3 or FIG. 13 in which no delay period is provided.

[Regarding Other Parameters Changed in Response to Changes in Threshold Value of Liquid Crystal] The ninth to twelfth embodiments relate to variations in the threshold value of the liquid crystal itself constituting the liquid crystal panel or the threshold value of the liquid crystal due to the environmental temperature. Is compensated by changing the duty of the selection pulse period with respect to the selection period, but the change of the threshold value of the liquid crystal can also be dealt with by changing the following parameters. First, the pulse height of the selection pulse can be changed according to the threshold value of the liquid crystal. Further, as parameters for changing the threshold value of the liquid crystal, the pulse width of the selection pulse and the time length of the delay period T2 for setting the timing of applying the selection pulse can be cited.

For example, when the pulse width, delay time, and temperature of the selection pulse are fixed, the critical values are Vth1 and Vth2 shown in FIG. 28 as the pulse height of the selection pulse. FIG.
Absolute value (vertical axis) of reset pulse voltage value Ve shown in FIG.
A1, a2 are in one of the metastable states (for example, when the torsion angle is 0)
(Ve |> V0 and |)
Vth1 | <| Vs | <| Vth2 |). Also,
b1, b2, and b3 are regions (| Ve |> V0 and | Vs | <| Vth1 | or | Ve |> V0 and | Vs |>) where the other metastable state (for example, a state with a twist angle of 360 degrees) appears. | Vth2 |). Where Vth1 and Vth
2 is a threshold value for the voltage value of the selection pulse, and there may be three or more threshold values in practice. In the present embodiment, the liquid crystal drive is performed using the above Vth1 as a threshold.

The critical value is given by the set of the above three parameters because the negative correlation between the thresholds Vth and Vsat and the temperature T shown in FIG. 29 and the negative correlation between the thresholds Vth and Vsat and the pulse width Pw shown in FIG. And the threshold Vt shown in FIG.
It is shown by the correlation between h, Vsat and the delay time τ. The on / off driving conditions of the liquid crystal aimed at in the following embodiments are as follows: Von = Vw + Vd ≧ Vsat, and Voff = Vw−
Vd ≦ Vth. In the following thirteenth to fifteenth embodiments, any one of the above parameters is changed to perform temperature compensation, and the temperature sensor 21 and the temperature compensation circuit 22 shown in FIG.
Is used to perform temperature compensation.

The temperature sensor 21 measures the environmental temperature of the liquid crystal cell 11 and sends a measurement signal to the temperature compensation circuit 22.
The temperature compensating circuit 22 outputs the compensation control signal x or y to the potential setting circuit 17 or the line sequential scanning circuit 18 according to a plurality of temperature compensating methods to be described later to correct the output potential of the potential setting circuit 17, or The control frequency or control pattern of the progressive scanning circuit is changed. Note that the normal temperature range is divided into a plurality of temperature ranges, different set values of the parameters are set in advance for each temperature range, and the set values of the parameters determined for the temperature range to which the environmental temperature belongs are selected. Thus, temperature compensation can be performed.

As the driving waveform for driving the simple matrix type liquid crystal display shown in FIG. 5, either the waveform shown in FIG. 2A or the waveform shown in FIG. 2B can be used. In addition, when the delay time is not changed as a parameter, a drive waveform shown in FIG. 3 in which a selection pulse is applied immediately after the reset period T1 has elapsed can be used.

(Thirteenth Embodiment) In the thirteenth embodiment, by changing the pulse height of the selection pulse, appropriate liquid crystal driving is performed according to the threshold value of the liquid crystal. In the thirteenth embodiment, the duty ratio of the selection period T3 to one frame period T is set to 1/240, and the pulse width (the selection period T
2) = 40 μs, delay period T2 = 200 μs, and signal potential Vd = ± 1.2 V. On state (corresponding to a uniform orientation state with a twist angle of 0 °) and off state (corresponding to a 360 ° twist angle with a twist orientation state)
When the changes in the threshold values Vth and Vsat with respect to the temperature in the case of obtaining the values in the range from 0 ° C. to 50 ° C. in the normal temperature range, the changes in the threshold values are as shown in Table 3 and FIG. If the modulation state of the scanning potential Vw in the selection period is set as shown in Table 3 and FIG. 29 so as to satisfy the above-described liquid crystal on / off driving conditions, stable driving can be performed in the normal temperature range.

[0090]

[Table 3]

Here, the scanning potential Vw is modulated by setting the potential of the potential setting circuit 17 based on the output signal of the temperature compensating circuit 22.
That is, the drive voltage was modulated. As is clear from Table 3 and FIG. 29, when the threshold value of the liquid crystal is high, the absolute value of the selection voltage is set to be large, and when the threshold value of the liquid crystal is low, the absolute value of the selection voltage is set to be small. .

(Fourteenth Embodiment) In the fourteenth embodiment, the control frequency of the line-sequential scanning circuit 18, that is, the drive frequency of the liquid crystal display is modulated stepwise by the output signal of the temperature compensation circuit 22 to perform temperature compensation. Was. Here, the duty ratio of the selection period T3 to one frame period T is set to 1/240, the signal potential Vd = ± 1.2v, and the scanning signal potential Vw = ± 4.2v in the selection period. In the modulation method, in consideration of the negative correlation between the pulse width Pw and the threshold values Vth and Vsat shown in FIG. 30, the pulse width in the temperature range of 15 to 35 ° C. was set to Pw = 40 μs, and the delay time was set to τ = 200 μs. On the other hand, in the low temperature range of 0 to 15 ° C., the frequency was set to 1/2 and the pulse width Pw = 80 μs. At this time, the changes of the threshold values Vth and Vsat with respect to the temperature are as shown in Table 4, and the driving conditions were satisfied in the entire temperature range. In this case, the delay time is also 50 to 400 μs due to frequency modulation.
However, it is also possible to satisfy the driving conditions by modulating only the pulse width.

[0093]

[Table 4]

As is apparent from Table 4 and FIG.
When the threshold value of the liquid crystal is high, the drive frequency is lowered to lengthen the selection period T3. When the threshold value of the liquid crystal is low, the drive frequency is lowered and the selection period T3 is set short.

(Fifteenth Embodiment) In the fifteenth embodiment, the control pattern of the line-sequential scanning circuit 18 is changed stepwise by the output signal of the temperature compensating circuit 22, and the length of the delay period T2 is modulated to perform temperature compensation. Was done. Here, one frame period T
, The duty ratio of the selection period T3 is 1/240,
Signal potential Vd = ± 1.2 V, scanning signal potential Vw = ± 4.2 V during selection period T3, pulse width P of selection pulse
w is set to 40 μs. In the modulation method, in the correlation between the delay time τ and the threshold values Vth and Vsat shown in FIG. 31, a negative correlation part having a short delay time τ is used, and the delay time in the temperature range of 15 to 35 ° C. is τ = 40 μs × 5
= 200 μs. On the other hand, in the low temperature range of 0 to 15 ° C., the delay period is doubled and the delay time τ = 40 μs × 10 =
400 μs, the delay period is 2/5 in the high temperature range of 35-50 ° C.
And the delay time τ = 40 μs × 2 = 80 μs. At this time, the changes of the threshold values Vth and Vsat with respect to the temperature are as shown in Table 5, and the driving conditions were satisfied in the entire temperature range.

[0096]

[Table 5]

As is clear from Table 5 and FIG. 31, when the threshold value of the liquid crystal is high, the delay period T2 may be set long, and when the threshold value of the liquid crystal is low, the delay period T2 may be set short.

An experiment was conducted as to whether or not on / off driving was possible when driving was performed by changing the duty ratio, pulse width and delay time using the same liquid crystal display as in the above embodiment. The results are shown in Table 6 below. When the pulse width is shortened to shorten the writing time, the threshold value rises and the on / off drive becomes impossible. However, it can be seen that the on / off drive becomes possible even with a short pulse width by introducing the delay time.

[0099]

[Table 6]

In Table 6 above, TP indicates the type of drive waveform, type 1 is the drive waveform shown in FIG. 3, type 2 and type 4 are the drive waveforms shown in FIG. 2 (A), and type 3 and type 5 are the types shown in FIG. Each was driven by the drive waveform shown in FIG.

The modulation of the delay time τ corresponding to the delay period T2 makes it possible to shorten the pulse width Pw while suppressing the rise of the on-voltage, and the writing time can be shortened.
The number of scanning lines can be increased. This means
Chiral nematic liquid crystal, which has the characteristics of metastable state memory (around 1 second), high contrast ratio (100 or more), wide viewing angle (60-80 degrees), and high-speed response (8 ms or less), exceeds STN liquid crystal. 64 pixels with high needs
It is very effective in that it can be applied to a matrix display such as 0 × 400, 640 × 480, etc. without the aid of an active element.

The data in Table 6 directly shows that the pulse width of the selection pulse and the delay time have a strong correlation with the critical value of the two states of ON and OFF. Also,
It is understood that the ON / OFF threshold value fluctuates even when only the pulse width of the selection pulse is changed.

In the thirteenth to fifteenth embodiments, a critical value serving as a reference when selecting two metastable states is grasped by three parameters of a voltage value indicating a state of application of a selected pulse, a pulse width, and a delay time. Was modulated so as to compensate for the fluctuation of the critical value due to the temperature change, and a stable liquid crystal display could be realized. In particular, it has been clarified that the temperature compensation in the normal temperature range can be performed by controlling only one of the above three parameters, so that the significance in that a large degree of freedom in driving conditions is secured is significant.

In actual temperature compensation, stable driving of the display body can be performed with a simple circuit configuration by modulating the driving voltage or the driving frequency. In particular, when a temperature sensor is provided in a circuit to automatically compensate for temperature, it is possible to modulate the voltage and frequency in an analog manner according to the detection signal of the temperature sensor, but the circuit configuration may be complicated. is there. Therefore, temperature compensation can be easily performed by digitally selecting and switching the drive voltage by the selection circuit or by digitally switching the drive clock by the switching circuit.

Note that this type of temperature compensation is not necessarily automatically performed based on the output of the temperature sensor, but may be performed manually using a manual switch. Further, the temperature compensation is not limited to the one that performs the temperature compensation by changing the above parameters,
Variations in the threshold value of the liquid crystal in the liquid crystal panel as shown in FIG. 49 may be compensated.

[Regarding Voltage Levels of Scanning Signal and Data Signal] FIG. 8 shows driving waveforms using seven levels as voltage levels of the scanning signal and the data signal. That is, the data signal Xm has two voltage levels of ± Vb, and the scanning signal Yn has a total of five levels of ± Vr, ± 2Vb and 0 level. Here, the scanning signal Y
n during the reset period T1 is 20V
Is required. On the other hand, the data signal Y
As the voltage level Vb of n, around 1 V is sufficient. Therefore, in the case of the driving waveform shown in FIG.
A large potential difference occurs between n and the data signal Xm. Further, even in the same waveform of the scanning signal Yn, the voltage Vr
And a voltage of 2 Vb, a voltage difference of about 20 V is generated.

As described above, in the display driving method using the liquid crystal having two metastable states, the ratio between the voltage of the scanning signal and the voltage of the data signal at the time of matrix driving is largely unbalanced. This is a major obstacle in configuring the circuit. In particular, the above-mentioned imbalance has become a serious problem in implementing this drive circuit as an IC.

As a conventional voltage averaging driving method for a matrix-type liquid crystal display device, a six-level driving method has been proposed (see Liquid Crystal Device Handbook / Nikkan Kogyo Co., p. 401). This six-level driving method is effective in balancing the driving voltages of the scanning signal waveform and the data signal waveform, and increasing the ratio between the on-voltage and the bias voltage. However, since a relatively large reset voltage is required to drive the liquid crystal targeted by the present invention, this problem cannot be solved by the six-level driving method. Here, in the following various embodiments, a method of driving the liquid crystal at a drive level of at least eight levels will be described. In each of the following embodiments, an example is described in which a delay period T2 is provided between the reset period T1 of the scanning signal and the selection period T3. However, a driving method without the delay period T2, that is, FIG. The eight-level driving method can be applied to the driving method shown in FIG.

(Sixteenth Embodiment) FIG. 32 shows a drive waveform according to a sixteenth embodiment. Scan signals Yn, Yn + 1
Indicates scanning signals supplied to the n-th and n + 1-th row electrodes, respectively. As the eight levels of potentials set in the scanning signal and the data signal, the first group of four levels (V1, V2, V3, V4, where V1 <V2)
<V3 <V4) and the four levels (V
5, V6, V7, V8, where V4 <V5 <V6 <V7
<V8). In FIG. 32, the data signal Yn of the k-th frame (k is an integer) is the reset period T
1, the voltage V1 during the delay period T2, the voltage V6 during the selection period T3, and the voltage V8 during the selection period T3.
Is set to the voltage V6. The subsequent (k + 1) th frame is symmetrical to the kth frame with respect to the intermediate voltage between V4 and V5. That is, the scanning signal Yn of the (k + 1) th frame is reset during the reset period T
1, the voltage V8 during the delay period T2, the voltage V3 during the selection period T3, and the voltage V1 during the selection period T3.
Are set to V3. Further, although not shown, the subsequent (k + 2) th frame has the same waveform as the kth frame, and the waveform is repeated in this relationship.

The scanning signal Yn + 1 is the waveform of the scanning signal in the next row. The difference from the scanning signal Yn is that the reset period T
1. The difference is that each of the delay period T2 and the selection period T3 is shifted by one line time (1H). Also,
The beginning and end of the first frame are the same as the scanning signal Yn, and thereafter, similarly, the waveforms of the scanning signals before and after are shifted by 1H.

In the data signal Xm, the on
The voltage is set to V4 or V5, and the off voltage on the display is set to V2 or V7. In the k-th frame, the potential is turned on at V5 on the high potential side, turned off at V7, and has the largest potential difference from the reset voltage V1.
That is, the waveforms of the scanning signal and the data signal are 180
° The relationship is shifted. In the (k + 1) -th frame, in order to invert the polarity of the voltage applied to the liquid crystal, V4 on the lower potential side is turned on, V2 is turned off, and a maximum potential difference is generated between the reset voltage V8 at this time. .

The pixel PXL (mn) driven by the difference signal Yn-Xm between the scanning signal Yn and the data Xm has a large reset voltage (V1-V7) or (V8
−V2) is applied, and the same on voltage, off voltage, and bias voltage as in the voltage averaging method shown in FIG. 8 are obtained. That is, V4-V3 = V3-V2 = V7-V
If 6 = V6−V5, it is possible to set so that the bias voltages in the non-selection period T4 are equally applied. Here, when it is desired to increase the on-voltage, the voltage difference between V1 and V2 and between V7 and V8 may be increased.

When it is desired to increase the reset voltage, the potential difference between V4 and V5 may be further increased. Further, in order to add the length of the delay time after the application of the reset voltage to this, the timing of the selection period may be shifted by 1H.

By the way, as a first example, V1 = 0V, V
1st group of 2 = 1V, V3 = 2V, V4 = 3V, and V5 =
Each voltage was set to the second group of 23V, V6 = 24V, V7 = 25V, and V8 = 26V. As a second example, V1 =
-13V, V2 = -12V, V3 = -11V, V4 =-
A first group of negative voltages of 10V, V5 = 10V, V6
= 11V, V7 = 12V, V8 = 13V The respective voltages were set to a second group of positive voltages. In both the first and second examples, a reset voltage = ± 25 V, an on voltage = ± 3 V, an off voltage = ± 1 V, and a bias voltage = ± 1 V are obtained. In particular, in the voltage setting of the second example, a large voltage exceeding 20 V and a small bias voltage near 1 V can be simultaneously realized while the voltage values approach each other with the 0 potential as the axis of symmetry.
This is suitable for converting into C. That is, ±
A circuit can be designed in consideration of the symmetry of 10, ± 11, ± 12, ± 13V. Further, if it is desired to further increase the reset voltage of the present embodiment, it is preferable to increase the reset voltage in the positive and negative directions so as to further increase the potential difference between the first group voltage V4 and the second group voltage V5. , 30
V, a reset voltage of 40 V and a bias voltage of 1 V can also be realized.

(Seventeenth Embodiment) FIG. 33 shows a drive waveform in which the polarity of the voltage applied to the pixel is inverted for each frame, as in the sixteenth embodiment. Voltage V shown in FIG.
The relationship of 1 to V8 is the same as that of the sixteenth embodiment. In FIG. 33, the scanning signal Yn has a reset period T
1 is voltage V1 (frame k) or voltage V8 (frame k + 1), and delay time T2 is voltage V7 (frame k) or voltage V2 (frame k + 1),
The voltage is V5 (frame k) or V4 (frame k + 1) in the selection period T3, and is V in the non-selection period T4.
7 (frame k) or voltage V2 (frame k + 1)
It has become. This scanning signal Yn repeats inversion for each frame with the midpoint between the voltages V4 and V5 as the axis of symmetry. The on-voltage of the data signal Xm is V in the frame k.
8, the off voltage is V6, and in frame k + 1 it is on
The voltage is V1 and the off voltage is V3. When the voltages V1 to V8 are set to be the same as those in the first or second example of the sixteenth embodiment, the reset voltage becomes ± 26 V, and the voltage amplitude can be made wider by ± 1 V than in the sixteenth embodiment. This has the effect. The on voltage, the off voltage and the bias voltage are the same as in the sixteenth embodiment, and do not change. In order to achieve compatibility with the voltage averaging method shown in FIG. 8, V2-V1 = V3-V2 = V7-V6 = V
8-V7 may be set.

(Eighteenth Embodiment) FIG. 34 shows a drive waveform in which the polarity of the voltage applied to the liquid crystal is inverted for each pulse. In FIG. 34, the scanning signal Yn changes the two potentials of the voltages V1 and V8 to 1H / V during the reset period T1.
2 (1H is the length of the selection period T3). Further, this scanning signal Yn has a delay period T2
, Two kinds of potentials of the voltages V3 and V6 are set to 1H / 2
Are set alternately and repeatedly. However, the delay period T
After 2 the pulse phase is compared with the reset pulse and 1
It is changed by 80 °. The scanning signal Yn is output during the selection period T3.
In this example, two kinds of potentials V1 and V8 are set alternately and repeatedly every 1H / 2. Further, in the non-selection period T4, two kinds of potentials of the voltages V3 and V6 are alternately set every 1H / 2. On the other hand, in the data signal Xm, two kinds of potentials V4 and V5 are alternately and repeatedly set every 1H / 2 as an on voltage, and an off voltage is alternately repeated every 1H / 2 of two kinds of potentials V2 and V7. Is set.

As shown in FIG. 34, the polarity of the reset voltage, the selection voltage, and the non-selection voltage of the difference signal Yn-Xm between the scanning signal Yn and the data signal Xm is inverted every 1H / 2. Will be. As a result, the polarity of the voltage applied to the liquid crystal can be inverted for each line. Also in the eighteenth embodiment, the same on-voltage, off-voltage and bias voltage as in the voltage averaging method shown in FIG. 8 are obtained. That is, V4-V3 = V3-V2 = V7-
Assuming that V6 = V6-V5, the bias voltage can be set to be equally applied in the non-selection period T4.

(Nineteenth Embodiment) As in the eighteenth embodiment, the driving waveform of the nineteenth embodiment shown in FIG. 35 is such that the polarity of the voltage applied to the liquid crystal is inverted for each pulse.
The scanning signal Yn shown in FIG. 35 is the same as the scanning signal Y shown in FIG.
The difference from n is the set potential of the delay period T2, the selection period T3, and the non-selection period T4. In the scanning signal Yn shown in FIG. 35, in the delay period T2 and the non-selection period T4, two kinds of potentials of the voltages V2 and V7 are alternately set every 1H / 2. The scanning signal Yn
In the selection period T3, two kinds of potentials of the voltages V4 and V5 are alternately set every 1H / 2.

On the other hand, the data signal Xm is completely different from the eighteenth embodiment, and has two kinds of potentials V1 and V8 as its on-voltage and two kinds of potentials V3 and V6 as its off-voltage. In the difference signal Yn-Xm between the scanning signal Yn and the data signal Xm, a voltage having the same absolute value as that of the difference signal shown in the eighteenth embodiment is applied to the liquid crystal in the delay period T2, the selection period T3, and the non-selection period T4. Will be. On the other hand, in the reset period T1 of the difference signal Yn-Xm of the nineteenth embodiment, the maximum amplitude is V1-V8 or V8-V1, and the amplitude of the reset voltage is set to the first as in the seventeenth embodiment.
This can be larger than that of the eighth embodiment.
It is superior to the driving method of the embodiment. It should be noted that in order to achieve compatibility with the voltage averaging method shown in FIG.
V2 = V7−V6 = V8−V7 may be set.

(Twentieth Embodiment) The twentieth embodiment is a method in which the number of inversions in one frame is reduced to about half as compared with the eighteenth embodiment, and the driving frequency of the pulse is suppressed.
As shown in FIG. 36, the signal FR that determines the timing of pulse inversion of the scanning signal and the data signal is a signal that repeats on and off every 1H.
The phase is shifted by 1H / 2 from the rise of the selection period T3. With this arrangement, the waveforms of the scanning signal Yn and the data signal Xm are repeatedly pulse-inverted in synchronization with the signal FR. Therefore, the number of pulse inversions in one frame is halved compared to the waveform in FIG. I have. However, in the waveforms of these difference signals Yn-Xm, the pulses are inverted every 1H / 2, so that a long liquid crystal life can be ensured as in the eighteenth embodiment. According to the twentieth embodiment, since the driving frequency of each driver for the scanning signal and the data signal is halved, the shaping of the waveform is facilitated and the power consumption is reduced. Furthermore, it is particularly advantageous in the case of a circuit in which the power supply voltage itself is swung to the plus side and the minus side for AC conversion. In the twentieth embodiment, each period T of the scanning signal and the data signal is different.
The voltage settings at 1 to T4 are the same as in the eighteenth embodiment, but may be the same as in the nineteenth embodiment.

(Twenty-first Embodiment) FIG. 37 shows a driving method for performing pulse inversion every 1H. As shown in the figure, the signal FR is similar to the twentieth embodiment shown in FIG. 36 in that the signal FR is repeatedly turned on and off every 1H.
R differs from the twentieth embodiment in that it synchronizes with the selection period T2. The scanning signal Yn shown in FIG.
In 3, the voltage V1 is set in the frame k, the voltage V8 is set in the frame (k + 1), and changes to V1 and V8 for each frame. In the waveform of the data signal Xm, when the voltage of the scanning signal Yn during the selection period T3 is V1, the voltage V4 is turned on and the voltage V2 is turned off. When the voltage of the data signal Xm in the selection period T3 of the scanning signal Yn is V8, the voltage V5 is turned on and the voltage V7 is turned off. Focusing on the frame k, the difference signal Yn-Xm between the scanning signal and the data signal has a large number of times that a negative voltage is applied to the liquid crystal. I can't take it. However, the following (k +
1) In the frame, on the contrary, the number of times that the positive voltage is applied to the liquid crystal increases, and the polarity of the voltage applied to the liquid crystal can be balanced in these two consecutive frames. In this sense, the twenty-first embodiment can be said to be a combination of the frame inversion shown in the sixteenth and seventeenth embodiments and the pulse inversion shown in the eighteenth and nineteenth embodiments.

The advantages of the twenty-first embodiment are that the selection period T3 (1H) can be extended even in the case of high duty, and the DC component to the liquid crystal can be reduced compared to the case of only frame inversion. The voltage application time can be set short. The voltages in the respective periods T1 to T4 of the scanning signal and the data signal of the twenty-first embodiment were set to be the same as those of the seventeenth embodiment, but instead were set to be the same as those of the eighteenth embodiment. You can also.

(Twenty-second Embodiment) FIG.
FIG. 4 is a block diagram illustrating a driving circuit of a difference signal electrode (row electrode) for implementing the driving method according to the embodiment. In the following description, a circuit for generating a drive waveform according to the twenty-first embodiment will be described. In FIG. 38, the logic circuit 110 includes:
Based on the information of the delay period T2, a reset signal RE specifying the reset period T1 and a selection signal S specifying the selection period T3 after the delay period T2 has elapsed from the reset period T1 are generated. The signal RE and the signal S are input to the shift registers 111 and 112, respectively. Each of the registers 111 and 112 sends the signals RE and S in accordance with the shift clock SCK, and the states in the registers at this time are parallel-out simultaneously for 160 channels. 2to
The four decoder 113 distinguishes the three states (RE, S) = (1, 0) or (0, 1) or (0, 0) according to the register output states of the signals RE and S, and outputs the level shifter 1
14 to the Y driver 115. The Y driver 115 includes a power supply circuit 116 and a phase inversion circuit 117.
, Three voltages are input. The power supply circuit 1
The 16 power supply voltages themselves are swinged to ± Va and ± Vb by the alternating signal FR. Where R
When E and S are (1, 0), the voltage ± Va is selected, when (E, S) is (0, 1), the inverted voltage of ± Va via the phase inverting circuit 117 is selected, and when (0, 0), ± Vb is selected. It is supposed to. For example, Va = V8, -Va = V1, Vb = V
6. If -Vb = V3 is set, the waveform of the scanning signal Yn in FIG. 37 which is the driving waveform of the twenty-first embodiment can be obtained.

FIG. 39 is a block diagram of a drive circuit for a data signal electrode (column electrode). In FIG. 39, 8-bit image data D0 to D7 are input to a data latch circuit 121 via a multiplexer 120, and are converted into 160-channel parallel data by the data latch circuit 121. The latch timing of the data latch circuit 121 is determined by a latch pulse output from the control circuit 122 that inputs the clock SCK. The 160-channel image data is sent from the data latch circuit 121 to the level shifter 123, and at the same time, an inversion operation is performed by a signal from the logic circuit 125 based on the AC signal FR. Therefore, the data signal is generated as a total of four states since two states of on or off are superimposed with two states of plus or minus for alternating current. The X driver 124 that inputs these four states for each channel selects and outputs one level among the power supply voltages VL1 to VL4 for each channel according to the state of each channel. Here, VL1 = V7, VL2 = V2,
By setting VL3 = V5 and LV4 = V4, it is possible to generate the same waveform as the data signal Xm in FIG. 37 showing the drive waveform of the twenty-first embodiment.

In the above description, the scan signal Yn and the scan signal Yn shown in the twenty-first embodiment are used as the scan signal waveform and the data signal waveform generated by each drive circuit shown in FIGS.
The generation of the data signal Xm has been described.
By changing the period of the R signal and the set voltages corresponding to ± Va, ± Vb, and VL1 to VL4, it is possible to generate any of the drive waveforms of the 16th to 20th embodiments.

Twenty-third Embodiment Next, referring to FIGS. 40 to 45, the switching of the voltage in each of the periods T1 to T4 of the scanning signal and the switching of the voltage for each of the selection periods of the data signal will be described in a logical manner. Will be described.

FIG. 40 is a block diagram showing an overall configuration including a liquid crystal panel and its driving circuit. LCD panel 1
The liquid crystal panel 1 has 320 × 320 pixels.
30 to drive the first and second Y driver circuits 1
31A, 131B and first and second X drivers 132
A, 132B are provided. The first and second Y driver circuits 131A and 131B have the same configuration, respectively.
The details are shown in FIG. The X driver circuits 132A and 132B also have the same configuration, and the details are shown in FIG.

First, regarding the Y driver circuit 131A,
This will be described with reference to FIG. This Y driver circuit 131
A is a shift register 1 comprising a select shift register 140A and a reset shift register 140B.
40. The select shift register 140A is
The reset shift register 140B includes the registers SR1 to SR160, and the registers RR1 to RR160.
Having. The selection shift register 140A receives a selection signal S specifying a selection period T3, and is sequentially shifted to the next-stage register by the shift clock YSCL. Note that the contents of the register SR160 are output via the select-out terminal, enabling cascade connection with the second Y driver circuit 131B. A reset signal RE specifying a reset period T1 is input to the reset shift register 140B, and is sequentially shifted to the next-stage shift register by the shift clock YSCL. In addition,
The contents of the register RR160 are output via a reset out terminal, enabling cascade connection with the second Y driver circuit 131B.

The contents in each resist of each shift register 140A, 140B are input to the output control circuit 141 for all 160 channels. The output control circuit 141 has six states, that is, RE, S, FR = (0, 0, 0) or (0, 0, 0) depending on the input states of the reset signal RE, the select signal S, and the AC conversion signal FR.
1) or (0,1,0) or (0,1,1) or (1,0,0) or (1,0,1), and outputs a signal which is distinguished via the level shifter 142. It is input to the Y driver 143. This Y driver 143 has 4
The drive voltages V1Y, V2Y, V3Y, and V4Y are input, and one of the drive voltages is applied to each channel in accordance with the truth table shown in Table 7 based on the six states output separately from the output control circuit 141. Output every time.

[0130]

[Table 7]

The state of the input signal and output signal to each component of the first and second Y driver circuits 131A and 131B having the above configuration is shown in the timing chart of FIG. In the case of the timing chart shown in FIG.
When the length of the selection period T3 is 1H, the signal YFR becomes 1
It is a signal that repeats on / off every H, and the polarity of the voltage applied to the liquid crystal is inverted every 1 H. Further, since one row has 320 pixels, the duty is 1/320, the reset period T1 is set to 5H, and the delay period T2 is set to 2H. The signal waveform of the scanning signal Yn in the n-th row output according to the operation of the driving circuit is
This is shown in FIG.

Next, details of the first X driver circuit 132A will be described with reference to FIG. This first X
The driver circuit 132A has a shift register 150 having 160 registers, and sequentially shifts the input signal EI to the next-stage register according to the shift clock XSCL. The content of the 160th register is E
The signal is output to the outside via the O terminal, and enables cascade connection with the second X driver circuit 132B.

Signal E input to shift register 150
I is 1 in one horizontal scanning period (1H) as shown in FIG.
It is a signal that becomes logical 1 in time. Therefore, the logical 1 is sequentially output from each register of the shift register 150, so that the first latch circuit 151 latches the image data at an address corresponding to each register. The 160-channel data of the first latch circuit 151 is latched by the second latch circuit 152 at the timing when the latch pulse LP is input. AC signal Y
The output control circuit 153 that inputs FR and data from the second latch circuit 152 has four states (D and YF) depending on the input state of the data D and the AC conversion signal YFR.
R) = (0,0) or (0,1) or (1,0) or (1,1)
Through the X driver 155 for each channel. The X driver 155 includes four types of driving voltages V1X,
V2X, V3X, and V4X are input, and one of four drive voltages is output for each channel based on information from the output control circuit 153 according to a truth table shown in Table 8.

[0134]

[Table 8]

Of the data signals for each channel output from X driver 155, data signal X in the m-th column
m is shown in FIG. Further, FIG. 45 shows the scanning signal Y
The difference signal Yn-Xm between n and the data signal Xm is shown. This difference signal is a driving waveform of the twenty-first embodiment shown in FIG.
7, the voltage applied to the liquid crystal is inverted every 1H. Further, since the voltage applied to the liquid crystal is not balanced between plus and minus in one frame, the voltage applied to the liquid crystal is balanced between plus and minus by the successive kth frame and the (k + 1) th frame. In this sense, the difference signal shown in FIG. 45 can be said to be a combination of the polarity inversion every 1H and the polarity inversion every frame, as in the twenty-first embodiment.

As described above, according to the twenty-third embodiment, it is advantageous to switch the voltages of the scanning signal and the data signal in a logical manner as compared with that of the twenty-second embodiment in forming a circuit. Become.

Twenty-fourth Embodiment Next, a driving method capable of changing the delay period T2 in a signal using the driving circuit shown in the twenty-third embodiment will be described with reference to FIGS. 46 and 47. As a method for changing the delay period T2, it is necessary to change the delay period T2 without changing the designated position of the selection period T3 within one frame T, and also to change the reset period T1 before the delay period T2. is there. Therefore, as shown in FIG. 46, when the reset period T1 is 5H and the delay period T2 is 2H, a reset + delay signal having a pulse width of reset period T1 + delay period T2 = 7H is provided before the selection period T3. It is generated. The reset signal input to the reset shift register 140B of each of the Y driver circuits 131A and 131B is the reset signal
It can be generated by an exclusive OR of the delay signal and the delay signal specifying the delay period T2.

Here, when it is necessary to change the delay period T2 in order to compensate for the variation in the threshold value of the liquid crystal of each pixel constituting the liquid crystal panel or the variation in the threshold value of the liquid crystal due to the environmental temperature, The delay period T2 is calculated by the following method.
Then, the designation of the reset period T1 before that is changed.
That is, 2H which is the length of the delay period T2 shown in FIG.
Is changed to 3H as shown in FIG. 47, the pulse width of the reset + delay signal may be changed to 5H + 3H = 8H simultaneously with the change of the delay period T2. By taking the exclusive OR of the changed delay signal and the reset + delay signal, a reset signal having the same 5H reset period T1 as in FIG. 46 can be generated. When it is desired to change the delay period T2 to 3H and the reset period T1 to 7H, the reset + delay signal may be changed to a signal having a pulse width of 7H + 3H = 10H, as shown in FIG.

[0139]

According to the method of the present invention, when driving a chiral nematic liquid crystal having memory properties, the selection period, that is, the writing time is shortened by providing a delay period between the reset period and the selection period. In addition, it is possible to perform a highly practical liquid crystal drive by preventing display flicker. Further, according to the method of the present invention, the writing time per line can be shortened. High-duty liquid crystal driving can be performed.

In addition, according to the method of the present invention, by changing the parameter relating to the application state of the selection pulse, the variation of the threshold value of the liquid crystal in the liquid crystal panel due to the manufacturing or the like, or the driving voltage of the liquid crystal due to the temperature is changed. Fluctuations can be compensated.

In addition, according to the method of the present invention, while applying a reset potential having a relatively large absolute value to cause the Freedericksz transition to the liquid crystal, by adopting the 7-level or 8-level driving method, the scanning signal can be reduced. In addition, it is possible to provide a liquid crystal driving method capable of reducing the voltage imbalance between data signals, simplifying the configuration of a driving circuit, and supporting an IC.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a structure of a liquid crystal cell in an embodiment of a liquid crystal display device according to the present invention.

FIGS. 2A and 2B are drive waveform diagrams of a first embodiment used in an experiment of the present invention, respectively.

FIG. 3 is a driving waveform diagram having no delay period.

FIG. 4 is an explanatory diagram illustrating the behavior of liquid crystal molecules of a bistable liquid crystal used in the present invention.

FIG. 5 is a schematic block diagram illustrating the overall configuration of a liquid crystal drive circuit.

FIG. 6 is a matrix drive waveform diagram according to a second embodiment to which the present invention is applied.

7 is a pulse voltage characteristic diagram of the matrix drive waveform shown in FIG.

FIGS. 8A to 8D are drive waveforms used in the second embodiment of the present invention, and are matrix drive waveform diagrams showing row and column electrode signals and their difference signals.

FIGS. 9A and 9B are driving waveform diagrams used in a third embodiment of the present invention, respectively.

FIGS. 10A to 10E are drive waveform diagrams in which the effective values after the reset pulse off are the same. .

FIGS. 11A to 11E are matrix drive waveform diagrams according to a fourth embodiment to which the present invention is applied.

FIG. 12 is an explanatory diagram showing a scanning order of row electrodes when the driving waveform of FIG. 11 is used.

FIG. 13 is a matrix drive waveform diagram when the fourth embodiment is applied to the drive waveform of FIG.

FIGS. 14A and 14B are driving waveform diagrams used in a fifth embodiment of the present invention, respectively.

FIG. 15 is a drive voltage characteristic diagram when the waveform of FIG. 14A or 14B is applied to liquid crystal.

FIGS. 16A to 16E are matrix drive waveform diagrams according to a sixth embodiment to which the present invention is applied.

17A to 17E are matrix drive waveform diagrams according to a seventh embodiment to which the present invention is applied.

FIG. 18 is a temperature change characteristic diagram of a driving voltage when the driving waveform of FIG. 17 is used.

FIGS. 19A to 19E are matrix drive waveform diagrams according to an eighth embodiment to which the present invention is applied.

FIG. 20 is a block diagram of a drive circuit according to a ninth embodiment of the present invention that can change the duty of the selection pulse width with respect to the selection period.

21 is a detailed diagram of the monostable circuit shown in FIG.

FIG. 22 is a timing chart of the drive circuit of FIG.

FIG. 23 is a block diagram of a drive circuit according to a tenth embodiment of the present invention for digitally changing a duty of a selection pulse width with respect to a selection period.

24 is a timing chart of the drive circuit shown in FIG.

FIG. 25 is a block diagram of a drive circuit according to an eleventh embodiment of the present invention for changing the duty of a data potential period with respect to a selection period.

26 is a timing chart of the drive circuit shown in FIG.

FIG. 27 is a block diagram of a matrix drive circuit according to a twelfth embodiment of the present invention for automatically or manually compensating temperature of a drive voltage.

FIG. 28 is a characteristic diagram showing a threshold value regarding a voltage value of a selection pulse in a liquid crystal having two metastable states.

FIG. 29 is a characteristic diagram illustrating a driving principle of a thirteenth embodiment of the present invention and showing a correlation between a voltage value of a selection pulse and a temperature change of a threshold.

FIG. 30 is a characteristic diagram illustrating a driving principle of a fourteenth embodiment of the present invention and illustrating a correlation between a threshold value regarding a voltage value of a selection pulse and a pulse width of the selection pulse.

FIG. 31 is a characteristic diagram illustrating a driving principle of a fifteenth embodiment of the present invention and illustrating a correlation between a threshold value regarding a voltage value of a selection pulse and a delay time of the selection pulse.

FIGS. 32A to 32D are driving waveform diagrams according to an eight-level driving method according to a sixteenth embodiment of the present invention.

33 (A) to (D) are drive waveform diagrams according to an eight-level drive method according to a seventeenth embodiment of the present invention.

FIGS. 34A to 34D are drive waveform diagrams according to an eight-level drive method according to an eighteenth embodiment of the present invention.

FIGS. 35A to 35D are drive waveform diagrams according to an eight-level drive method according to a nineteenth embodiment of the present invention.

FIGS. 36A to 36D are drive waveform diagrams according to an eight-level drive method according to a twentieth embodiment of the present invention.

FIGS. 37 (A) to (D) are drive waveform diagrams according to an eight-level drive method according to a twenty-first embodiment of the present invention.

FIG. 38 is a block diagram of a Y driver circuit according to a twenty-second embodiment of the present invention for generating the scanning signal waveforms shown in the sixteenth to twenty-first embodiments.

FIG. 39 is a block diagram of an X driver circuit according to a twenty-second embodiment of the present invention for generating the data signal waveforms shown in the sixteenth to twenty-first embodiments.

FIG. 40 is a block diagram showing an overall configuration of a matrix liquid crystal drive circuit according to a twenty-third embodiment of the present invention.

FIG. 41 is a block diagram of a Y driver circuit shown in FIG. 40;

FIG. 42 is a block diagram of the X driver circuit shown in FIG. 40;

FIG. 43 is a timing chart illustrating the operation of each section of the Y driver circuit shown in FIG. 41.

FIG. 44 is a timing chart illustrating a data latch operation in the X driver circuit shown in FIG. 42;

FIG. 45 is a drive waveform diagram generated by the drive circuit shown in FIG. 40.

FIG. 46 is a waveform diagram showing signal waveforms for changing the length of the delay period according to the twenty-fourth embodiment of the present invention.

FIG. 47 is a waveform chart showing signal waveforms when the delay period of FIG. 46 is changed from 2H to 3H.

48 changes the delay period of FIG. 46 from 2H to 3H,
FIG. 9 is a waveform diagram showing signal waveforms when the reset period is changed from 5H to 7H.

FIG. 49 is a threshold distribution diagram of the liquid crystal in the liquid crystal panel.

[Explanation of symbols]

 T1 reset period T2 delay period T3 selection period (first selection period) T4 non-selection period T5 interval period T6 second selection period 1 liquid crystal molecule 2 polyimide alignment film 5 glass substrate 7 polarizing plate 11 liquid crystal cell 12 backlight 13 scanning Drive circuit 14 Signal drive circuit 15 Scan control circuit 16 Signal control circuit 17 Potential setting circuit 18 Line sequential scan circuit 21 Temperature sensor 22 Temperature compensation circuit 30 Reset voltage (reset pulse) 31 Delay voltage 32 Selection voltage (selection pulse) 33 Non-selection Voltage 40 Monostable circuit 43 Variable resistor 70-74 Analog switch 80 Dip switch 81A, 81B Counter 82A, 82B Magnitude comparator 90 Data signal drive circuit 94-96 Analog switch 100 Memory 101 Display A controller 102, 103 driver 104 temperature sensor 106 manual switch 108 liquid crystal display panel 110 logic circuit 111, 112, 140, 150 shift register 114, 123, 142, 154 level shifter 115 Y driver 116 power supply circuit 117 phase inversion circuit 120 multiplexer 121 data Latch circuit 122 Control circuit 124 X driver 141 Output control circuit 143 Y driver 151, 152 Latch circuit 153 Output control circuit 155 X driver

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/36 G09G 3/36 (31) Priority claim number Japanese Patent Application No. 5-263898 (32) Priority date Heisei Heisei October 21, 1993 (Oct. 21, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-275736 (32) Priority date November 4, 1993 ( (1993.11.1.4) (33) Priority Country Japan (JP) (72) Inventor Akira Inoue 3-3-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (72) Inventor Takaaki Tanaka Suwa, Nagano 3-5-5 Yamato-shi, Seiko Epson Corporation (72) Inventor Kenichi Momose 3-5-5 Yamato, Suwa-shi, Nagano Prefecture Seiko Epson Corporation

Claims (14)

[Claims] A liquid crystal molecule sealed between substrates has a predetermined twist angle in an initial state, and is a relaxed state after applying a voltage that causes a Freedericksz transition in the initial state. A liquid crystal having two metastable states; a plurality of row electrodes formed on one of the substrates and supplied with row electrode signals; and a plurality of column electrodes formed on the other substrate and supplied with column electrode signals, respectively. And driving the liquid crystal display device having a pixel at an intersection of the row electrode and the column electrode, and applying a voltage of a difference signal between the row electrode signal and the column electrode signal to the liquid crystal facing the pixel. (A) the difference signal includes a selection period shifted for each row electrode, a non-selection period following the selection period, and a reset period set before the selection period in one frame period. Included in b) the column electrode signal is set to a data potential including two types of ON selection potential or OFF selection potential for each selection period corresponding to each of the pixels on the same column electrode; In the electrode signal, two types of reset potentials for applying positive and negative reset voltages to the liquid crystal during the reset period are set, and positive and negative selection voltages are applied to the liquid crystal during the selection period. Are set as the non-selection period, an intermediate potential between the two types of the select potentials is set as the non-selection potential in the non-selection period, and the liquid crystal is driven using a total of seven levels of potentials. A method for driving a liquid crystal display device, comprising: 2. The method according to claim 1, wherein the non-selection potential is set to a ground potential, the two types of reset potentials are set to + V1 and −V1, respectively, and the two types of selection potentials are set to + V2 and −V2 ( V2 <V1), and the data potentials are set to + V3 and -V3 (V3 <V
A method for driving a liquid crystal display device, wherein the method is set in 2). 3. A liquid crystal molecule sealed between substrates has a predetermined twist angle in an initial state, and is a relaxed state after applying a voltage that causes a Freedericksz transition in the initial state. Liquid crystals having two meta-stable states; a plurality of row electrodes formed on one of the substrates and supplied with row electrode signals; and a plurality of columns formed on the other substrate and supplied with column electrode signals, respectively. A liquid crystal display device having an electrode, the intersection of the row electrode and the column electrode as a pixel, and applying the voltage of the difference signal between the row electrode signal and the column electrode signal to the liquid crystal facing the pixel. In the driving method for driving, (a)
The difference signal includes a selection period shifted for each row electrode, a subsequent non-selection period, and a reset period set before the selection period within one frame period,
(B) the column electrode signal is set to a data potential including an ON potential or an OFF potential for each of the selection periods corresponding to the respective pixels on the same column electrode; As the data potential, four types of potentials for applying a positive and negative ON selection voltage and a positive and negative OFF selection voltage to the liquid crystal are set, and (c) the row electrode signal is set during the reset period. Is set to a reset potential, is set to a selection potential during the selection period, is set to a non-selection potential during the non-selection period, and is used as the reset potential in the liquid crystal during the reset period. Two types of potentials for applying a voltage are set, and two types of potentials for applying the positive and negative selection voltages to the liquid crystal during the selection period are set as the selection potential. As the non-selection potential, two types of potentials for applying a bias potential to the four types of data potentials in the selection period are set, and the liquid crystal is driven using at least eight levels of potentials. For driving a liquid crystal display device. 4. The method according to claim 3, wherein the potential of eight levels is changed to four levels (V) of the first group on the low voltage side.
1, V2, V3, V4: V1 <V2 <V3 <V4, and four levels (V5, V6, V7, V8: V4 <V5 <of the second group on the high voltage side)
V6 <V7 <V8), and when the data potential of the column electrode signal is in the first group,
The reset potential is selected from a second group, and when the data potential of the column electrode signal is in a second group, the reset potential is selected from a first group. In the period, when the data potential of the column electrode signal is in the first group, each one potential is selected from the same first group, and the data potential of the column electrode signal is in the second group. When in a group,
A method for driving a liquid crystal display device, wherein one potential is selected from each of the same second group. 5. The reset voltage applied to the liquid crystal during the reset period by increasing a potential difference between the first group potential V4 and the second group potential V5 according to claim 4. A method for driving a liquid crystal display device, wherein the value is set to be large. 6. The apparatus according to claim 4, wherein in a k-th frame (k is an integer), an ON selection potential of the column electrode signal is set to V5 of the second group, and an OFF selection potential is set to V7. The reset potential of the row electrode signal is set to V1, the selection potential is set to V8, and the non-selection potential is set to V6. In the subsequent (k + 1) th frame, the ON selection of the column electrode signal is performed. The potential is set to V4 of the first group, the OFF selection potential is set to V2, the reset potential of the row electrode signal is set to V8, the selection potential is set to V1, and the non-selection potential is set to V3. A method for driving a liquid crystal display device, comprising: inverting the polarity of a voltage applied to a liquid crystal for each frame to drive the liquid crystal by alternating current. 7. The system according to claim 4, wherein in a k-th frame (k is an integer), an ON selection potential of the column electrode signal is set to V8 of the second group, and an OFF selection potential is set to V6. The reset potential of the row electrode signal is set to V1, the selection potential is set to V5, and the non-selection potential is set to V7. In the subsequent (k + 1) th frame, the ON selection of the column electrode signal is performed. The potential is set to V1 of the first group, the OFF selection potential is set to V3, the reset potential of the row electrode signal is set to V8, the selection potential is set to V4, and the non-selection potential is set to V2. A method of driving a liquid crystal display device, comprising: inverting the polarity of a voltage applied to the liquid crystal for each frame, and driving the liquid crystal by alternating current. 8. The method according to claim 4, wherein an ON selection potential of the column electrode signal in one frame period is set by an AC pulse of V4 and V5, and an OFF selection potential of the column electrode signal is set to V2 and V7. Set by the AC pulse of
In a corresponding order, the reset potential of the row electrode signal is set by an AC pulse of V8 and V1, the selection potential is set by an AC pulse of V1 and V8, and the non-selection potential is V3 and V6. And a voltage applied to the liquid crystal is inverted for each pulse to drive the liquid crystal by AC. 9. A driving method for a liquid crystal display device according to claim 6, wherein a relationship of V4-V3 = V3-V2 = V7-V6 = V6-V5 is set. 10. The column electrode signal according to claim 4, wherein an ON selection potential of the column electrode signal within one frame period is set by an AC pulse of V1 and V8.
The FF selection potential is set by an AC pulse of V3 and V6, the reset potential of the row electrode signal is set by an AC pulse of V8 and V1 in an order corresponding to this, and the selection potential is set to V4
AC voltage of V5 and V5, the non-selection potential is set by an AC pulse of V2 and V7, and the liquid crystal is AC-driven by inverting the polarity of the voltage applied to the liquid crystal for each pulse. Characteristic driving method of a liquid crystal display device. 11. The driving method for a liquid crystal display device according to claim 7, wherein a relationship of V3-V2 = V2-V1 = V8-V7 = V7-V6 is set. 12. The method according to claim 8, wherein when a unit time corresponding to the selection period is 1H, a pulse width of the signal FR for converting the row electrode signal and the column electrode signal into AC is 1H, and A method for driving a liquid crystal display device, wherein a phase of a signal FR is set to be shifted by (1H / 2) with respect to a selection period of the row electrode signal Yn. 13. The method according to claim 8, wherein the polarity of the voltage applied to the liquid crystal is inverted every unit time (1H) corresponding to the selection period, and the k-th frame (k is an integer) is started. When the polarity is positive, the (k +
1) The polarity at the beginning of the frame is negative, and when the polarity at the beginning of the k-th frame is negative, the (k + 1) th
The polarity at the beginning of the frame is positive, and the combination of the polarity inversion every 1H and the polarity inversion every frame gives
A method for driving a liquid crystal display device, wherein the liquid crystal is AC driven. 14. The liquid crystal according to claim 4, wherein each voltage of the first group and each voltage of the second group are set to be positive and negative symmetrically with respect to a ground level. A method for driving a display device.