JP2001231248A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of restraining boosting efficiency from lowering by a substrate bias effect or the like of a charge transfer transistor in a booster circuit. SOLUTION: Charge transfer transistors T1-T4 are arranged in series in the booster circuit 10, and the gates of the charge transfer transistors T1-T4 are alternately connected to the supply wiring of a clock signal Φ1 or Φ2 through booster capacities P1-P4 respectively. The gate length of the charge transfer transistor T1 on the previous stage side is 0.8 μm. On the other side, the gate lengths of the charge transfer transistors T2-T4 on the subsequent stage side are shorter than it, 0.5 μm. The threshold voltages of the charge transfer transistors T2-T4 on the subsequent stage side are smaller than that of the charge transfer transistor T1 on the previous stage side. The charge transfer transistor and an MIS-type transistor in another logic circuit have impurities concentration distribution in a common channel area and gate insulating film thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device equipped with a booster circuit, and more particularly to a measure for improving boosting efficiency.

[0002]

2. Description of the Related Art FIG. 4 is an electric circuit diagram showing a circuit diagram of a typical conventional booster circuit 50. As shown in FIG. As shown in the figure, in the booster circuit 50, a switching transistor Tsw is provided between a power supply voltage input terminal 51 for supplying a power supply voltage Vdd and a boosted voltage output terminal 52 for outputting a boosted voltage Vpp. , Each having a gate length Lg51 to Lg54 of about 0.8 μm
The m charge transfer transistors T51 to T54 are arranged in series. In the figure, four charge transfer transistors T51 to T54 are shown as an example, but a number of charge transfer transistors corresponding to the boost ratio are arranged. Then, for example, the odd-numbered charge transfer transistors T51, T51
The gate of 53 is connected to the supply line of the clock signal φ1 via the boost capacitors P51 and P53, and the gate of the even-numbered charge transfer transistors T52 and T54 is connected to the boost capacitor P5.
2 and P54 are connected to a supply line for the clock signal φ2. In this example, one charge transfer transistor and one boosting capacitor constitute one unit boosting block.

When this booster circuit is operated, the booster capacitance P5 is generated by the clock signals φ1 and φ2 whose phases are shifted by π.
1 to P54 are transferred to the charge transfer transistors T51 to T5.
4 to the subsequent stage, and as a result, the input power supply voltage Vdd is pumped up to the boosted voltage Vpp.

[0004]

However, in the conventional booster circuit 50, the charge transfer transistor T
Among the charge transfer transistors 51 to T54, the threshold voltage Vth increases with the substrate bias effect in the later charge transfer transistors.
Since dd-Vth is reduced, when the number of stages of the charge transfer transistors is increased, there is a problem that the boosting efficiency in the path from the voltage reduction input terminal 51 to the boosted voltage output terminal 52 is significantly reduced. The charge transfer transistor T5
There is also a problem that the load due to the channel resistance of 1 to T54 increases, and especially when the booster circuit 50 is operated at high speed, the boosting characteristics are deteriorated. Such disadvantages have become more important with higher performance of semiconductor integrated circuit devices such as low power supply voltage and high-speed operation.

An object of the present invention is to provide a booster circuit having a large number of boosting stages, that is, arranging a large number of charge transfer transistors, by taking measures to suppress a reduction in boosting efficiency due to a substrate bias effect and a channel resistance of a charge transfer transistor. It is another object of the present invention to realize a booster circuit which maintains excellent boosting efficiency at a low power supply voltage and a high clock frequency without increasing a circuit area and a manufacturing process in a semiconductor integrated circuit device.

[0006]

A first semiconductor integrated circuit device according to the present invention supplies a logic circuit having MIS transistors arranged therein and a boosted voltage having a logic amplitude larger than a power supply voltage to the logic circuit. And a booster circuit for performing the boosting circuit, wherein the booster circuit has at least one between an input unit for inputting the power supply voltage and an output unit for outputting the boosted voltage. A plurality of unit boosting blocks each including a boosting capacitor and at least one MIS type charge transfer transistor of the first conductivity type are connected in series, and the MIS type charge transfer transistor of at least one unit boosting block of the boosting circuit is configured. The length of the gate electrode in the channel direction is shorter than the length of the gate electrode of the MIS transistor of the logic circuit in the channel direction.

Thus, by using the MIS type charge transfer transistor having a shorter gate length than the MIS type transistor of the logic circuit, the channel resistance of the MIS type charge transfer transistor is reduced and the load at the time of charge transfer is reduced. Therefore, a booster circuit capable of maintaining excellent boosting efficiency even when a low power supply voltage or a high clock frequency is used can be obtained. In addition, since it is not necessary to separately provide a transistor or the like for control, a circuit area is not increased.

The MIS-type charge transfer transistor of the booster circuit and the MIS-type transistor of the logic circuit have the same impurity concentration distribution in the channel region and the same thickness of the gate insulating film. By making the absolute value of the threshold voltage of the short MIS type charge transfer transistor smaller than the absolute value of the threshold voltage of the gate electrode of the MIS type transistor of the above logic circuit, the substrate bias effect of the charge transfer transistor on the subsequent stage can be obtained. , It is possible to suppress a decrease in boosting efficiency due to the above, and to realize a boosting circuit with low current consumption and small characteristic variations. Further, since the impurity concentration distribution of the channel region and the thickness of the gate insulating film of the MIS type charge transfer transistor and the MIS type transistor of the logic circuit are common, the booster circuit having excellent characteristics without increasing the number of manufacturing steps. Can be realized.

By providing the MIS transistor and the MIS charge transfer transistor of the logic circuit with the same impurity concentration distribution in the source and drain regions, the number of manufacturing steps including the formation of the source and drain regions can be increased. However, when extracting device parameters for circuit simulation, there is an advantage that device parameters can be efficiently extracted from the MIS-type charge transfer transistor and the MIS-type transistor in the logic circuit.

A second semiconductor integrated circuit device according to the present invention has a M
In a semiconductor integrated circuit device including a logic circuit in which an IS-type transistor is arranged, and a booster circuit for supplying a boosted voltage having a logic amplitude larger than a power supply voltage to the logic circuit, the booster circuit includes: A unit boost block including at least one boost capacitor and at least one MIS charge transfer transistor of the first conductivity type between an input unit for inputting a power supply voltage and an output unit for outputting the boost voltage. Are connected in series in n stages (n ≧ 2), and the threshold of the MIS-type charge transfer transistor of the k-th unit booster block (2 ≦ k ≦ n) of the n-stage unit booster blocks The absolute value of the value voltage is configured to be smaller than the absolute value of the threshold voltage of the MIS-type charge transfer transistor in the (k-1) th unit boosting block.

Thus, the MIS type charge transfer transistor having a low threshold voltage is disposed in the subsequent unit boosting block, thereby compensating for a rise in the threshold voltage caused by the substrate bias effect which becomes prominent in the subsequent stage. And each MI
The threshold voltage of the S-type charge transfer transistor can be adjusted to be optimal according to the number of stages of the booster circuit, and boosting efficiency can be improved. Also, unlike controlling the threshold by control or the like, there is no need to separately arrange a transistor for controlling the threshold.
There is no increase in circuit area.

The MIS transistor and the MIS charge transfer transistor of the logic circuit have the same impurity concentration distribution in the channel region and the same thickness of the gate insulating film as those of the MIS transistor and the MIS charge transfer transistor. By making the channel direction length of the gate electrode of the MIS type charge transfer transistor of the unit boosting block shorter than the channel direction length of the gate electrode of the MIS type charge transfer transistor of the (k-1) th unit boosting block,
The threshold voltage can be adjusted using the short channel effect, and the MIS-type charge transfer transistor having a shorter gate length is arranged at a later stage according to the number of unit boosting blocks in the booster circuit. The charge transfer load can be reduced by reducing the overall channel resistance of the charge transfer transistor. In addition, in the unit boosting block on the preceding stage, by suppressing the leakage current of the MIS-type charge transfer transistor, variation in boosting characteristics and current consumption can be reduced, so that boosting efficiency and stability of boosting characteristics are excellent even at a high clock frequency. A booster circuit can be realized. Further, since the impurity concentration distribution of the channel region and the thickness of the gate insulating film of the MIS type charge transfer transistor and the MIS type transistor of the logic circuit are common, the booster circuit having excellent characteristics without increasing the number of manufacturing steps. Can be realized.

The MIS type transistor and the MIS type charge transfer transistor of the logic circuit have the same impurity concentration distribution in the source and drain regions, thereby increasing the number of manufacturing steps including formation of the source and drain regions. In addition, when extracting device parameters for circuit simulation, there is an advantage that device parameters can be efficiently extracted from the MIS type charge transfer transistor and the MIS type transistor in the logic circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block circuit diagram showing a configuration of a flash memory built-in microcomputer 1 which is a semiconductor integrated circuit according to a first embodiment of the present invention. That is, the microcomputer 1 in the present embodiment
Is a flash memory cell array 2, a row decoder 3 connected to each memory cell in the flash memory cell array 2 via a word line, and a data line (bit line) to each memory cell in the flash memory cell array 2. A column decoder 4 connected thereto, a sense amplifier 5 used for reading data from each memory cell, an SRAM 6 in which a static memory cell array (not shown) and its peripheral circuits (not shown) are arranged, Circuit 1
Microcomputer circuit (MPU) 7 for controlling the operation of 6
And a booster circuit 10 for boosting the power supply voltage Vdd and supplying the boosted voltage to each circuit via the regulator 8.

FIG. 2 is an electric circuit diagram of the booster circuit 10. As shown in FIG.
The configuration of 0 is basically the same as the configuration of the conventional booster circuit 50 shown in FIG. That is, between the power supply voltage input terminal 11 for supplying the power supply voltage Vdd and the boosted voltage output terminal 12 for outputting the boosted voltage Vpp, the switching transistor Tsw and the charge transfer transistors T1 to T
4 are arranged in series. FIG. 2 shows four charge transfer transistors T1 to T4 as an example,
A number of charge transfer transistors can be provided according to the boosting ratio. For example, the gates of the odd-numbered charge transfer transistors T1 and T3 are connected to the supply line for the clock signal φ1 via the boost capacitors P1 and P3, and the gates of the even-numbered charge transfer transistors T2 and T4 are connected to the boost capacitor P2.
2 and P4 are connected to a supply line for a clock signal φ2. In this example, one charge transfer transistor and one boosting capacitor constitute one unit boosting block.

When the booster circuit 10 is operated, the charges of the booster capacitors P1 to P4 are transferred to the subsequent stage via the charge transfer transistors T1 to T4 by the clock signals φ1 and φ2 whose phases are shifted by π. The input power supply voltage Vdd is pumped up to the boosted voltage Vpp. This operation is the same as the operation of the conventional booster circuit 50 described above.

Here, the booster circuit 10 in the present embodiment
The feature is that the gate length Lg, which is the dimension of the gate electrodes of the charge transfer transistors T1 to T4 in the channel direction, is not common, and the gate length Lg1 of the first-stage charge transfer transistor T1 is 0.8 μm. , The gate lengths Lg2 to Lg2 of the charge transfer transistors T2 to T4 on the subsequent stage.
g4 is as short as 0.5 μm. That is, the gate lengths Lg2 to Lg4 of the subsequent charge transfer transistors T2 to T4 are shorter than the gate length Lg1 of the previous charge transfer transistor T1.

Hereinafter, the detailed structure of the semiconductor integrated circuit of the present embodiment will be described with reference to FIGS.

In the microcomputer 1 with a built-in flash memory shown in FIG. 1, a high voltage (for example, a maximum of 12 V) is required for the write / erase operation of the flash memory, and therefore, a row decoder 2, a column decoder 3, a regulator 4, a microcomputer 7 are high voltage transistors (MOSFE having a gate oxide film thickness of about 15 nm).
T) is arranged, and the minimum gate length of the high breakdown voltage transistor in the row decoder 2, the column decoder 3, and the regulator 4 is 0.8 μm.

Each of the charge transfer transistors T1 to T1 shown in FIG.
T4 is an NMOSFET in which the gate length Lg1 of the charge transfer transistor T1 is 0.8 μm, which is the same as the minimum gate length of the row decoder 2 or the like. On the other hand, as described above, the gate lengths Lg2 to Lg4 of the subsequent charge transfer transistors T2 to T4 are all reduced to 0.5 μm. As a result, while the threshold voltage Vt1 of the charge transfer transistor T1 is 0.6 V, the threshold voltages Vt2 and Vt of the subsequent charge transfer transistors T2, T3 and T4 are changed.
3, Vt4 is reduced to 0.3 V due to the short channel effect. The source / drain diffusion layers of any of the NMOSFET charge transfer transistors T1 to T4 are formed at the same time as the source / drain diffusion layers of the high breakdown voltage transistor constituting the row decoder 2 and the like. That is, any of the charge transfer transistors T1 to T
The source / drain diffusion layers of No. 4 also have the same impurity concentration distribution as the source / drain diffusion layers of the high breakdown voltage transistors forming the row decoder 2 and the like. Further, the channel regions of all the charge transfer transistors T1 to T4 have the same impurity concentration distribution as the channel regions of the high breakdown voltage transistors constituting the row decoder 2 and the like.

When the booster circuit 10 is operated by applying a clock signal having an amplitude (for example, an amplitude of 3 V) equal to the difference between the power supply voltage Vdd and the ground voltage, the charge transfer transistors T2, T3, and T4 at the subsequent stage become active. Therefore, the threshold voltages Vt2, Vt3, and Vt4 increase due to the substrate bias effect, so that the boosted voltage Vdd-Vtn (n = 1, 1) per stage.
2, 3, 4), but the threshold voltages Vt2, Vt3, Vt4 of the subsequent charge transfer transistors T2, T3, T4.
, The influence of the substrate bias effect is small, and the input power supply voltage Vdd (3 V) can be boosted to a desired boosted voltage Vpp (13 V) to be output.

Further, the charge transfer transistors T2 and T2 in the subsequent stage
Since the gate lengths Lg2, Lg3, and Lg4 of T3 and T4 are reduced from 0.6 μm to 0.5 μm of the gate length of the MIS transistor such as a microcomputer circuit, and the channel resistance is reduced, the load at the time of charge transfer is reduced. Become. Therefore, for example, a high-frequency clock signal φ of about 200 MHz
Even if 1, 2 is used, the boosting efficiency does not decrease,
A normal boost operation can be obtained. In addition, there is no need to separately provide a transistor or the like for control, so that the circuit area and the manufacturing process are not increased.

In this embodiment, the source / drain diffusion layers of any of the charge transfer transistors T1 to T4 are
Since it has the same impurity concentration distribution as the source / drain diffusion layers of the high breakdown voltage transistor constituting the row decoder 2 and the like, not only the manufacturing process is simplified, but also device parameters for circuit simulation are extracted. At this time, the MIS type charge transfer transistor and the row decoder 2
There is an advantage that the device parameters can be efficiently extracted together with the high withstand voltage transistor among the above.

Further, any charge transfer transistor T
Since the channel regions 1 to T4 also have the same impurity concentration distribution as the channel region of the high breakdown voltage transistor constituting the row decoder 2 and the like, the manufacturing process is further simplified.

In this embodiment, the charge transfer transistors T1 to T4 are all NMOSFETs.
For example, even if this embodiment is applied to a booster circuit configured to perform a boosting operation in accordance with a negative gate voltage by disposing a PMOSFET, the same effect as that of this embodiment can be obtained. Also in this case, since the gate length of the charge transfer transistor on the subsequent stage is shorter than the gate length of the charge transfer transistor on the preceding stage, the absolute value of the threshold voltage of each charge transfer transistor becomes smaller toward the latter stage.

(Second Embodiment) Also in this embodiment, the block configuration of a microcomputer with a built-in flash memory is as follows.
This is the same as the first embodiment. Only the configuration of the booster circuit is different from that of the first embodiment.

FIG. 3 shows a booster circuit 20 according to this embodiment.
FIG. As shown in the figure, the configuration of the booster circuit 20 in the present embodiment is also basically the same as the configuration of the booster circuit 10 of the first embodiment shown in FIG. That is, a switching transistor Tsw is provided between a power supply voltage input terminal 21 for supplying the power supply voltage Vdd and a boosted voltage output terminal 22 for outputting the boosted voltage Vpp.
The charge transfer transistors T11 to T14 are arranged in series. Although four charge transfer transistors T11 to T14 are shown in FIG. 3 as an example, a number of charge transfer transistors according to the boosting ratio can be provided. Then, the odd-numbered charge transfer transistors T11, T13
Are connected to the supply line for the clock signal φ1 via the boost capacitors P11 and P13, and the gates of the even-numbered charge transfer transistors T12 and T14 are connected to the boost capacitors P12 and P14.
14 is connected to the supply line of the clock signal φ2. Also in this example, one unit boosting block is constituted by one charge transfer transistor and one boosting capacitor.

When the booster circuit 20 is operated, the charges of the booster capacitors P11 to P14 are changed by the clock signals φ1 and φ2 whose phases are shifted by π, respectively.
The operation is also the same as the operation of the booster circuit 10 in the first embodiment in that the power supply voltage Vdd is transferred to the subsequent stage via T14, and as a result, the input power supply voltage Vdd is pumped up to the boosted voltage Vpp.

Here, the booster circuit 20 in the present embodiment
Is characterized in that the gate length Lg11 of the first stage charge transfer transistor T11 is 0.8 μm and the MIS in the row decoder 2
The gate length Lg12 of the second-stage charge transfer transistor T12 is 0.7 μm, while the gate length Lg13 of the third-stage charge transfer transistor T13 is 0.6 μm. The point is that the gate length LgLg14 of the charge transfer transistor T14 is formed as short as 0.5 μm. That is, the gate length of the charge transfer transistor in the k-th (2 ≦ k ≦ n) unit boost block of the boost circuit 20 is equal to or less than the gate length of the charge transfer transistor in the (k−1) -th unit boost block. It is set to be.

In the microcomputer 7 with a built-in flash memory shown in FIG. 1, a high voltage (for example, a maximum of 12 V) is required for the writing / erasing operation of the flash memory. Therefore, the row decoder 2, the column decoder 3, the regulator 4, All circuits such as the microcomputer 7 include high-voltage transistors (MOS transistors having a gate oxide film thickness of about 15 nm).
FET) are arranged, and the minimum gate length of the high breakdown voltage transistor in the row decoder 2, the column decoder 3, and the regulator 4 is 0.8 μm, as in the first embodiment.

Each charge transfer transistor T11 shown in FIG.
To T14 are all NMOSFETs. Since the gate length Lg11 of the first-stage charge transfer transistor T11 is 0.8 μm, which is the same as the minimum gate length of the row decoder 2 or the like, the threshold voltage Vt11 is 0.6V. It is. If the gate length Lg12 of the charge transfer transistor T12 of the second stage is 0.
Since the thickness is 7 μm, the threshold voltage Vt12 is reduced to 0.5 V due to the short channel effect.
The gate length Lg13 of the third-stage charge transfer transistor T13
Is 0.6 μm, their threshold voltages V
t13 is reduced to 0.4 V due to the short channel effect. Since the gate length Lg14 of the fourth stage charge transfer transistor T14 is 0.5 μm, the threshold voltage Vt14 is 0.3 V due to the short channel effect.
It has dropped to.

The source / drain diffusion layers of the charge transfer transistors T11 to T14, which are NMOSFETs, are formed simultaneously with the source / drain diffusion layers of the high breakdown voltage transistors constituting the row decoder 2 and the like. That is, any of the charge transfer transistors T11 to T11
The source / drain diffusion layer of T14 also has the same impurity concentration distribution as the source / drain diffusion layers of the high breakdown voltage transistor constituting the row decoder 2 and the like. Further, the channel regions of all the charge transfer transistors T11 to T14 have the same impurity concentration distribution as the channel regions of the high breakdown voltage transistors constituting the row decoder 2 and the like.

When the booster circuit 20 is operated by applying a clock signal having an amplitude equal to the difference between the power supply voltage Vdd and the ground voltage (for example, an amplitude of 3 V), the charge transfer transistors T12, T13, T14 in the middle stage and the subsequent stage are operated. Since the threshold voltages Vt12, Vt13, and Vt14 are low, the influence of the substrate bias effect is small, and the input power supply voltage Vdd (3 V)
Can be boosted to a desired boosted voltage Vpp (12.5 V) to be output.

Also, the gate lengths Lg12, Lg13, Lg13 of the charge transfer transistors T12, T13, T14 in the middle and later stages are set.
Since Lg14 is reduced and the channel resistance is reduced, a normal boosting operation can be obtained even if high-frequency clock signals φ1 and φ2 of, for example, about 200 MHz are used.

Further, the gate length Lg11 of the first stage charge transfer transistor T11 is set to 0.8 μm and the gate length Lg12 of the second stage charge transfer transistor T12 is set to 0 in accordance with the output voltage of each unit boosting block. .7 μm, third
The gate length Lg13 of the charge transfer transistor T13 at the stage is set to 0.6 μm, and the charge transfer transistor T14 at the stage
By optimizing each of the gate lengths Lg14 to 0.5 μm, the channel resistance of the entire charge transfer transistor can be reduced and the leak current of the first-stage charge transfer transistor T11 and the like can be suppressed. Variations in boost characteristics of the boost circuit 20 can be reduced, and current consumption can be reduced.

In this embodiment, the source / drain diffusion layers of any of the charge transfer transistors T11 to T14 have the same impurity concentration distribution as the source / drain diffusion layers of the high breakdown voltage transistors constituting the row decoder 2 and the like. Not only simplifies the manufacturing process, but also extracts MIS type charge transfer transistors and high breakdown voltage transistors in the row decoder 2 and the like when extracting device parameters for circuit simulation. There is an advantage that device parameters can be efficiently extracted.

Further, any charge transfer transistor T
Since the channel regions 11 to T14 also have the same impurity concentration distribution as the channel regions of the high breakdown voltage transistors forming the row decoder 2 and the like, the manufacturing process is further simplified.

In this embodiment, the charge transfer transistors T11 to T14 are all NMOSFETs. However, the charge transfer transistors T11 to T14 are arranged in a booster circuit configured to perform a boosting operation in accordance with a negative gate voltage by disposing a PMOSFET, for example. Even when the embodiment is applied, the same effect as that of the embodiment can be obtained.

[0039]

According to the first semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device having a logic circuit and a booster circuit, the booster circuit includes at least one booster capacitor and at least one first conductivity type. And a plurality of unit boosting blocks including the MIS type charge transfer transistors are connected in series, and the channel direction length of the gate electrode of the MIS type charge transfer transistor of at least one unit boosting block is determined by the Since the configuration is made shorter than the length of the gate electrode in the channel direction, by reducing the load during charge transfer, it is possible to achieve excellent boosting efficiency at low power supply voltages and high clock frequencies without increasing the circuit area. A booster circuit that can be held can be realized.

According to the second semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device including a logic circuit and a booster circuit, the booster circuit includes at least one booster capacitor and at least one MIS of the first conductivity type. And a unit booster block including n-type charge transfer transistors connected in series in n stages. The absolute value of the threshold voltage of the MIS-type charge transfer transistor in the k-th unit booster block is set to the (k-1) th stage. Since the absolute value of the threshold voltage of the MIS type charge transfer transistor in the unit boosting block is made smaller than the absolute value of the threshold voltage of each MIS type charge transfer transistor, the threshold voltage of each MIS type charge transfer transistor is optimized according to the number of stages of the booster circuit. The adjustment can be performed, and the boosting efficiency can be improved without increasing the circuit area.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of a microcomputer with a built-in flash memory according to a first embodiment of the present invention.

FIG. 2 is an electric circuit diagram of the booster circuit according to the first embodiment of the present invention.

FIG. 3 is an electric circuit diagram of a booster circuit according to a second embodiment of the present invention.

FIG. 4 is an electric circuit diagram of a booster circuit of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 microcomputer 2 flash memory cell array 3 row decoder 4 column decoder 5 sense amplifier 6 SRAM 7 microcomputer circuit 8 regulator 10 booster circuit 11 power supply voltage input terminal 12 booster voltage output terminal 20 booster circuit 21 power supply voltage input terminal 22 booster voltage output terminal Tsw switching Transistors T1 to T4 Charge transfer transistors P1 to P4 Boost capacitance T11 to T14 Charge transfer transistors P11 to P14 Boost capacitance

Claims (6)

[Claims] 1. A semiconductor integrated circuit device comprising: a logic circuit in which a MIS transistor is arranged; and a booster circuit for supplying a boosted voltage having a logic amplitude larger than a power supply voltage to the logic circuit. The booster circuit includes at least one booster capacitor and at least one MIS charge transfer transistor of the first conductivity type between an input unit for inputting the power supply voltage and an output unit for outputting the boosted voltage. And at least one unit boosting block of the boosting circuit is connected.
A semiconductor integrated circuit device, wherein the length of the gate electrode of the IS-type charge transfer transistor in the channel direction is shorter than the length of the gate electrode of the MIS transistor of the logic circuit in the channel direction. 2. The semiconductor integrated circuit device according to claim 1, wherein the MIS-type charge transfer transistor of the booster circuit and the MIS-type transistor of the logic circuit have the same impurity concentration distribution in the channel region and the same thickness of the gate insulating film. Wherein the absolute value of the threshold voltage of the MIS charge transfer transistor whose gate electrode has a short length in the channel direction is smaller than the absolute value of the threshold voltage of the gate electrode of the MIS transistor of the logic circuit. A semiconductor integrated circuit device characterized by being small. 3. The semiconductor integrated circuit device according to claim 1, wherein the MIS transistor and the MIS charge transfer transistor of the logic circuit have the same source / drain region impurity concentration distribution. Semiconductor integrated circuit device. 4. A semiconductor integrated circuit device comprising: a logic circuit in which a MIS transistor is arranged; and a booster circuit for supplying a boosted voltage having a logic amplitude larger than a power supply voltage to the logic circuit. The booster circuit includes at least one booster capacitor and at least one MIS charge transfer transistor of the first conductivity type between an input unit for inputting the power supply voltage and an output unit for outputting the boosted voltage. Are connected in series in n stages (n ≧ 2), and the k-th stage (2 ≦ k ≦
n) the absolute value of the threshold voltage of the MIS charge transfer transistor of the unit booster block is smaller than the absolute value of the threshold voltage of the MIS charge transfer transistor of the (k-1) th unit booster block A semiconductor integrated circuit device comprising: 5. The semiconductor integrated circuit device according to claim 4, wherein the MIS transistor and the MIS charge transfer transistor of the logic circuit have the same impurity concentration distribution in the channel region and the same thickness of the gate insulating film. The length of the gate electrode of the MIS charge transfer transistor of the k-th unit boost block in the channel direction in the unit boost block is the MIS charge transfer transistor of the (k-1) -th unit boost block. Wherein the length of the gate electrode is shorter than the length of the gate electrode in the channel direction. 6. The semiconductor integrated circuit device according to claim 4, wherein the MIS transistor and the MIS charge transfer transistor of the logic circuit have the same source / drain region impurity concentration distribution. Semiconductor integrated circuit device.