JP2001230373A - Flat semiconductor device and power converter using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat semiconductor device which can simplify the treatment of gate signal wiring, storing a plurality of semiconductor chips in high density with positioning accuracy, and a large-capacity power converter using it. SOLUTION: This flat semiconductor device is given a function of deciding en block the positions, within a package, of a plurality of semiconductor chips mounted and or a plurality of middle electrodes arranged in the semiconductor chips, by constituting control signal wiring, which is provided within itself so as to transmit the control signal from outside a package to each chip, of a component which is molded integrally with insulating material 23, and providing this component with insulating member projections 12 and providing its interior with extraction electrodes, and further this stores control signal wiring parts shown in the figure within the common electrodes of the package, and connects the control electrode and the lead electrode of each semiconductor chip to them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat semiconductor device and a power converter using the same, and more particularly, to a low-cost semiconductor device.
The present invention relates to a flat semiconductor device having high reliability and a power converter using the same.

[0002]

2. Description of the Related Art In recent years, power electronics technology for controlling main circuit current by making full use of semiconductor electronics technology has been applied in a wide range of fields, and the field of application has been expanding. As power semiconductor elements, thyristors, optical thyristors, GTO (Gate Turn-off) thyristors, GCT (Gate Commutated Turn-off) thyristors, insulated gate bipolar transistors (hereinafter referred to as IGBTs) and MOSs as MOS control devices Type field effect transistor (hereinafter referred to as MOSFET)
And diodes. These semiconductor devices generally have a first main electrode (cathode electrode, emitter electrode) and a control electrode formed on a first main surface of a semiconductor substrate, and a second electrode.
Another main electrode (anode electrode, collector electrode) is formed on the main surface side.

A high-power semiconductor device such as a GTO or an optical thyristor is configured by packaging elements for each wafer. Both main electrodes of such a semiconductor element are
The package is configured to be brought into pressure contact with a pair of external main electrodes of a package via a heat buffering electrode plate made of Mo or W, and generally has a flat structure suitable for pressure application.

On the other hand, IGBTs and the like have conventionally been constituted by mounting a plurality of chips in a package form of an electrode connection system using wires, which is mainly called a modular structure. Such a module type package dissipates the heat generated inside the element only from one side of the package, that is, only from the collector side directly mounted on the metal base, and thus generally has a large thermal resistance and is mounted in one package. There is a limit on the number of chips that can be performed, in other words, the amount of heat or current capacity that can be tolerated in one package. Recently, in order to deal with such a problem and respond to a demand for a large capacity, a plurality of IGBT elements are incorporated in parallel into a flat package similar to the above-mentioned packages such as the GTO and the optical thyristor. A flat type semiconductor device having a multi-chip parallel type pressure contact structure in which an emitter electrode and a collector electrode formed in the above-described manner are brought into surface contact with a pair of external main electrode plates provided on the package side, respectively, and pulled out.

[0005] As a conventional technique relating to such a flat semiconductor device having a multi-chip parallel-type pressure contact structure, for example, the technique described in Fuji Tokiho Vol. 69, No. 5 (1996) and the like is known. This prior art relates to a flat IGBT package having a withstand voltage of 2.5 kV and a current capacity of 1 kA, on which 12 semiconductor chips (9 IGBTs and 3 diodes) are mounted. Further, as another conventional technique, for example, a technique described in Japanese Patent Application Laid-Open No. 7-94673 is known. This prior art includes five IGBTs and one IGBT.
The present invention relates to a flat IGBT package in which a plurality of diodes are arranged side by side.

FIG. 11 is a cross-sectional view showing a package structure of a flat type semiconductor device having a multi-chip parallel-type pressure contact structure according to the above-mentioned prior art, which will be described below. 11, reference numerals 1 and 2 denote semiconductor chips, 7 and 8 denote common electrode plates, 61 denotes an electrode substrate, 62 denotes a solder layer, 63 and 64 denote contact terminal bodies, 65 denotes a slit, 66 denotes a positioning guide, and 67 denotes a wiring. Stand. 68 is a wiring network, and 69 is wire bonding.

In the flat type semiconductor device according to the prior art shown in FIG. 11, a second main surface on the collector side of each of the semiconductor chips 1 and 2 is provided on a common electrode plate 8 of a package made of Cu or the like. Is connected via a solder layer 62 to a single electrode substrate 61 made of Mo.
The main surface has a structure in which it is connected to a common electrode plate 7 of a package of Cu via individual contact terminals 63 and 64 made of Mo separated for each semiconductor chip. The positioning of the semiconductor chips 1 and 2 in the package is performed by positioning guides 6 in slits 65 formed around the chip mounting area on the electrode substrate 61 described above.
6 is fitted and fixedly supported in a standing position in a predetermined position. That is, the positioning guide 6
6 functions as an outer frame guide, and the semiconductor chips 1, 2,.
Further, the contact terminal bodies 63 and 64 are held at fixed positions. Gate electrodes, which are control electrodes of the semiconductor chips 1 and 2, are connected by wire bonding 69 to a wiring network 68 on a wiring board 67 provided on a peripheral portion of an electrode substrate 61 to which a collector is connected. Further, the contact terminal body 63 is formed with a concave notch in order to avoid contact with a wire wire-bonded to the wiring network 68.

As another conventional technique relating to a flat semiconductor device having a multi-chip parallel type pressure contact structure, for example, a technique described in Japanese Patent Application Laid-Open No. 8-0824020 is known. This conventional technology is based on a flat type IG mounted with 21 semiconductor chips (9 IGBTs and 12 diodes).
It relates to a BT package.

FIG. 12 is a cross-sectional view showing an example of a package structure of a flat type semiconductor device having a multi-chip parallel type pressure contact structure according to the prior art, which will be described below. In FIG. 12, reference numeral 4 denotes a gate electrode portion (control electrode), and reference numeral 70 denotes a chip frame. 71 is an outer frame, 7
2 is a probe, 73 is a socket, 74 is a gate lead wire, 75 is a groove, and other reference numerals are the same as those in FIG.

In the flat type semiconductor device according to the prior art shown in FIG. 12, the second main surfaces on the collector sides of the semiconductor chips 1 and 2 are provided on a common electrode plate 8 of a package made of Cu. One electrode substrate 6 made of Mo
1 and the first main surface on the emitter side is connected to the common electrode plate 7 of the package made of Cu via the contact terminals 63 and 64 which also serve as pressure contact plates made of individual Mo separated for each chip. It has a structure. The positioning of the semiconductor chips 1 and 2 in the package is performed by mounting an individual chip frame 70 on the outer peripheral portion of each semiconductor chip 1 and 2 and abutting the chip frames to arrange the chips on the same plane. The position of each chip is finally determined by surrounding the outermost periphery of the chips arranged by the external frame 71. Each chip frame 70 enables the chip to be fixed and the contact terminals 63 and 64 as pressure contact plates to be fixed.
Makes the positional relationship of the gate electrode 4 accurate. The tip of a probe 72 is in contact with the gate electrode portion 4 of each of the semiconductor chips 1 and 2, and a gate lead wire 74 for each chip connected to the probe 72 by using a socket 73 is individually connected to the package outer peripheral portion. Wired. On the other hand, the press-contact surface on the inner side surface of the emitter-side electrode plate 7 has a groove 75 around a portion facing the semiconductor chip, which is a portion where the chips contact each other.
Are formed, and the plurality of gate leads 74 described above are arranged in the grooves 75.

According to the package structure of the flat type semiconductor device according to the prior art as described above, the connection of the main electrode is not a wire bond as compared with the module type package structure, so that the connection reliability is improved. Therefore, it is possible to reduce the inductance and resistance of the connection conductor and to cool the semiconductor chip from both sides, so that effects such as an increase in cooling efficiency can be expected.

[0012]

However, in the above-mentioned prior art, when the number of semiconductor chips connected in parallel to further increase the capacity is further increased, that is, the number of semiconductor elements mounted on the same package is reduced. In the case of a very large-capacity and large package ranging from tens to hundreds or more, due to the difference in thermal expansion due to the difference between the material of the positioning member and other component materials such as the common electrode and intermediate electrode, Accurate positioning of the semiconductor chip becomes difficult, and the number of gate wirings to be processed becomes very large, which causes a problem that processing of the gate wiring itself becomes difficult.

Further, in the above-mentioned prior art, when the number of semiconductor chips connected in parallel is further increased, problems such as generation of noise in a gate circuit due to wiring inductance cannot be ignored, and further, in order to meet the demand for high withstand voltage. When the withstand voltage of the chip is increased, heat is generally increased, which causes a problem that the influence of a displacement or the like due to a difference in thermal expansion between members constituting the package further affects severely.

Further, the prior art described with reference to FIG. 11 utilizes a frame component or the like for positioning each semiconductor chip, but has a problem that the mounting density is reduced by these members. I have.

As described above, in order to make the size of the flat type semiconductor device as compact as possible and to increase the power capacity to be handled, the mounting density of the built-in semiconductor elements is further improved, and a high breakdown voltage and a large current capacity are obtained. In addition, since a large number of individual parts are required for positioning and the number of parts is increased, it is necessary to improve assembling workability, parts cost, and the like. .

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, reduce the mounting cost, increase the mounting density of elements, reduce the size of semiconductor devices, improve assembly workability, A flat type semiconductor device capable of improving repairability, reliability, etc., and in particular, can position a super-multiple chip accurately, easily, and at low cost even in a large flat type package. It is another object of the present invention to provide a flat semiconductor device capable of simplifying the processing of gate signal wiring in a package and increasing reliability.

Another object of the present invention is to provide a highly reliable, inexpensive, and large-capacity power converter suitable for use in a large-capacity system using a flat semiconductor device obtained thereby. is there.

[0018]

According to the present invention, there is provided a flat package in which a pair of common electrode plates exposed on both sides are externally insulated by an insulating outer cylinder. In order to transmit a control signal from outside the package to each chip in a flat semiconductor device in which a plurality of semiconductor chips having one main electrode and control electrode and a second main electrode on a second main surface are juxtaposed and incorporated. The control signal wiring formed inside the flat type semiconductor device is composed of control signal wiring parts integrally molded with an insulating material, and the parts are mounted on a plurality of semiconductor chips or semiconductor chips mounted inside the flat type semiconductor device. This can be achieved by simultaneously providing a function of collectively determining the positions of a plurality of arranged intermediate electrodes in the package.

The object is to provide a function of collectively determining the position of the semiconductor chip or the intermediate electrode as described above by providing a large number of integrally formed projections on the insulating material of the control signal wiring component, and attaching this to the intermediate electrode. This is achieved by fitting into the formed through hole (or notch), whereby the position of each intermediate electrode and semiconductor chip can be easily positioned at a predetermined position with respect to the control signal wiring component. .

Another object of the present invention is to solve the problems of displacement and thermal stress caused by a difference in thermal expansion between a material of an insulating material as a positioning member and a material of another mounting component such as a common electrode and an intermediate electrode. To this end, the control signal wiring component in which the control signal wiring member and the insulating material are integrally formed, the wiring member is made of a material having a thermal expansion coefficient close to that of the common electrode member, and the insulating material is made of the wiring member. This is achieved by orienting a filler material having a low thermal expansion in a direction parallel to the above, thereby forming a resin, glass or ceramic composite material having a thermal expansion coefficient close to that of the control signal wiring member.

Further, the above object is achieved by dividing the insulating material of the control signal wiring component into a plurality of parts and integrating each of them with the wiring member, whereby the thermal expansion of the wiring member and the insulating material is achieved. The stress generated due to the difference can be greatly reduced, and the displacement caused by the difference in thermal expansion between the insulating material, which is the material of the positioning member, and other mounting component materials such as the common electrode and intermediate electrode, and the thermal stress The problem can be solved easily.

Further, the above object is achieved by forming the wiring member used for the control signal wiring component from a plate-like elastic metal body, thereby forming the control signal wiring component on the surface of the semiconductor chip from the wiring member. A function of applying a pressing force to the extracted extraction electrode for connection with the control electrode on the first main surface and holding a contact with the control electrode on the semiconductor chip can be provided, and the connection between the semiconductor chip and the wiring member can be provided. With a small number of components, a semiconductor device can be easily realized at low cost.

Further, the above object is attained by the fact that the insulating material itself integrated with the wiring member of the control signal wiring component has elasticity, whereby the first main surface formed on the surface of the semiconductor chip from the wiring member is provided. A pressurizing force is applied to the extraction electrode for connection with the control electrode, and a function of holding a contact with the control electrode on the semiconductor chip can be provided.

Further, the object is to accommodate the control signal wiring component in a groove formed in a common electrode of a package,
This is achieved by connecting an extraction electrode from the control electrode of each semiconductor chip to the semiconductor device, thereby reducing the size of the semiconductor device, improving the workability of assembly, improving the chip repairability,
Noise and the like in the gate circuit due to wiring inductance can be reduced.

Further, the above object is achieved by using a flat semiconductor device having the above-described configuration as a main conversion element in a power converter for converting AC to DC or DC to AC.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a flat semiconductor device and a power converter using the same according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a view for explaining a first structural example of a control signal wiring component constituting a flat semiconductor device according to one embodiment of the present invention, and FIG. 2 is a view illustrating the flat semiconductor device according to one embodiment of the present invention. FIG. 3 is an enlarged view for explaining the structure of the control signal wiring component in detail. 1 to 3, 3 is a flat semiconductor device, 5, 6, and 15 are intermediate electrodes,
9 is an insulating outer cylinder, 10 is a metal plate, 11 is a pull-out pin, 1
2, 17 are protrusions of the insulating member, 13 is a hole, 14 is a through hole, 1
6 is a non-through hole, 18 and 19 are grooves, 20 is a control signal wiring component, 21 is a control signal wiring member, 22 is a collective terminal, 23 is an insulating member, and 24 is an external lead-out terminal.
1, the same as in FIG.

First, the structure of the flat semiconductor device 3 according to one embodiment of the present invention will be described with reference to FIG. In the example shown here, an IGBT (hereinafter, referred to as the semiconductor chip 1) is used as the semiconductor chip 1.
This is an example of a reverse conduction type switching device incorporating a switching device using an IGBT chip 1) and a flywheel diode (FWD2) as a semiconductor chip 2 connected in anti-parallel to the switching device. FIG. 2 shows a cross section of the flat semiconductor device 3 from the rightmost end to the middle toward the center. The example shown in FIG. 2 has a structure in which the entire semiconductor device 3 is formed in a circular shape, and a large number of semiconductor chips forming IGBTs and FWDs are arranged inside the circle. Therefore, the common electrodes 7 and 8 are formed in a circular shape, and the outer cylinder 9 is also formed in a cylindrical shape.

In FIG. 2, an emitter electrode is provided on almost the entire first main surface on the upper surface side of the IGBT chip 1, and a second main surface on the lower surface side is provided.
A collector electrode is formed on the main surface.
A control electrode (gate electrode) 4 is formed at the center of the main surface. In the FWD 2, an anode electrode is formed on the upper surface of the chip, and a cathode electrode is formed on the lower surface. On each of these semiconductor chips, intermediate electrodes 5 and 6, which serve both as heat dissipation and electrical connection, are fixed to the main electrodes of the chip.
These are the first common electrode plate 7 (emitter electrode plate) and the second common electrode plate 7
Of the common electrode plate 8 (collector electrode plate). The pair of common electrode plates 7 and 8 are externally insulated by an insulating outer cylinder 9 made of ceramic or the like, and furthermore, a metal plate 10 connects between the common electrode plates 7 and 8 and the insulating outer cylinder 9. It has a hermetic structure in which the inside of the package is sealed and sealed. However, this hermetic structure is not necessarily required depending on the application.

Next, a method of forming a control signal wiring formed inside the flat type semiconductor device for transmitting a control signal from the outside of the package to each of a large number of semiconductor chips, and positioning the chip at a predetermined position in the package. The method will be described.

FIG. 1 shows an example of the control signal wiring component 20 for this purpose. The control signal wiring member 21 constituting the control signal wiring component 20 is integrally formed by etching, wire processing, or the like in a shape in which a plurality of control signal wirings to be formed inside the flat semiconductor device 3 are assembled in one component in advance. It is preferable to manufacture it. Then, the control signal wiring member 2
1 is integrally molded using a mold so as to cover the periphery of the control signal wiring member 21 by a method such as molding, potting or the like. As shown in FIG. 1, the shape of the control signal wiring component 20 had a circular control signal wiring member 21 having substantially the same size as the outer circumference of the circular common electrodes 7 and 8 described above. The control signal wiring member 2 has an outer periphery made of the whole garden material 23 and has a circular inside formed therein.
1 is formed in a rod shape and a plurality of insulating materials 23 are arranged in parallel.

As shown in FIG. 1, the control signal wiring component 20
Has a collective terminal 22 connected to a control signal wiring member 21 molded inside an insulating material 23. One end of the collective terminal 22 is connected to the insulating outer cylinder 9 as shown in FIG. It is connected to an external lead-out terminal 24 which is formed while maintaining airtightness. That is, a control signal from outside the package is transmitted to the control signal wiring member 21 formed inside the package via the collective terminal 22. Collective terminal 22
Of course, it is also possible to cover a part with the insulating material 21 to insulate it as described above. Further, the control signal wiring component 20 is provided with a projection 12 in which a hole 13 is formed in a part of an insulating material 23.

FIG. 3 is an enlarged view of a portion where the projection is formed. The protrusions 12 and the holes 13 are formed at a time when the insulating material 23 is formed, and the inside of the holes 13 is a hole having no insulating member up to the position of the control wiring member. At the time of mounting, a lead pin 11 for connecting a control wiring member 21 and an electric wiring is fitted into a pad of the control electrode 4 on the semiconductor chip 1 in a direction perpendicular to the chip main surface.
By using the control signal wiring component 20 having such a shape, there is no need to separately provide an insulating component for insulating the extraction pin from the intermediate electrode 6 and the common electrode 7, so that the assembly is simplified and the number of components is reduced. Reduction and cost reduction can be realized.

The incorporation of the semiconductor chip into the package is performed by fitting the above-mentioned lead-out pins 11 and the protrusions 12 of the insulating member 23 into the through holes 14 of the intermediate electrode 6, whereby each semiconductor chip is The position is determined at the position where the protrusion 12 of the insulating member 23 of the control signal wiring component 20 is formed. That is, in the flat semiconductor device 3 according to the embodiment of the present invention shown in FIGS. 1 to 3, the method for drawing wiring from the control electrode of each semiconductor chip to form wiring to the outside of the package is as follows. The structure also serves as a method for determining the position of each semiconductor chip in the plane within the device, and does not require new components for positioning.Therefore, the number of components is significantly reduced compared to the conventional technology. Can be reduced. In the illustrated embodiment, since positioning is not based on the outer shape of the semiconductor chip or the intermediate electrode, it is not necessary to arrange a member for that purpose between the chips. Can be.

Referring again to FIG. 2, a large number of parallel grooves 18 are formed on the inner surface of the package of the common electrode 7, and grooves 19 are also formed on the outer peripheral portion. The control signal wiring member 21 is built in the grooves 18 and 19 while being insulated from the common electrode 7 by the insulating material 23. Then, the pull-out pin 11 connected to the control signal wiring network 21
Are connected to the control electrode 4 of the semiconductor chip by being guided by the center hole 13 of the insulating member 12. As a result, according to the embodiment of the present invention, it is possible to form a compact gate wiring network with little waste built in the common electrode 7 of the package.

The outer dimensions of the intermediate electrode 6 provided on the first main surface side of each semiconductor chip are formed smaller than the outer dimensions of the semiconductor chip in order to avoid contact of the intermediate electrode 6 with the chip end of the planar breakdown voltage structure. ing. The intermediate electrode 6 arranged on the IGBT chip 1 having the control electrode has a round outer diameter, a through hole 14 in the center, and a chamfered edge. The intermediate electrode 6 is not limited to the above-described shape, and may be, for example, a shape in which a hole or a notch is provided at an eccentric position, and the outer shape 23 of the hole and the insulating member is also round. However, the shape is not limited to this, and may be square.

In the above-described embodiment of the present invention, the control electrode 4 and the lead-out pin 11 are not joined, and have a structure in which they come into contact and conduct. Thus, it is possible to avoid a problem such as deterioration of bonding due to a difference in thermal expansion between a control electrode or a semiconductor substrate on a chip and a material of a control wiring lead-out pin.

In general, when the temperature inside the package changes due to the operation of the semiconductor device or the like, a positional displacement (lateral displacement) between the components occurs due to a difference in thermal expansion coefficient between the components. For this reason, in a structure in which the control electrode and the extraction pin are not joined, there is generally a risk that the control wiring may be disconnected due to displacement. However, in the structure of the semiconductor device according to the present invention described above, the protrusion of the insulating material integrally formed with the control signal wiring moves together with the intermediate electrode 6 and the semiconductor chip 1, so that the relative position between the extraction pin and the semiconductor chip is reduced. There is no displacement. That is, the structure according to the embodiment of the present invention has a so-called self-alignment function.

Further, the structure of the semiconductor device according to the above-described embodiment of the present invention is such that the control electrode pad 4 provided on the semiconductor chip and the lead pin 11 disposed directly above the control electrode pad 4 serve as the central axis. And the position of the intermediate electrode. For this reason, the position change due to the thermal expansion of the individual semiconductor chip and the intermediate electrode occurs around this axis, and the mutual position between the control electrode pad and the lead pin on the center axis is definitely shifted. There is no.
Therefore, the semiconductor device according to the above-described embodiment of the present invention greatly improves the reliability of the connection between the control electrode pad and the lead pin, and particularly, the size of the mounted semiconductor chip is large, This is effective when the number of semiconductor chips is large or when the package size is large.

As described above, the IGBT chip 1 shown in FIG.
However, when the FWD chip 2 is described, a hole 16 that does not penetrate is formed in the intermediate electrode 15 disposed on the FWD chip 2, and the protrusion 12 formed on the control signal wiring component 20 is formed in this hole. The position of each intermediate electrode 15 and the FWD chip 2 which is a semiconductor chip is determined. The above-described hole formed in the intermediate electrode 15 may be used as a through hole to share the IGBT chip 1 and the intermediate electrode component. Also, the insulating member projections 12
A pin having no pin hole at the center may be used. Also, FWD
The chip 2 is not at the outermost periphery of the semiconductor device formed in a circular shape, and the position of the FWD chip 2 is an IGBT surrounding the periphery.
If it is almost determined by the chip 1, the FWD chip 2
With respect to the above, it is also possible not to perform the positioning using the insulating member 12 as described above. As a result, it is possible to reduce the processing cost, the number of parts, and the like of the components constituting the semiconductor device.

FIG. 4 is a view for explaining a second structural example of the control signal wiring component constituting the flat semiconductor device according to one embodiment of the present invention, and the reference numerals in FIG. 4 are the same as those in FIG.
The second example of the structure of the control signal wiring component shown in FIG. 4 is an example in which the insulating member is divided into a plurality of parts and integrally molded to reduce the difference in thermal expansion.

If the common electrode and the control signal wiring component according to the present invention have different coefficients of thermal expansion, when the temperature changes inside the package due to the operation of the semiconductor device or the like, they may be displaced from each other (lateral displacement). become. Even if the same material or a material of the same system is selected as the material used for the common electrode and the wiring member 21 constituting the control signal wiring component, and the thermal expansion coefficient is approximated, the same material is used. If the thermal expansion coefficient of the integrally formed insulating member 23 is significantly different from that of the wiring member 21, the average thermal expansion coefficient of the control signal wiring component 20 is significantly different from that of the common electrode. In the example shown in FIG. 4, as a measure to prevent this, the insulating material 23 is divided into several small parts, each of which is formed integrally with the control signal wiring member 21. With such a structure, the distance that the insulating material 23 is continuously connected is reduced, so that the influence of the insulating material 23 on the average thermal expansion coefficient of the control signal wiring component 20 can be reduced,
As a result, the average thermal expansion coefficient of the control signal wiring component 20 can be approximated to that of the common electrode.

As another countermeasure, the insulating member 23 constituting the control signal wiring component is made of a composite material of resin, glass and ceramic with a low thermal expansion filler material oriented in a direction parallel to the control signal wiring 21. It is also possible.
Thereby, the thermal expansion coefficient of the insulating member can be adjusted, and the average thermal expansion coefficient of the control signal wiring component 20 can be approximated to the common electrode.

FIG. 5 is a view for explaining an example of a typical shape of a control signal wiring member 21 constituting a control signal wiring component and a collective terminal 22 connected to the control signal wiring member and led out of the semiconductor device. The reference numerals in the figure are the same as those in FIG. 5 (a), 5 (b) and 5 (c) show examples of the wiring member shape of the control signal wiring component built in the grooves 18 and 19 of the common electrode described with reference to FIG. 2, and FIG. 13 shows another example of the shape of the control signal wiring member. When using these control signal wiring components, it is preferable to form grooves corresponding to the respective shapes in the common electrode.

The example shown in FIGS. 5A and 5B has a structure in which the control signal wiring members 21 are integrally connected at the outer peripheral portion. ,
The effect that this outer peripheral portion can stabilize the shape of the control signal wiring component can be obtained. In the example shown in FIG. 5 (c), the control signal wiring member 21 is formed only on a part of the outer peripheral portion. It is also possible to form a part of the control signal wiring component and to have a structure in which only the insulating member of the control signal wiring component is integrally connected at the outer peripheral portion. Further, as in the case described above, the effect of stabilizing the shape of the control signal wiring component can be realized. Further, the example shown in FIG. 5D is an example in which the external shape of the semiconductor device described with reference to FIG. 2 is configured to be a rectangle, and the control signal wiring member 21 is formed in a shape according to the rectangle. 5 (a) and FIG.
The same effect as in the case of the example shown in (b) can be obtained.

The collective terminal 22 may be formed of the same material as the control signal wiring member, or the thickness of the wiring may be changed.
By changing the material or the like, another component may be joined and integrated with the control signal wiring member.

The control signal wiring members 21 and 22 are
It can be made by etching, wire processing, etc., punched out of a thin metal plate and made all at once, or can be made by joining several parts.

In the case where the insulating member 23 constituting the above-mentioned control signal wiring component is formed of an organic material, it is simplest to integrally mold it with the wiring member, and it is relatively easy to form an arbitrary shape. There is an advantage that it can be easily formed.

As a characteristic required for the resin-based material, it is desirable that the tracking resistance (CTI value) is 400 V or more, more preferably 600 V or more. In addition, it is preferable to use a UL94V-0 level flame retardant. As the thermomechanical properties, it is preferable to use a material system having high mechanical strength and fracture toughness, and a material system whose thermal expansion coefficient can be adjusted to another mounting material and an optimum value determined in consideration of the mounting form. .

Specific materials include epoxy-based, phenol-based, polyester-based thermosetting resins, or
It is preferable to use a silicone-based or fluorine-based elastomer. In addition, polyphenylene sulfide (PP
S), an engineering plastic thermoplastic resin such as an aromatic polyamide and a thermoplastic polyimide can also be used. In addition, curing agents, catalysts, pigments, and additives can be used as needed for improving / retaining properties. Furthermore, those obtained by compounding various filler materials (fillers) with these materials can also be used. For example, compounding a low thermal expansion inorganic material powder such as crystalline or non-crystalline silica powder, alumina powder, or compounding by orienting an anisotropic material (fibrous, plate-like, etc.) as a filler. Can be done. Thereby, since the thermal expansion coefficient of the composite material of the resin and the powder can be freely adjusted, the control signal wiring component itself,
Further, it is possible to improve the reliability of the package on which the package is mounted with respect to the temperature cycle.

In general, the above-mentioned inorganic filler is preferably contained in a volume of about 60% or more of the whole resin composition, and particularly preferably in the range of 7% by weight to 9% by weight. Further, by increasing the amount of the inorganic filler, it is possible to reduce the amount of water absorption and improve the resin strength. Further, in addition to the additives, the epoxy resin composition may contain a rubber component such as a silicone oil, a silicone rubber, or a synthetic rubber to reduce stress, or to improve hydro-resisting reliability for the purpose of improving moisture resistance reliability. May be blended.

As a method of manufacturing a resin part, potting,
Injection molding, transfer molding, compression molding, powder sintering molding and other methods can be used,
The optimum method may be selected according to the material and the mounting method.
In particular, in order to perform integral molding using potting,
It is preferable to use an elastomer made of silicone, urethane, polystyrene, polybutadiene or the like and a copolymer thereof, or a thermosetting material such as epoxy or phenol resin. To improve workability such as flowability, low-temperature curing property, defoaming property, low thixotropy, mold release property when molding using a mold, low thermal expansion, low content of impurity ions, etc. The most suitable resin or composite resin can be selected for the requirements. It is also possible to reduce the stress by using silicone rubber or silicone-modified resin to improve the thermal shock resistance.

Insulating member 23 constituting control signal wiring component
Of course, it is also possible to use a thermoplastic resin as a material, and as the material, use thermoplastic polyimide, aromatic polyamide, polyamideimide resin, polyetheretherketone (PEEK), PPO, PPS, liquid crystal polymer and the like. be able to. However, these materials need to be heated and melted and injected, and care must be taken when handling them.

As a material for the insulating member 23, besides a thermosetting resin, an active energy ray-curable resin that is cured with an active energy ray such as an ultraviolet curable resin or an electron beam curable resin can be used. It can be used depending on the use of the device, process conditions, and the like. A typical composition of the active energy ray-curable resin includes an alkyd resin having an unsaturated group such as an acrylic acid group, an allyl group, an itaconic acid group and a conjugated double bond, an acrylic resin, a urethane resin,
Examples thereof include a polyurethane resin and an epoxy resin.

In the semiconductor device according to the embodiment of the present invention described with reference to FIG. 2, it is necessary to reduce the thickness of the wiring material and the insulating material incorporated in the common electrode and the thickness of the groove provided in the common electrode to reduce the entire electrode area. , The area of the groove in the electrode volume,
This is preferable because the volume of the groove can be reduced to reduce the thermal resistance. In the embodiment of the present invention, for example, since a large number of individually covered gate lead wires are not provided in one groove, the groove provided in the common electrode can be narrowed. Further, according to the embodiment of the present invention, since wire bonding is not used for forming the wiring, it is not necessary to secure a space area for wire bonding, and a groove for the wire bonding can be made unnecessary. The semiconductor chips can be mounted at high density by filling the gaps between the chips without restriction.

Further, according to the embodiment of the present invention, since the control electrode wiring is a built-in control electrode wiring in the common electrode,
The effect of being less affected by the main circuit wiring (main circuit current and voltage) can also be obtained. That is, since a large current flows through the main circuit wiring and the voltage changes by several thousand volts, noise may jump into the control electrode wiring by magnetic or electrostatic induction from the main circuit wiring. This noise changes the current of the control electrode wiring, and causes a problem that the current is concentrated only on a specific chip and the chip may be destroyed. The structure of the semiconductor device according to the above-described embodiment of the present invention is such that the control electrode wiring network is disposed at right angles to the main circuit, and the control electrode wiring network is embedded in the emitter electrode having a constant potential. As a result, the emitter electrode exerts a shielding effect, thereby preventing an electrical influence on the control electrode wiring due to a potential change of the collector electrode.

FIGS. 6 to 8 are diagrams illustrating an example of a detailed structure of a portion where a control signal wiring is formed, and are all cross-sectional views parallel to a control signal wiring member formed on a common electrode.
In FIG. 6, 25 is a bonding layer, 26 is a pressing force, 27
Is an insulating member, 28 and 33 are extraction pins, 31 is a solder layer, and 32 is an auxiliary frame.

FIG. 6 shows an example in which intermediate electrode plates 5 and 6 are inserted between IGBT chip 1 and common electrode plates 7 and 8. In this example, the intermediate electrode plates 5 and 6 include:
Au plating is applied in advance, and the Al electrode on the emitter side and the Au electrode on the collector side of the IGBT chip 1 are bonded to the intermediate electrode plates 5 and 6 by the bonding layer 25 mainly composed of Au. Drawer pin 1 with adjusted length
Numeral 1 is kept perpendicular to the semiconductor chip via the insulating member projections 12 and further pressed against a control signal wiring member 21 built in the groove 18 of the common electrode 7. The insulating member 23 is formed of a resin having heat resistance and elasticity as described above, and is elastically deformed when the pull-out pin 11 is pressed, and the restoring force is controlled on the semiconductor chip via the pull-out pin 11. The pressing force 26 of the electrode 4 against the pad is applied. This makes it possible to maintain a good contact state between the tip of the extraction pin 11 and the control electrode 4.

The example shown in FIG. 7 is another structural example in which a pulling force is applied to the lead pin 11 against a control electrode on a semiconductor chip. In this example, the control signal wiring member 21
Has a high yield point such as phosphor bronze, nickel silver, beryllium copper,
It is manufactured using a metal material that has high fatigue strength and is unlikely to cause fatigue deformation. As the insulating member 23, a hard heat-resistant resin is used, and the insulating member 23 is removed only at a portion corresponding to the position of the drawer pin. Thus, the control signal wiring member 21 is configured to bend at the position of the extraction pin 11. When the drawer pin 11 is pressed against this portion, the wiring is bent and a restoring force is generated. The example shown in FIG. 7 has a structure in which the contact of the extraction pin 11 with the control electrode 4 is maintained by using a pressing force 26 that presses the extraction pin 11 downward.

The example shown in FIG.
The semiconductor chip 1 and the emitter-side intermediate electrode plate 6 are not joined together, while the semiconductor chip 1 and the emitter-side intermediate electrode plate 6 are joined together. Therefore, in this example, the relative position between the semiconductor chip 1 or the intermediate electrode plate 5 and the intermediate electrode plate 6 on the emitter side is determined by fixing using the auxiliary frame 32 made of a heat-resistant resin such as Teflon or silicone. . Thus, the relative position between the extraction pin 11 and the semiconductor chip 1 can be maintained without change.

Even when the auxiliary frame 32 is used as in the example shown in FIG. 7 described above, since the external dimensions of the auxiliary frame 32 do not require precision, the thickness of the auxiliary frame 32 can be reduced.
Since the processing can be simplified, the cost of parts can be reduced. The auxiliary frame 32 can also have a role of strengthening insulation protection and mechanical protection of the terminal portion of the semiconductor chip 1. If the purpose is only insulation reinforcement, the auxiliary frame 32
For example, a member having a structure similar to the auxiliary frame 32 having a looser dimensional accuracy or a plate-shaped member can be used. It is also effective to cover the end and side surfaces of the semiconductor chip with an adhesive such as silicone or polyimide instead of the auxiliary frame 32.

The example shown in FIG. 8 is another structural example in which a pressing force is applied to a control electrode on a semiconductor chip by a method of imparting elasticity to the extraction pin 11 itself. In this example, a small spring is built in the lead pin 11 for drawing a wiring from the control electrode 4 on the semiconductor chip 1 and has a vertical spring property. The length of the lead-out pin 11 is adjusted in advance so as to be slightly longer than the distance (including variation) between the control electrode 4 and the control electrode wiring member 21 when the semiconductor chip 1 is incorporated in a package. . Therefore, in the example shown in FIG. 8, the pull-out pin 11 is held vertically to the semiconductor chip via the projecting portion 12 of the insulating member, and the control signal wiring member 21 embedded in the groove 18 of the common electrode 7. Is pressed against the pad 11, the pin 11 itself generates a pressing force 26 of the control electrode 4 against the pad, so that the contact state between the pin 11 and the control electrode 4 can be kept good.

In the example shown in FIG. 8, between the Al electrode on the emitter side of the semiconductor chip 1 and the intermediate electrode plate 6 on the emitter side previously plated with Ag, an adhesive layer 25 mainly composed of Ag is used. Joined. On the collector side of the semiconductor chip 1, an Ag electrode is formed on the surface, and is joined via a solder layer 31 to the intermediate electrode plate 5 on the collector side, which has been previously plated with Ni.

In a semiconductor device, when the size of the package becomes very large, the resistance value variation of the control signal wiring to each semiconductor chip formed in the package becomes large. In order to equalize the operation of a very large number of semiconductor chips connected in parallel, the resistance value of the control signal wiring to each semiconductor chip must be reduced by the resistance value of the resistor individually arranged for each semiconductor chip. It is preferable to set it to 1/10 or less. In the above-described embodiment of the present invention, the control signal wiring is configured as described above, so that the variation of the gate resistance from the gate input terminal to each semiconductor chip can be made 10% or less, and the accuracy of circuit design can be improved. The circuit can be manufactured inexpensively by relaxation.

It is not essential that an intermediate electrode is interposed between the first and second common electrode plates and the semiconductor chip as in the above-described embodiment of the present invention. When it is necessary to reduce the generated stress based on the difference in thermal expansion between the two materials, a material with an intermediate thermal expansion coefficient between the two members, or a material having a thermal expansion coefficient closer to that of the semiconductor chip, and having excellent thermal conductivity and conductivity Preferably, an intermediate electrode is provided. As such a material, a simple metal such as tungsten (W) or molybdenum (Mo), or Cu-
W, Ag-W, Cu-Mo, Ag-Mo, Cu-FeN
i or other composite material or alloy, and further, a composite material of metal and ceramics or carbon, for example, Cu / SiC, C
u / C, Al / SiC, Al / AlN, etc. can be used. On the other hand, as the common electrode, copper or aluminum having good electrical conductivity and thermal conductivity, or an alloy or a composite material containing them, as described above, can be used.

As described above, it is simplest to form the through-hole in the center of the intermediate electrode to provide the control wiring lead-out portion provided on the emitter-side intermediate electrode. Depending on the position, shape, and number of pads, the position of the through hole may be decentered, the through hole may be formed in a notch shape or a rectangular shape at the end of the electrode, or a plurality of holes may be formed. The outer shape of the intermediate electrode is round, square,
Any structure may be used, but it is preferable that the intermediate electrode provided on the emitter side has a structure capable of avoiding contact with the withstand voltage structure formed at the end of the chip. In addition, a structure that can avoid contact with the control electrode part is required, and the shape of the surface in contact with the semiconductor chip is not only a ring shape, but also a comb-like shape, a single-tooth shape, a dice-like shape, etc. of the emitter electrode pad. It is preferable to use one that matches the position, shape, and number. On the other hand, it is preferable that the collector side has a structure that is planar and can contact the collector electrode as widely as possible. Furthermore, as for these intermediate electrodes, individual intermediate electrodes may be arranged for each semiconductor chip as in the embodiment of the present invention described above, or a single large intermediate electrode plate may be used. Good.

In the above-described embodiment of the present invention, the positions of the control electrode pads formed on the main surface of the semiconductor chip are all formed at the center of the chip. The number of pads may be two or more, not limited to one. Except for the pad of the control electrode on the first main surface of the semiconductor chip and the terminal end of the chip, it is a connection portion of the first main electrode (emitter electrode), and an electrode of Al or AlSi is formed. Further, an electrode or the like for detecting an overcurrent may be formed on the first main surface of the chip in addition to the control electrode. It is desirable that the region other than the region of the control electrode and the emitter electrode on the first main surface of the semiconductor chip is covered with, for example, a passivation film of polyimide.

The outer shape of the common electrode plate or the package can be a round semiconductor device in addition to a round semiconductor device.
In this case, the insulating outer cylinder is also preferably square. A quadrangular semiconductor device is preferable when the chip itself is square and the number of mounted semiconductor chips is small because the whole can be made more compact than a circle. However, if the number of semiconductor chips to be mounted is very large, even if the package has a round shape, the area loss of the package will be small, so if the shape is selected from other factors such as the manufacturing cost of the packaging material, Good.

The flat semiconductor device in which a large number of semiconductor chips are connected in parallel as described above has a problem in that, when there is an unbonded portion at the interface between the built-in semiconductor chip, the intermediate electrode, and the common electrode, It is preferable to press the two members exposed from the outside of the plate and pressurize the plate so that the above-mentioned members are in good contact with each other. In this case, a round package is more preferable because it can be pressed uniformly.

Generally, when the withstand voltage of the IGBT element is increased, the loss of the element increases, and the heat generation during operation increases, so that the current density cannot be increased much. Therefore,
In particular, when a semiconductor device with a high withstand voltage and a large current is required, the number of chips connected in parallel needs to be very large. The embodiment of the present invention described above is particularly suitable for such a requirement, and the wiring processing inside the package can be made compact and the thermal resistance can be reduced.

On the other hand, in order to reduce the number of mounting steps and costs, it is desirable to reduce the number of mounted chips as much as possible, that is, it is desirable that the size of the semiconductor chip be as large as possible within the range of the cost of the semiconductor chip. In the case of a reverse conduction type flat semiconductor device, if the FWD element and the IGBT element are designed to have the same size, the arrangement can be freely selected. Therefore, the degree of freedom of the number distribution ratio of the semiconductor chips is increased, which is combined with the high-density arrangement. Thus, elements having various ratings can be easily provided. The mounting structure according to the embodiment of the present invention includes:
Basically, it has a structure that can flexibly cope with a change in the type of chip irrespective of the presence or absence of the control electrode, so that it is possible to relatively easily cope with the above-described change. Where I
In the arrangement of the GBT and the FWD in the package, it is preferable to arrange the chips of the same type as evenly as possible in order to equalize the heat generation points.

The mounting structure according to the embodiment of the present invention described above is, of course, an IGBT not including a diode.
It can also be used for flat semiconductor devices consisting only of switching semiconductors, etc. In addition, for example, a large number of diode chips alone can be positioned and mounted in a flat package by the above-described method to increase the capacity. It can also be applied to achieve

In the above-described embodiment of the present invention, an IGBT is used as a semiconductor device with a control electrode. However, the present invention provides at least a first main electrode on at least a first main surface.
The present invention can be applied to all semiconductor devices having a second main electrode on a second main surface, and includes an insulated gate transistor (MOS transistor) other than an IGBT and an IGCT (Insulated Ga transistor).
The present invention can be similarly applied to a semiconductor element with a control electrode such as an insulated gate thyristor (MOS controlled thyristor) such as a te Controlled Thyristor) and a diode.

Since the flat semiconductor device according to the above-described embodiment of the present invention can mount an extremely large number of semiconductor chips at high density, the use of the flat semiconductor device greatly increases the volume and cost of the power converter. Thus, a large-capacity power converter can be realized.

FIGS. 9 and 10 are diagrams showing an example of a circuit configuration of a power converter using the flat semiconductor device according to the present invention as a main conversion element. In these configuration examples, a package in which an IGBT chip and a diode chip are packaged is used as a semiconductor chip included in the flat semiconductor device. 9 and 10, 76 is an IGBT, 77 is a diode, and 78 is a snubber circuit.

The example shown in FIG. 9 shows a circuit configuration for one bridge of a power converter having a three-phase configuration. An IGBT 76 serving as a main conversion element and a diode 77 are arranged in anti-parallel. One arm is constituted by being connected in series. The IGBT 76 and the diode 77 are flat semiconductor devices in which a number of semiconductor chips according to the embodiment of the present invention described above are mounted in parallel. When a flat semiconductor device using a reverse conducting IGBT is used as in the circuit example shown in FIG. 9, the IGBT 76 and the diode 77 in the figure are collectively housed in one package.
In the illustrated circuit example, the IGBT 76 and the diode 77
A snubber circuit 78 is connected to the anti-parallel circuit, and a current limiting circuit and a smoothing capacitor are provided for the entire circuit. FIG. 10 shows a configuration of a self-excited power converter in which the three-phase bridge shown in FIG. 9 is configured by multiplexing four.

The flat semiconductor device according to the embodiment of the present invention is mounted in a so-called stack structure in which a plurality of the flat semiconductor devices are connected in series with a water-cooled electrode interposed therebetween so as to make surface contact with the outside of the main electrode plate. Pressurized. One arm of the power converter shown in FIG. 9 described above can be configured by using a flat semiconductor device mounted on such a stack structure.

The flat type semiconductor device according to the embodiment of the present invention is not limited to the above-described example, and is used for a self-excited large-capacity power converter used in a power system and a large-capacity power converter used as a mill power converter. It is also particularly suitable for use in variable-speed pumped-storage power generation, substation facilities in buildings, substation facilities for railways, sodium-sulfur (NaS) battery systems, and power converters for vehicles and the like.

According to the above-described embodiment of the present invention, in a flat semiconductor device in which a plurality of semiconductor chips are juxtaposed, a wiring for a control signal which is indispensable for controlling the operation of each semiconductor chip is formed. Is a self-aligned structure having the function of always aligning the position of the control electrode on the semiconductor chip at the same time and positioning each semiconductor chip in the package. In addition, it is possible to prevent the occurrence of a problem caused by a mutual displacement between different members due to a difference in thermal expansion or the like, a problem caused by stress between the members, etc., and further, it is possible to improve a mounting density by reducing the space between semiconductor chips.

Further, the flat type semiconductor device according to the embodiment of the present invention has a structure in which an integrated control signal wiring component is built in the common electrode, so that control signal wiring processing can be greatly simplified. In addition, it is possible to cope with a case where a very large number of semiconductor chips need to be mounted, and it is possible to dramatically improve the assembling workability and the reliability as a package. Further, according to the embodiment of the present invention, since the package can be made thin and compact, the thermal resistance can be reduced, and the control signal wiring is configured to be hardly affected by the main circuit wiring. Therefore, the influence of noise on the gate wiring can be reduced.

According to the embodiment of the present invention, it is possible to realize a flat semiconductor device capable of connecting super-multiple chips in parallel, so that the rated voltage is 3.5 kV and the rated current is 1 kA or more. A large-capacity semiconductor device of 3 kA or more can be realized. Furthermore, large-capacity power converters using these semiconductor devices can significantly reduce the converter volume and cost while ensuring element reliability, and make the power converter compact. As a result, the inductance of the DC wiring can be significantly reduced, and the voltage utilization of the element can be improved.

[0082]

As described above, according to the present invention, the mounting cost of a flat type semiconductor device is reduced, the mounting density of elements is increased, the size of the semiconductor device is reduced, and the workability of assembly is improved. It is possible to improve chip repairability and reliability, and to position the super-multiple chips accurately and easily. In addition, using this flat type semiconductor device, high reliability suitable for use in a large capacity system,
An inexpensive and large-capacity power converter can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first structural example of a control signal wiring component included in a flat semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a structure of a flat semiconductor device according to one embodiment of the present invention.

FIG. 3 is an enlarged view illustrating the structure of a control signal wiring component in detail.

FIG. 4 is a diagram illustrating a second structural example of a control signal wiring component included in the flat semiconductor device according to the embodiment of the present invention.

FIG. 5 is a view for explaining an example of a typical shape of a control signal wiring member constituting a control signal wiring component and a collective terminal connected to the control signal wiring member and led out of a semiconductor device.

FIG. 6 is a diagram for describing a detailed structural example (part 1) of a portion where a control signal wiring is formed.

FIG. 7 is a view for explaining a detailed structural example (part 2) of a portion for forming a control signal wiring;

FIG. 8 is a diagram illustrating a detailed structure example (part 3) of a portion where a control signal wiring is formed.

FIG. 9 is a diagram showing a circuit configuration example of a power converter using a flat semiconductor device according to the present invention as a main conversion element.

FIG. 10 is a diagram showing a circuit configuration of a self-excited converter in which four three-phase bridges are multiplexed.

FIG. 11 is a cross-sectional view showing a package structure of a flat semiconductor device having a multi-chip parallel type pressure contact structure according to the related art.

FIG. 12 is a cross-sectional view showing another example of a package structure of a flat semiconductor device having a multi-chip parallel type pressure contact structure according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 2 Semiconductor chip 3 Flat semiconductor device 4 Gate electrode part (control electrode) 5, 6, 15 Intermediate electrode 7, 8 Common electrode plate 9 Insulated outer cylinder 10 Metal plate 11 Leader pin 12, 17 Insulating member protrusion 13 Hole Reference Signs List 14 through hole 16 non-through hole 18, 19 groove 20 control signal wiring component 21 control signal wiring member 22 collective terminal 23 insulating member 24 external lead-out terminal 25 bonding layer 26 pressing force 31 solder layer 32 auxiliary frame 61 electrode substrate 62 solder layer 63, 64 Contact terminal body 65 Slit 66 Positioning guide 67 Wiring board 68 Wiring network 69 Wire bonding 70 Chip frame 71 External frame 72 Probe 73 Socket 74 Gate lead wire 75 Groove 76 IGBT 77 Diode 78 Snubber circuit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mamoru Sawahata 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 5F047 JA01 JA03 JA05 JA06 JA10 JA11 JA12 JA14 JA15 JB00 JB03 JB11 JC00

Claims (11)

[Claims] A first main electrode and a control electrode on a first main surface, and a first main electrode and a control electrode on a second main surface in a flat package in which a pair of common electrode plates exposed on both surfaces are externally insulated by an insulating outer cylinder. In a flat semiconductor device in which a plurality of semiconductor chips having a second main electrode are juxtaposed and incorporated, a control signal from outside the flat package is transmitted to each of the plurality of semiconductor chips, and A flat semiconductor device comprising a control signal wiring component in which a wiring member having a function of collectively determining the positions of individual semiconductor chips in a package and an insulating material are integrally formed. 2. A flat package in which a pair of common electrode plates exposed on both sides are externally insulated by an insulating outer cylinder, a first main electrode and a control electrode on a first main surface, and a second main surface on a second main surface. A plurality of semiconductor chips having a second main electrode are juxtaposed and incorporated, and conductive and conductive layers are provided on at least the first main electrode side between each main electrode of the plurality of semiconductor chips and a common electrode plate opposed thereto. In a flat semiconductor device having an intermediate electrode also serving as a heat radiator, a control signal from the outside of the flat package is transmitted to each of the plurality of semiconductor chips, and within the package of the plurality of semiconductor chips. A flat semiconductor device comprising a control signal wiring component in which a wiring member having a function of collectively determining the position and an insulating material are integrally formed. 3. The flat panel according to claim 1, wherein a projection integrally formed on an insulating material of the control signal wiring component is provided for positioning the semiconductor chip or the intermediate electrode. Type semiconductor device. 4. The control signal wiring component, wherein the control signal wiring and the insulating material are integrally formed, the insulating material of the control signal wiring component is made of resin, glass, or a resin having a low thermal expansion filler material oriented in a direction parallel to the wiring member. 4. The flat semiconductor device according to claim 1, wherein the flat semiconductor device is a ceramic composite material. 5. The control signal wiring component according to claim 1, wherein the insulating material is divided into a plurality of parts, and each of the divided insulating materials is integrated with the signal wiring material. 2. The flat semiconductor device according to 1. 6. A first wiring member used for the control signal wiring component is formed of a plate-like elastic metal body, and the wiring member is formed on the surface of the semiconductor chip from the control signal wiring.
6. A function for holding a contact with a control electrode on the semiconductor chip by applying a pressing force to an extraction electrode for connection with the control electrode on the main surface. 2. The flat semiconductor device according to 1. 7. An insulating material for the control signal wiring component has elasticity, and the insulating material serves as a lead electrode for connection with the control electrode on the first main surface formed on the surface of the semiconductor chip from the control signal wiring. 6. The flat semiconductor device according to claim 1, wherein the flat semiconductor device has a function of holding a contact with a control electrode on the semiconductor chip by applying a pressing force. 8. The lead electrode for connecting a wiring member of the control signal wiring component to a control electrode of each semiconductor chip is a pin having a spring. Flat semiconductor device. 9. The control signal wiring component is housed in a groove formed in a common electrode plate facing the first main surface side of the plurality of semiconductor chips. 8. The flat type semiconductor device according to any one of items 1 to 7. 10. The semiconductor device according to claim 2, wherein at least one of the main electrodes of the plurality of semiconductor chips is joined to an intermediate electrode plate facing the main electrode. Flat semiconductor device. 11. A power converter for converting alternating current into direct current or direct current into alternating current, wherein the flat semiconductor device according to claim 1 is used as a main conversion element. Power converter.