JP2001223597A - Interleaver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interleaver that can read data without the need for an address conversion circuit. SOLUTION: The multi-stage interleaver is provided with two RAMs 31, 32 as storage elements to which data are written. Furthermore, an S/P conversion circuit 11 converts serial data into parallel data whose number is equal to number of columns C of a matrix to write the data to the two RAMs 31, 32. In this case, since the serial data whose interleave length is K are written in the 1st and 2nd RAMs 31, 32 with the same matrix arrangement of the interleave matrix, address conversion required to read data is not needed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave device used for communication.

[0002]

2. Description of the Related Art
In the MA transmission system, an error correction code is indispensable to keep the transmission bit error rate low. Conventionally, convolutional coding and Viterbi decoding have been used. The decoding method of the convolutional code is effective for random errors. Here, interleaving is performed for adaptation when a burst error occurs. This is because if a signal is interleaved and transmitted, even if a burst error is added, decoding can be performed as a random error by performing deinterleaving.

Conventionally, interleaving has been employed in which writing is performed for each row of a matrix and reading is performed for each column. However, when a periodic error occurs, deinterleaving may result in a burst error. Therefore, in order to further scatter the data, multi-stage interleaving in which rearrangement is performed twice has been proposed.

The operation of this multi-stage interleaver will be described with reference to FIG.

First, the interleave size K is given, and the number of columns C of the matrix is selectively given. In this example, C = 4. The number of rows R in the matrix is K
It is determined by the minimum number satisfying ≦ R × C. In this case, the number L of blank bits (shown by oblique lines in FIG. 8) of the matrix is L =
It becomes R × CK. The number of the bit in the matrix indicates the order of the input data bit. Hereinafter, the bit numbers will be described as “bit numbers”.

In this multi-stage interleaver, data is written in a matrix (R × C) for each row.
And 1st stage interleave (1stIL)
Then, in-row interleaving is performed, and data is read out from the matrix for each column by 2nd stage interleaving (2ndIL). Since blank bits in the matrix are omitted and read, the bits are obtained and puncturing is performed. By doing so, multi-stage interleaving in which rearrangement is performed twice can be performed.

FIG. 9 shows a configuration of the above-described multi-stage interleaver studied by the present inventors. In this example, a RAM is used as a storage element for writing and reading data, and the number of bits is eight. Also, the number of columns C of the interleave matrix
Is variable depending on the data transmission speed, etc., but will be described below by taking a case where the number of columns C = 4 as an example.

First, serial input data is converted by a serial / parallel conversion circuit (S / P conversion circuit) 10 into 8
It is converted to bit parallel data. This parallel data is stored in the RAM 3 by the input address generation circuit 20.
0 is sequentially written for each row. In this case, the number of data bits of the RAM 30 is 8, and the number of columns C of the interleave matrix is
Is different from 4 bits, but as shown in FIG.
M30 is input so as to be completely filled with data.

Next, data is read from the RAM 30.
This reading is performed by the output address generation circuit 40. The output address generation circuit 40 calculates a bit number to be read, converts the bit number into a row number and a column number by the address conversion circuit 46, and converts the data in the RAM 30 specified by the row number and the column number. read out. The calculation of the bit number is performed by considering an interleave matrix.

Here, 2nd interleaving is performed by reading out the matrix from the matrix for each column. The row counter 41 is used to read the first column of the matrix in order from the first row. When the reading of the first column of the matrix is completed, that is, when the row counter 41 counts up to the last row R, the row counter 41 outputs a carry. The column counter 42 counts the carry. Therefore,
The output of the row counter 41 and the output of the column counter 42 specify which row and column in the matrix.

The first interleaving is performed by changing the order of the columns of the matrix. This behavior is
This is performed by the mapping circuit 43. The mapping circuit 43 is provided with a selection circuit for selecting an interleave pattern corresponding to the number of columns C, that is, a pattern such as which column is to be moved to which column. According to the pattern, the column of the matrix to be read is determined. Therefore, the mapping circuit 43
Output specifies the columns of the matrix to be read after the first interleave.

The output of the row counter 41 is bit-shifted by a shifter 44 according to the number of columns C. In particular,
When the number of columns C is 2 ⁿ , the output of the row counter 41 is shifted by n bits. In the case of the above example, since the number of columns C is 4, it is shifted by 2 bits. If the row counter 41 counts from 0 and the column counter 42 counts from 1, the output of the shifter 44 and the mapping circuit 4
By adding the sum of the outputs of 3 with the adder 45, the bit number to be read can be obtained. For example, consider a bit number "5" in an interleaved matrix, which is in the second row and first column. In this case, the output of the row counter 41 is 1 and the output of the column counter 42 is 1. At this time, the output of the shifter 44 is 1
Is shifted by 2 bits to become 4. The output of the mapping circuit 43 is 1 unless the first column is replaced by the first interleave. Therefore, shifter 4
When the output of 4 and the output of the mapping circuit 43 are added, the result becomes 5, which indicates the bit number. In addition,
By using the mapping circuit 43, the column can be specified even if the column is switched by the first interleave, so that the value added by the adder 45 indicates a bit number.

The bit number thus obtained is converted by an address conversion circuit 46 into a row number and a column number from which data in the RAM 30 is to be read. For example, when the bit number is 5, the row number = address (add) is 1 and the column number is 5. In this case, since the number of data bits in the RAM 30 is 8, the lower three bits are
And the upper 4 bits or more as the number of rows of the RAM 30,
Output can be performed from the address conversion circuit 46. As described above, by using the address conversion circuit 46, even if the number of columns of the matrix and the number of bits of the RAM 30 are different from each other and a data sequence is generated in the RAM 30, data can be accurately read.

When data is read from the RAM 30, one row of data is read in units of address. Therefore, column data specified by the column number is extracted from the one row of data by the column selection circuit 50.

When the interleave length is K, the matrix (R × C) has L (= R × CK) blank bits (shown by oblique lines in the figure). In order to thin out the blank bits, the interleave length K is subtracted from the bit number by the subtracter 47 in the output address generation circuit 40. If the result is positive, it can be determined as a blank bit. The puncturing circuit (PUNC circuit) 60 thins out the data of the determined bit.

In this manner, data obtained by interleaving serial input data in multiple stages is output.

In the above-described example, the thinning-out operation is performed after the data is read from the RAM 30.
It is also possible to perform thinning out before reading data from 0. FIG. 10 shows an example in this case. A PUNK circuit 61 is provided on the output side of the address conversion circuit 46, and a row number and a column number for a bit number determined as a blank bit are thinned out so as not to be output.

In each of the examples shown in FIGS. 9 and 10, the PUNK circuits 60 and 61 include RA signals in order to prevent the data output timing from being distorted due to the thinning.
A storage element such as M (hereinafter, referred to as a thinning-out RAM) is provided.

In the examples of FIGS. 9 and 10, R
Since the number of data bits of the AM 30 is 8 and the number of columns C of the interleave matrix is variable, when the number of columns C is other than 8, the number of columns C of the matrix and the number of data bits of the RAM 30 are different. Therefore, the data output from the S / P conversion circuit 10 is stored in a RAM as shown in FIGS.
If all the data 30 are filled and filled with data, the data is arranged in the RAM 30 in a matrix arrangement different from the interleave matrix, and the address conversion circuit 46 is required.

The number of columns in the interleaved matrix is 2 ⁿ
== {1, 2, 4, 8, 32}, the calculation of the address conversion becomes very complicated. For this reason, there is a problem that the circuit scale of the entire device becomes large.

When thinning is performed, the PUNK circuit 6
It is necessary to prepare a thinning RAM at 0 and 61,
Since the thinning-out RAM requires a RAM having the same size as the data writing RAM 30, there is a problem that the circuit scale of the entire apparatus becomes large.

The present invention has been made in view of the above problems, and has a common object to reduce the circuit scale of the entire apparatus.

Another object of the present invention is to make it possible to read data without an address conversion circuit.

Another object of the present invention is to eliminate the need for a PUNK circuit for thinning out data so that data can be output accurately.

[0025]

In order to achieve the above object, according to the first aspect of the present invention, serial input data is stored in accordance with an interleave matrix of a row number R × a column number C in which the number of columns C is variable. An interleave device that stores data in an element and performs interleaving by making the writing direction and the reading direction different. Even when the number C of columns of the interleaving matrix changes, writing is performed on the storage element in the same matrix arrangement as the interleaving matrix. It is characterized by having such a configuration.

This eliminates the need for address translation when reading data.

In this case, specifically, a serial / parallel conversion circuit for converting serial input data into parallel data with the number of bits corresponding to the number of columns C is provided as in the second aspect of the present invention. In addition, writing can be performed on the storage element in the same matrix arrangement as the interleave matrix.

Further, as in the third aspect of the present invention, a plurality of storage elements are provided so that the total number of bits is larger than the maximum number of bits that can be taken by the number of columns C of the interleave matrix. The elements can be written in the same matrix arrangement as the interleave matrix.

In this case, it is preferable that writing and reading are performed by making the addresses of a plurality of storage elements common, as in the invention described in claim 4.

The interleaving device may be a device that performs multi-stage interleaving. In this case, writing is performed for each row of the matrix and reading is performed for each column of the matrix, and the columns are rearranged when data is read from the storage elements. In addition, as in the invention according to claim 6, data in which columns are rearranged is written in the storage element, or data is read from the storage element as in invention according to claim 7. After that, the columns can be rearranged.

Further, as in the eighth aspect of the present invention, there is provided a blank bit determining means for determining a blank bit by the time of reading the bit immediately before the blank bit, and based on the determination by the blank bit determining means. If the reading of the next bit is skipped by skipping the reading of the blank bits, the circuit for thinning out the blank bits can be eliminated. Further, a circuit for calculating a bit number as shown in FIGS. 9 and 10 can be omitted.

Similarly, according to the ninth aspect of the present invention,
Blank bit judging means for judging a blank bit in the column by the time of reading the bit one row before the last row in the reading for each column, and skips reading of the blank bit based on the judgment of the blank bit judging means. If the next bit is read out, the circuit for thinning out blank bits can be eliminated.

According to the tenth aspect of the present invention, serial input data is stored in a storage element in accordance with an interleave matrix of the number of rows R × the number of columns C, and the interleaving is performed by changing the writing direction and the reading direction. In the interleaving device that performs
Blank bit determining means for determining a blank bit by the time of reading the previous bit, and skipping the reading of the blank bit based on the determination of the blank bit determining means and reading the next bit. I have.

As a result, a circuit for thinning out blank bits can be eliminated. Also, FIG.
The circuit for calculating the bit number as shown in FIG. 10 can be omitted.

In this case, it is preferable that the blank bit determining means determines the blank bit by the time of reading the bit one row before the last row of the matrix.

[0036]

(First Embodiment) FIG. 1 shows the configuration of a multistage interleaver according to a first embodiment of the present invention. In this embodiment, two R elements are used as storage elements for writing data in the configuration shown in FIG.
AM 31 and 32 are provided. Also, the S / P conversion circuit 1
1 is configured to convert into parallel data of the same number as the number of columns C of the matrix. Further, the output address generation circuit 40 in this embodiment is configured to be able to output data column numbers and row numbers without providing the address conversion circuit 46 shown in FIG.

The operation will be described below, taking as an example the case where the number of columns C of the matrix is 10.

The serial input data is converted into parallel data in the S / P conversion circuit 11. in this case,
The number of columns C of the matrix is input to the S / P conversion circuit 11, and the S / P conversion circuit 11 converts the input data into the number of columns C.
(= 10), which is converted into parallel data of 10 bits. The converted parallel data is input to the first RAM 31 and the second RAM 32. In this case, since the total number of bits in the first and second RAMs 31 and 32 is 16, the parallel data is directly stored in one address. Therefore, the serial data of the interleave length K is arranged in the same matrix arrangement as the interleave matrix, and the first and second serial data are arranged as shown in FIG.
Are written to the RAMs 31 and 32. In other words, data is directly input into the first and second RAMs 31 and 32 in an interleaved matrix state.

The output address generation circuit 40 is provided with a row counter 41, a column counter 42, and a mapping circuit 43 having the same configuration as in FIG. Here, as described above, since the first and second RAMs 31 and 32 store data in the same matrix arrangement as the interleave matrix, the output of the row counter 41 and the output of the column counter 42 correspond to the row of the matrix. , Columns, ie, first and second RAM
The row numbers and column numbers of 31 and 32 are specified. Further, in this embodiment, a mapping circuit 43 is provided to perform the first interleaving, and the mapping circuit 43 determines which column of the matrix is to be read in an interleave pattern corresponding to the number C of columns. The output of the mapping circuit 43 specifies the column number after the first interleaving.

Therefore, the row number is specified by the output of the row counter 41, the column number after the first interleave is performed is specified by the output of the mapping circuit 43, and the first and second RAMs 31 are determined according to the row number and the column number. , 32 are read out. Thus, according to this embodiment, data can be read without providing the address conversion circuit 46.

In this embodiment, the first and second R
Since data is stored in the AMs 31 and 32 in the same matrix arrangement as the interleave matrix, the bit number is calculated by multiplying the output of the row counter 41 and the number of columns C by the multiplier 4.
8 and the result is added by the adder 45 to the output of the mapping circuit 43. For example, consider the bit number "15", which is in the second row and fifth column. In this case, the output of the row counter 41 is 1 and the output of the mapping circuit 43 is 5. Output of row counter 41 =
When 1 is multiplied by the number of columns = 10 in the multiplier 48 and added to the output = 5 of the mapping circuit 43, the result is 15
And the bit number can be obtained. Then, in the same manner as that shown in FIG. 9, the thinning-out determination is performed based on this bit number, and the thinning-out of blank bits is performed.

The number of columns C of the above-mentioned matrix is variable depending on the data transmission speed and the like.
In other cases, data can be written into the first and second RAMs 31 and 32 in the same matrix arrangement as that of the interleave matrix, and an output obtained by performing the first and second interleaving can be obtained.

In the above-described embodiment, two RAMs are used.
In this case, the number of RAMs is as follows.
The total number of bits is set to be larger than the maximum number of bits that the number of columns C of the matrix can take.

It is preferable that the RAMs have a common address as shown in FIG.
Even if a different address is set to M, it can be implemented.

The output address generation circuit 40 may be configured as shown in FIG. 2 to perform address thinning similarly to the configuration shown in FIG.

As described above, according to the present embodiment, the number of columns of the interleave matrix is {1, 2,
Even in the case other than 2 ⁿ such as 4, 8, 32, there is no need to perform address conversion, so that the circuit scale of the entire apparatus can be reduced. (Second Embodiment) In the above-described first embodiment, after writing data to the first and second RAMs 31 and 32, the first
Although the interleaving is shown, the first and second R
Before writing data to the AMs 31 and 32, the first interleave may be performed.

For example, as shown in FIG. 3, a first interleave circuit 70 is provided at the subsequent stage of the S / P conversion circuit 11 for the configuration shown in FIG. 1st interleave, and write the result to the first and second RAMs 31 and 32.

In this case, the first and second RAMs 31 and 32
Since the data after the 1st interleave is written in, the output of the column counter 42 specifies the column number from which the data is to be read as it is.

Similarly, the first interleave may be performed after data is read from the first and second RAMs 31 and 32. For example, in the configuration shown in FIG. 2, as shown in FIG. 4, a first interleave circuit is provided before the column selection circuit 50, and the first interleave is performed on data read from the first and second RAMs 31 and 32. . (Third Embodiment) In the first and second embodiments described above, P
Although the thinning is performed by providing the UNK circuits 60 and 61, if a blank bit is determined in advance and the next bit is read by skipping the blank bit, PU
A configuration without the NK circuit can be provided. Hereinafter, this embodiment will be described.

FIG. 5 shows the configuration. In this embodiment, in the output address generation circuit 40, an adder 45, a subtracter 47, and a multiplier 48 are added to the configuration shown in FIGS.
And a blank bit determination circuit 49 is provided instead. This blank bit determination circuit 49 performs the following operation.

The position of the blank bit in the blank bit number L (= R × CK) is specified from the interleave length K, the number of rows R of the matrix, and the number C of columns. Also, the row counter 41
From the output of the mapping circuit 43 and the first and second
It is possible to know how many rows and how many columns of data of the RAMs 31 and 32 are to be read out.
The read time point one row before (= R−1) is determined. When determining one line before the blank bit, a signal for incrementing by one is output to the row counter 41 and the column counter 42. As a result, the next bit is read while skipping the blank bits, so that the configuration without the PUNK circuit can be achieved. Note that the configuration may be such that the determination of the blank bit is made before the read time of the row before the blank bit, and the next bit is read by skipping the blank bit at the blank bit read timing.

This embodiment can be applied not only to the configuration shown in FIGS. 1 and 2, but also to the configuration shown in FIGS. FIG. 6 shows an example in which the present invention is applied to the embodiment shown in FIG.

In order to reduce the circuit scale by eliminating the PUNK circuit, the present invention can be similarly applied to the examples shown in FIGS. FIG. 7 shows an example of this case. This example shows a case where the number of bits of the RAM 30 is 8 and the number of columns C of the matrix is different from the number of data bits of the RAM, as in the case shown in FIGS. An address conversion circuit 46 is required.

In the various embodiments described above, an example is shown in which the present invention is applied to a multi-stage interleaver that performs rearrangement twice. However, the present invention can be similarly applied to an interleaver that performs rearrangement once. it can.

Further, the circuits and the like in the above embodiments are grasped as function realizing means for realizing the respective functions.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a multi-stage interleaver according to a first embodiment of the present invention.

FIG. 2 is a diagram showing another configuration of the multi-stage interleaver according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a multi-stage interleaver according to a second embodiment of the present invention.

FIG. 4 is a diagram showing another configuration of the multi-stage interleaver according to the second embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a multi-stage interleaver according to a third embodiment of the present invention.

FIG. 6 is a diagram showing another configuration of the multi-stage interleaver according to the third embodiment of the present invention.

FIG. 7 is a diagram showing still another configuration of the multi-stage interleaver according to the third embodiment of the present invention.

FIG. 8 is a diagram provided for describing the operation of a multi-stage interleaver.

FIG. 9 is a diagram showing a configuration of a multi-stage interleaver studied by the present inventors.

FIG. 10 is a diagram showing another configuration of the multi-stage interleaver studied by the present inventors.

[Explanation of symbols]

10, 11 S / P conversion circuit, 20 input address generation circuit, 30, 31, 32 RAM, 40 output address generation circuit, 41 row counter, 42 column counter, 43
... Mapping circuit, 44 ... Shifter, 45 ... Adder, 4
6 ... Address conversion circuit, 47 ... Subtractor, 48 ... Multiplier,
49: blank bit determination circuit, 50: column selection circuit, 60,
61 ... PUNC circuit, 70, 71 ... 1st interleave circuit.

Claims (11)

[Claims] 1. An interleave for storing serial input data in a storage element according to an interleave matrix of a row number R × a column number C in which the number of columns C is variable, and performing interleaving by making the writing direction and the reading direction different. An interleave device, wherein data is written to the storage element in the same matrix arrangement as the interleave matrix even when the number of columns C changes. 2. An interleave in which serial input data is stored in a storage element in accordance with an interleave matrix of a row number R × a column number C in which the number of columns C is variable, and interleaving is performed by changing a writing direction and a reading direction. A serial / parallel conversion circuit for converting the serial input data into parallel data with the number of bits corresponding to the number of columns C, and using the parallel data converted by the serial / parallel conversion circuit. An interleaving device, wherein writing is performed in the storage element in the same matrix arrangement as the interleave matrix. 3. An interleave for storing serial input data in a storage element in accordance with an interleave matrix of the number of rows R × the number of columns C in which the number of columns C is variable, and interleaving by making the writing direction and the reading direction different. In the apparatus, a plurality of the storage elements are provided so that the total number of bits is larger than the maximum number of bits that the number of columns C can take, and writing is performed using the plurality of storage elements in the same matrix arrangement as the interleave matrix. Interleaving device characterized in that the interleaving is performed. 4. The interleave device according to claim 3, wherein said plurality of storage elements are written and read using a common address. 5. The method according to claim 1, wherein the writing is performed for each row of the matrix, and the reading is performed for each column of the matrix. Further, when data is read from the storage element, the columns are rearranged. The interleave device according to claim 1, wherein: 6. The writing operation is performed for each row of the matrix, and the reading operation is performed for each column of the matrix. Further, the storage element stores data obtained by rearranging columns. 5. The interleaving device according to claim 1, wherein the data is written. 7. The writing is performed for each row of the matrix, and the reading is performed for each column of the matrix. After reading data from the storage element, the columns are rearranged. The interleave device according to claim 1, wherein: 8. A blank bit judging means for judging a blank bit occurring in the matrix by a time point at which the immediately preceding bit is read, and skips reading of the blank bit based on the judgment of the blank bit judging means. 8. The interleave device according to claim 1, wherein the next bit is read out. 9. A method according to claim 1, wherein one of the last rows in the reading for each column is performed.
It has blank bit determining means for determining a blank bit in the column by the time of reading of the bit before the row, and skips reading of the blank bit based on the determination of the blank bit determining means to read the next bit. 8. The interleaving device according to claim 5, wherein the interleaving is performed. 10. An interleave device for storing serial input data in a storage element in accordance with an interleave matrix of the number of rows R × the number of columns C and performing interleaving by making the writing direction and the reading direction different, wherein the interleave length K Is a blank bit for determining a blank bit by the time of reading the bit immediately before each blank bit for (R × CK) blank bits generated in the interleave matrix when K <R × C. An interleave device comprising a determination unit, wherein the reading of the blank bit is skipped and the next bit is read based on the determination of the blank bit determination unit. 11. The reading is performed for each column of the matrix, and the blank bit determining means determines the blank bit by the time of reading a bit one row before the last row of the matrix. The interleaving device according to claim 10, wherein