JP2001222895A - Semiconductor storage device and its operating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device and its operating method where an access time can be shortened. SOLUTION: Plural bit lines BL1-BLn are connected to a common data line CDL through a bit line selecting circuit 2. A dynamic pre-charge circuit 30 is connected to the common data line CDL. The dynamic pre-charge circuit 30 is composed of a capacitor transistor 30A, a transfer gate 30B, and a transistor 30C for charging. The capacitor transistor 30A is charged by turning on the transistor 30C for charging. The common data line CDL is connected to the capacitor transistor 30A by turning on the transfer gate 30B. After the common data line CDL and a selected bit line are charged, the transfer gate 30B is turned off, and the common data line CDL is separated from the capacitor transistor 30A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a memory cell is provided at an intersection of a bit line and a word line, and the bit line is connected to a common data line via a bit line selection circuit. The present invention relates to a semiconductor memory device and an operation method thereof.

[0002]

2. Description of the Related Art In a mask ROM (read only memory), information is written in a memory cell composed of transistors in a manufacturing process. Hereinafter, a transistor included in a memory cell is referred to as a cell transistor. For example, when writing information "0", the drain of the cell transistor is connected to the bit line via a contact, and when writing information "1", the drain of the cell transistor is not connected to the bit line.

FIG. 4 is a circuit diagram showing an example of the configuration of a conventional mask ROM. The mask ROM shown in FIG.
No. 6259.

As shown in FIG. 4, m word lines WL1
To WLm and n bit lines BL1 to BLn are arranged to cross each other. Here, m and n are each an integer. A plurality of ground lines SL are arranged corresponding to the plurality of word lines WL1 to WLm.

Further, (m × n) cell transistors T
11 to Tmn are arranged in a matrix. Each cell transistor Tij has a word line WLi and a bit line BLj.
Is provided at the intersection with. Where i = 1,2,2
, M and j = 1, 2,..., N. The gate of each cell transistor Tij is connected to the corresponding word line WLi, and the source is connected to the ground line SL. The drain of each cell transistor Tij is connected to the corresponding bit line BLj when the stored information is "0",
When the stored information is "1", the corresponding bit line B
Lj.

A plurality of word lines WL1 to WLm are connected to a word line selection circuit 11, and a plurality of bit lines BL1 to BLm are connected.
n is a common data line CDL via the bit line selection circuit 12.
It is connected to the. The bit line selection circuit 12 includes a plurality of transfer gates connected between each of the bit lines BL1 to BLn and the common data line CDL. The plurality of ground lines SL are connected to the plurality of reinforcing ground lines 5.

A reset circuit 21 is connected to each of the plurality of bit lines BL1 to BLn. Reset circuit 2
1 corresponds to the bit lines BL1 to BLB in response to the clock signal Φr.
Ln is grounded. The precharge circuit 13 is connected to the common data line CDL. Precharge circuit 1
3 is a common data line CDL in response to the clock signal Φp.
To the power supply voltage Vcc in the chip. Power supply voltage Vc
c is, for example, the operating voltage of the circuit of 5V. Common data line C
An output circuit 14 is connected between DL and the output terminal OL.

Further, m cell transistors T11 to T
A dummy circuit 20 is provided on the side of m1. The dummy circuit 20 includes m dummy cell transistors 20A, a dummy bit line 20B, a dummy bit line precharge circuit 20C, and a dummy bit line selection circuit 20D.

Each dummy cell transistor 20A is provided at an intersection of a corresponding word line WLi and a dummy bit line 20B. The configuration of the dummy cell transistor 20A is similar to the configuration of the cell transistor Tij, and the configuration of the dummy bit line precharge circuit 20C is similar to the configuration of the precharge circuit 13.

The dummy bit line selection circuit 20D comprises a transfer gate connected between the common data line CDL and the dummy bit line 20B. The power supply voltage Vc is applied to the gate of the transistor constituting the transfer gate.
c is given. Thus, the common data line CDL is always connected to the dummy bit line 20B via the dummy bit line selection circuit 20D. Although this dummy bit line selection circuit 20D is not necessary for the circuit operation,
It is provided to share the layout of 0 with the layout of the cell transistors T11 to Tmn and the bit line selection circuit 12.

Next, the read operation of the mask ROM of FIG. 4 will be described. During standby, the precharge circuit 13 charges the common data line CDL, and the dummy bit line precharge circuit 20C charges the dummy bit line 20B. Thereby, the potentials of the common data line CDL and the dummy bit line 20B become high level. Further, the potentials of all the bit lines BL1 to BLn are set to a low level by the reset circuit 21.

In a read operation, a plurality of cell transistors T1 to Tmn are operated based on an address signal (not shown).
Is selected. Here, for example, it is assumed that the cell transistor T22 is selected. In this case, the potential of the word line WL2 is raised to the high level by the word line selection circuit 11, and the bit line BL2 is connected to the common data line CDL by the bit line selection circuit 12.

Accordingly, when information "0" is stored in the cell transistor T22, the dummy bit line 2
The electric charge stored in 0B and the common data line CDL is discharged to the ground line SL via the bit line BL2 and the cell transistor T22. When information “1” is stored in the cell transistor T22, the dummy bit line 20
The charges stored in B and the common data line CDL are held without being discharged. The output circuit 14 changes the potential of the output terminal OL to a high level or a low level based on whether the potential of the common data line CDL is higher or lower than a predetermined threshold.

[0014]

In the conventional mask ROM, when information "1" is stored in the selected cell transistor T22, the potential of the common data line CDL previously charged to the high level is output. It is necessary to maintain a level higher than the threshold value in the circuit 14.

Since the potential of the selected bit line BL2 has been reset to a low level, the bit line selection circuit 12
Accordingly, when the bit line BL2 is connected to the common data line CDL, the potential of the common data line CDL decreases. At this time, if the parasitic capacitance of the common data line CDL is smaller than the parasitic capacitance of the bit line BL2, the amount of decrease in the potential of the common data line CDL increases.

Therefore, in the mask ROM of FIG. 4, the dummy bit line 20B is connected to the common data line CDL, and the dummy bit line 20B is also charged to a high level in advance.
That is, the common data line CDL is connected to the common data line CDL.
The parasitic capacitance of DL and the parasitic capacitance of dummy bit line 20B are added. Therefore, when the bit line BL2 is connected to the common data line CDL, the common data line CDL
Decreases in the potential of the first electrode. Therefore, the output circuit 1
4 can accurately output the information stored in the selected cell transistor T22 to the output terminal OL.

However, when the parasitic capacitance of the dummy bit line 20B is added to the common data line CDL in addition to the parasitic capacitance of the common data line CDL, the change in the potential of the common data line CDL is delayed. Therefore, when the information “0” is stored in the selected cell transistor T22, the time required for the potential of the common data line CDL to drop to a level lower than the threshold value of the output circuit 14 becomes longer. As a result, the operation speed of the mask ROM is reduced, and the access time is increased.

An object of the present invention is to provide a semiconductor memory device having a reduced access time and an operation method thereof.

[0019]

A semiconductor memory device according to a first aspect of the present invention includes a plurality of bit lines, a plurality of word lines arranged to cross the plurality of bit lines, and a plurality of bit lines. Select one of a plurality of memory cells provided at the intersection of a bit line and a plurality of word lines to store information, a common data line provided commonly to the plurality of bit lines, and a plurality of bit lines. A bit line selecting means for connecting the selected bit line to the common data line, and a word line selecting means for selecting any of a plurality of word lines for reading information from a memory cell to a corresponding bit line; After charging the common data line together with the bit line selected by the bit line selection means with the value of the capacitance added to the common data line being the first value, the value of the capacitance added to the common data line is changed to the first value. The value of 1 It is obtained by a charging means for reducing to a low second value.

In the semiconductor memory device according to the present invention,
One of the plurality of bit lines is selected by the bit line selecting means, and the selected bit line is connected to the common data line. Further, one of the plurality of word lines is selected by the word line selecting means for reading information from the memory cell to the corresponding bit line.

On the other hand, the common data line and the selected bit line are charged to a predetermined potential with the value of the capacitance added to the common data line being the first value. The potential of the bit line and the common data line is reduced or held in accordance with the information of the memory cell connected to the selected word line. Thereafter, the value of the capacitance added to the common data line is changed to the first value.
Is reduced to a second value that is smaller than Thereby,
The speed of change of the potential of the common data line is increased. Therefore, information can be read from the memory cell in a short time, and the access time is shortened.

The semiconductor memory device according to the second invention has the first
In the configuration of the semiconductor memory device according to the invention, the charging unit includes a capacitance unit, a capacitance charging unit that charges the capacitance unit,
Connecting the capacitance means charged by the capacitance charging means to the common data line to charge the common data line together with the bit line selected by the bit line selection means, and then disconnecting the capacitance means from the common data line. It is a thing.

In this case, the capacity means is charged by the capacity charging means. Then, the charged capacitance means is connected to the common data line by the connection means. Thereby, the common data line and the selected bit line are charged to a predetermined potential. The potential of the bit line and the common data line is reduced or held in accordance with the information of the memory cell connected to the selected word line.

Thereafter, the connection means disconnects the capacitance means from the common data line. Thereby, the value of the capacitance added to the common data line is reduced, and the speed of change in the potential of the common data line is increased. Therefore, information can be read from the memory cell in a short time, and the access time is shortened.

The semiconductor memory device according to the third aspect of the present invention is the semiconductor memory device according to the second aspect.
In the configuration of the semiconductor memory device according to the invention, the connection means is a switching element connected between the common data line and the capacitance means.

In this case, when the switching element is turned on, the common data line is connected to the capacitance means, and when the switching element is turned off, the common data line is disconnected from the capacitance means.

The semiconductor memory device according to the fourth aspect of the present invention is the semiconductor memory device according to the second aspect.
Alternatively, in the configuration of the semiconductor memory device according to the third aspect, the capacitance charging means charges the capacitance means in a state where the bit line selected by the bit line selection means is connected to the common data line. In this case, it is possible to arbitrarily set the charging timing of the capacitance means.

The semiconductor memory device according to a fifth aspect of the present invention is the semiconductor memory device according to the second aspect.
In the configuration of the semiconductor memory device according to any one of the fourth to fourth inventions, the word line selecting means sequentially selects a plurality of word lines while any one of the plurality of bit lines is selected by the bit line selecting means. It is.

In this case, since the common data line can be disconnected from the capacitance means by the connection means, the capacitance means can be charged while the selected bit line is connected to the common data line. Thus, an operation of sequentially selecting a plurality of word lines while any one of the plurality of bit lines is selected by the bit line selecting means becomes possible, and a high-speed access operation is realized.

According to a sixth aspect of the present invention, there is provided a method of operating a semiconductor memory device, comprising: a plurality of bit lines; a plurality of word lines arranged so as to intersect the plurality of bit lines; a plurality of bit lines and a plurality of word lines; A plurality of memory cells provided at the intersection of the plurality of bit lines, and a common data line provided commonly to the plurality of bit lines, the method comprising: selecting one of the plurality of bit lines. Connecting the selected bit line to a common data line; selecting one of a plurality of word lines for reading information from a memory cell to a corresponding bit line; After the common data line is charged together with the selected bit line with the value of the capacitance to be set as the first value, the value of the capacitance added to the common data line is set to the second value smaller than the first value. To reduce It is that a flop.

In the method of operating a semiconductor memory device according to the present invention, one of a plurality of bit lines is selected, and the selected bit line is connected to a common data line. Further, one of a plurality of word lines is selected for reading information from a memory cell to a corresponding bit line.

On the other hand, the common data line and the selected bit line are charged to a predetermined potential with the value of the capacitance added to the common data line being the first value. The potential of the bit line and the common data line is reduced or held in accordance with the information of the memory cell connected to the selected word line. Thereafter, the value of the capacitance added to the common data line is changed to the first value.
Is reduced to a second value that is smaller than Thereby,
The speed of change of the potential of the common data line is increased. Therefore, information can be read from the memory cell in a short time, and the access time is shortened.

In a method of operating a semiconductor memory device according to a seventh aspect of the present invention, in the method of operating a semiconductor memory device according to the sixth aspect of the present invention, the step of reducing includes a step of charging the capacitance means and a step of charging the charged capacitance means. Charging the common data line and the selected bit line by connecting to the common data line, and disconnecting the capacitance unit from the common data line after charging the common data line and the selected bit line by the capacitance unit. Including.

In this case, the capacitance means is charged, and the charged capacitance means is connected to the common data line. Thereby,
The common data line and the selected bit line are charged to a predetermined potential. The potential of the bit line and the common data line is reduced or held in accordance with the information of the memory cell connected to the selected word line. Thereafter, the capacitance means is disconnected from the common data line. Thus, the capacitance added to the common data line is reduced, and the speed of change in the potential of the common data line is increased. Therefore, information can be read from the memory cell in a short time, and the access time is shortened.

In the method of operating a semiconductor memory device according to an eighth aspect of the present invention, in the operation method of the semiconductor memory device according to the seventh aspect of the present invention, the step of charging the capacitance means includes the step of connecting the selected bit line to a common data line. In this state, the capacity means is charged. In this case, it is possible to arbitrarily set the charging timing of the capacitance means.

In the method of operating a semiconductor memory device according to a ninth aspect, in the method of operating a semiconductor memory device according to the seventh or eighth aspect, the step of selecting one of the plurality of word lines is selected. A plurality of word lines are sequentially selected while the bit lines are connected to the common data line.

In this case, by disconnecting the common data line from the capacitance means, the capacitance means can be charged while the selected bit line is connected to the common data line. Thereby, an operation of sequentially selecting a plurality of word lines while any one of the plurality of bit lines is selected becomes possible, and a high-speed access operation is realized.

[0038]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to one embodiment of the present invention. The semiconductor memory device of the present embodiment is a mask ROM.

As shown in FIG. 1, m word lines WL1
To WLm and n bit lines BL1 to BLn are arranged to cross each other. Here, m and n are each an integer. A plurality of ground lines SL are arranged corresponding to the plurality of word lines WL1 to WLm.

In addition, (m × n) memory cells C11 to Cmn formed of transistors are arranged in a matrix. Each memory cell Cij is provided at the intersection of a word line WLi and a bit line BLj. Where i =
1, 2, ..., m, and j = 1, 2, ..., n.

The gate of each memory cell Cij is connected to the corresponding word line WLi, and the source is connected to the ground line SL. The drain of each memory cell Cij is connected to the corresponding bit line BLj when the stored information is "0", and is separated from the corresponding bit line BLj when the stored information is "1". I have.

The plurality of word lines WL1 to WLm are connected to the word line selection circuit 1. The word line selection circuit 1
In response to the address signal AW, a plurality of word lines WL1 to WL
Lm, and selects the selected word line WLi.
Rise to a high level.

The plurality of bit lines BL1 to BLn are connected to the common data line CDL via the bit line selection circuit 2. The bit line selection circuit 2 includes a plurality of bit lines BL1 to BL
It is constituted by a plurality of transfer gates 2A respectively connected between Ln and the common data line CDL. FIG.
Shows only one transfer gate 2A. The bit line selection circuit 2 selects one of the plurality of bit lines BL1 to BLn in response to the address signal AB, and connects the selected bit line BLj to the common data line CDL.

Further, the plurality of reinforcing ground lines 5 are
They are arranged substantially parallel to L1 to BLn. The plurality of ground lines SL are connected to the plurality of reinforcing ground lines 5.

A reset circuit 6 is connected to each of the plurality of bit lines BL1 to BLn. Reset circuit 6
Consists of N-channel transistors, and the clock signal Φ
In response to r, the bit lines BL1 to BLn are grounded.

The precharge circuit 7 is connected to the common data line CDL. Precharge circuit 7 is formed of a P-channel transistor, and charges common data line CDL to power supply voltage Vcc in response to clock signal φp. The power supply voltage Vcc is the operating voltage of a circuit in the chip (for example, 5
V).

Further, a dynamic precharge circuit 30 is connected to the common data line CDL. The dynamic precharge circuit 30 includes a capacitor transistor 30A having a capacitance value larger than the parasitic capacitance of one bit line BLj, a transfer gate 30B including a P-channel transistor, and a charging transistor 30C including a P-channel transistor.

Transfer gate 30B is connected between common data line CDL and node N, and receives clock signal Φ.
Turns on or off in response to 2. Capacitor transistor 30A is connected between node N and a ground terminal. Charging transistor 30C is connected between a power supply terminal receiving power supply voltage Vcc and node N, and is turned on or off in response to clock signal Φ1.

An output circuit 4 is connected between the common data line CDL and the output terminal OL. The output circuit 4 changes the potential of the output terminal OL to a high level or a low level based on whether the potential of the common data line CDL is higher or lower than a predetermined threshold value TH (for example, an intermediate level between the power supply voltage Vcc and the ground potential). To change.

Next, the read operation of the semiconductor memory device of FIG. 1 will be described. FIG. 2 is a waveform chart for explaining an example of the read operation of the semiconductor memory device of FIG.

In FIG. 2, during standby, the clock signal Φr is at a high level. As a result, the reset circuit 6 is turned on, and the potentials of all the bit lines BL1 to BLn are set to the low level. Further, the clock signal Φp is at the low level. Thereby, the precharge circuit 7 is turned on, and the potential of the common data line CDL is charged to a high level.

At this time, the clock signal Φ2 is at a high level. Thereby, the transfer gate 30B of the dynamic precharge circuit 30 is turned off, and the common data line CDL is disconnected from the node N. Further, the clock signal Φ1 is at the low level. Thereby,
The charging transistor 30C is turned on, and the node N is charged to the power supply voltage Vcc.

At the time of the read operation, the clock signal Φr falls to the low level at time t1. Thereby, the reset circuit 6 is turned off. Further, the clock signal Φp rises to a high level. Thereby, the precharge circuit 7
Turns off. Further, the clock signal Φ1 rises to a high level. This turns off the charging transistor 30C.

Thereafter, at time t2, the clock signal Φ2 falls to a low level. Thereby, the transfer gate 30B is turned on, and the common data line CDL is connected to the node N.

One of a plurality of memory cells C11 to Cmn is selected based on address signals AB and AW. Here, it is assumed that the memory cell Cij is selected. In this case, the bit line selection circuit 2 changes the bit line BLj to the common data line CDL in response to the address signal AB.
Connect to Thereby, the potential of bit line BLj increases, and the potentials of common data line CDL and node N decrease.

At this time, the node N is connected to the common data line CDL.
Is connected to the common data line CDL via the common data line CDL.
The parasitic capacitance of L and the capacitance of the capacitor transistor 30A are added. Therefore, the potentials of common data line CDL and bit line BLj are set to threshold value TH of output circuit 4.
It is set to a higher level (for example, 2/3 of the power supply voltage Vcc). At this time, the potentials of the common data line CDL and the bit line BLj can be arbitrarily set by adjusting the capacitance value of the capacitor transistor 30A.

The word line selection circuit 1 selects the word line WLi in response to the address signal AW, and raises the potential of the selected word line WLi to a high level. Time t
At 3, the potential of the word line WLi exceeds a predetermined potential. When information “0” is stored in the selected memory cell Cij, the charges of the common data line CDL and the node N are transferred to the ground line SL via the bit line selection circuit 2, the bit line BLj and the memory cell Cij. Discharged. Thereby,
The potentials of the common data line CDL and the bit line BLj decrease.

At time t4, the clock signal Φ2 rises to a high level. Thereby, the transfer gate 30B
Is turned off, and the common data line CDL is disconnected from the node N and the capacitor transistor 30A. That is,
Only the parasitic capacitance of the common data line CDL is added to the common data line CDL. Therefore, common data line CD
The falling speed of the potentials of L and bit line BLj increases. Therefore, at time t5, the potential of the common data line CDL falls below the threshold value TH of the output circuit 4. As a result, the output circuit 4 lowers the potential of the output terminal OL to a low level.

Further, the clock signal Φ1 falls to a low level. As a result, the charging transistor 30C is turned on, and the node N is charged to the power supply voltage Vcc.

Information "1" is stored in the selected memory cell Cij.
Is stored in the word line WLi at time t3.
After the potential of the common data line CD exceeds a predetermined potential.
L and the potential of the bit line BLj maintain a high level higher than the threshold value TH of the output circuit 4. Therefore, the output circuit 4 holds the potential of the output terminal OL at a high level.

As shown by the dashed line, when the potential of the clock signal Φ2 is kept at the low level during the read operation, the transfer gate 30B is kept on, and the common data line CDL is connected to the node N. To maintain. In this case, the parasitic capacitance of the common data line CDL and the capacitor transistor 30 are connected to the common data line CDL.
Since the state where the capacitance of A is added is maintained, the rate of decrease in the potential of the common data line CDL and the bit line BLj is reduced. As a result, the potential of the common data line CDL becomes t
6, the output terminal 4 becomes equal to or less than the threshold value TH of the output circuit 4, and the output terminal O
The potential of L falls to a low level.

As described above, the selected bit line BLj is connected to the capacitor transistor 3 via the common data line CDL.
By turning off the transfer gate 30B after charging with the voltage of 0A and disconnecting the common data line CDL from the capacitor transistor 30A, the fall timing of the potential of the output terminal OL can be advanced by the time Δt.

By separating the common data line CDL from the capacitor transistor 30A by the transfer gate 30B, the capacitor transistor 30A can be charged at an arbitrary timing. Thereby,
The waiting time can be reduced. For example, the clock signal Φ2 in FIG. 2 may fall at a timing earlier than the time point t3 as shown by a broken line.

In the conventional mask ROM shown in FIG. 4, the bit lines BL1 to BLn need to be separated from the common data line CDL by the bit line selection circuit 12 in order to charge the dummy bit line 20B.

On the other hand, in the semiconductor memory device of FIG. 1, the transfer gate 30B controls the common data line CD.
Since L can be separated from the capacitor transistor 30A, the capacitor transistor 30A can be charged in a state where any of the bit lines BL1 to BLn is connected to the common data line CDL via the bit line selection circuit 2. . The operation in this case will be described below.

FIG. 3 is a waveform diagram for explaining another example of the read operation of the semiconductor memory device of FIG.

In the example of FIG. 3, the selected bit line BLj
Are connected to the common data line CDL via the bit line selection circuit 2 and the word line selection circuit 1 randomly selects a plurality of word lines WL1 to WLm. During this time, the clock signal Φr is at the low level. As a result, the reset circuit 6 is off.

First, the clock signal Φp is at the high level. Thus, the precharge circuit 7 is off. At this time, the clock signal Φ2 is at the high level. Thereby, the dynamic precharge circuit 3
The transfer gate 30B of 0 is turned off, and the common data line CDL is disconnected from the node N. Further, the clock signal Φ1 is at the low level. Thereby, charging transistor 30C is turned on, and node N is charged to power supply voltage Vcc.

At this time, it is assumed that the potentials of bit line BLj and common data line CDL are at low level. At time t11, the potential of the selected word line WLi rises to a high level.

Thereafter, the clock signal Φ1 rises to a high level. This turns off the charging transistor 30C.

Next, at time t12, the clock signal Φ2 falls to a low level. Thereby, transfer gate 30B is turned on, and bit line BLj and common data line CDL are connected to node N. Also, the clock signal Φ
p falls to a low level. Thereby, the precharge circuit 7 turns on. As a result, the potentials of the common data line CDL and the bit line BLj increase.

In this example, since the potential of node N has already been charged to power supply voltage Vcc, the rising speed of the potential of common data line CDL and bit line BLj increases.

At this time, node N is connected to common data line CDL.
Is connected to the common data line CDL via the common data line CDL.
The parasitic capacitance of L and the capacitance of the capacitor transistor 30A are added. Therefore, the potentials of common data line CDL and bit line BLj are set to threshold value TH of output circuit 4.
Set to a higher level.

When information "0" is stored in memory cell Cij connected to word line WLi and bit line BLj, charges on common data line CDL and node N are transferred to bit line selection circuit 2, bit line BLj And is discharged to ground line SL via memory cell Cij. Thereby, the potentials of common data line CDL and bit line BLj decrease.

At time t13, the clock signal Φ2 rises to a high level. Thereby, the transfer gate 30
B turns off, and the common data line CDL is disconnected from the node N and the capacitor transistor 30A. at the same time,
The clock signal Φp rises to a high level. Thereby, the precharge circuit 7 turns off. Further, the clock signal Φ1 falls to a low level. Thereby, the charging transistor 30C is turned on, and the node N is charged.

In this case, since the common data line CDL is disconnected from the capacitor transistor 30A, only the parasitic capacitance of the common data line CDL is added to the common data line CDL. Therefore, the falling speed of the potentials of the common data line CDL and the bit line BLj increases. As a result, at time t14, the potential of the common data line CDL falls below the threshold value TH of the output circuit 4. As a result, the output circuit 4 lowers the potential of the output terminal OL to a low level.

When information "1" is stored in memory cell Cij connected to word line WLi and bit line BLj, bit line BLj and common data line CDL are stored.
Rises to a high level higher than the threshold value TH of the output circuit 4 and maintains that level. Therefore, the output circuit 4 holds the potential of the output terminal OL at a high level.

As shown by the dashed line, at time t13
After that, if the clock signal Φ2 is kept at the low level, the transfer gate 30B maintains the ON state, and the state where the common data line CDL is connected to the node N is maintained. In this case, the common data line CDL is connected to the common data line CDL.
Since the state where the parasitic capacitance of L and the capacitance of the capacitor transistor 30A are added is maintained, the rate of decrease in the potential of the bit line BLj and the common data line CDL is reduced.
Therefore, the potential of the common data line CDL becomes equal to or lower than the threshold value TH of the output circuit 4 at time t15, and the potential of the output terminal OL falls to a low level.

Also in this example, the selected bit line BL
j is charged with the voltage of the capacitor transistor 30A via the common data line CDL, and then the common data line CDL is separated from the capacitor transistor 30A.
The timing of the fall of the potential of the output terminal OL is represented by time Δ
can be advanced by t.

As described above, in the semiconductor memory device of FIG. 1, common data line CD is provided by transfer gate 30B.
Since L can be separated from the capacitor transistor 30A, the capacitor transistor 30A can be charged while the selected bit line BLj is connected to the common data line CDL via the bit line selection circuit 2.
Therefore, the operation of randomly selecting a plurality of word lines WL1 to WLm can be performed while the selected bit line BLj is connected to the common data line CDL via the bit line selection circuit 2, and a high-speed access operation can be performed. Is achieved.

In the above embodiment, the present invention is applied to the mask R
Although the case where the present invention is applied to the OM has been described, the present invention is not limited to the mask ROM, but can be applied to other ROMs or other semiconductor memory devices.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining an example of a read operation of the semiconductor memory device of FIG. 1;

FIG. 3 is a waveform chart for explaining another example of the read operation of the semiconductor memory device of FIG. 1;

FIG. 4 is a circuit diagram showing an example of a configuration of a conventional mask ROM.

[Explanation of symbols]

 Reference Signs List 1 word line selection circuit 2 bit line selection circuit 4 output circuit 6 reset circuit 7 precharge circuit 30 dynamic precharge circuit 30A capacitor transistor 30B transfer gate 30C charging transistor WL1 to WLm word line BL1 to BLn bit line N node CDL common data Line OL output terminal

Claims (9)

[Claims] A plurality of bit lines; a plurality of word lines arranged so as to intersect with the plurality of bit lines; and an information portion provided at an intersection between the plurality of bit lines and the plurality of word lines. A plurality of memory cells, a common data line provided in common with the plurality of bit lines, and selecting one of the plurality of bit lines, and connecting the selected bit line to the common data line Bit line selecting means; word line selecting means for selecting any of the plurality of word lines for reading information from the memory cell to a corresponding bit line; and a value of capacitance added to the common data line After the common data line is charged together with the bit line selected by the bit line selecting means in a state where is set to the first value, the value of the capacitance added to the common data line is smaller than the first value. And a charging means for reducing the value to a second value. 2. The common data line according to claim 2, wherein said charging means comprises: a capacity means; a capacity charging means for charging said capacity means; and said capacity means charged by said capacity charging means connected to said common data line. 2. The semiconductor memory device according to claim 1, further comprising: connection means for disconnecting said capacitance means from said common data line after charging with said bit line selected by said bit line selection means. 3. The semiconductor memory device according to claim 2, wherein said connection means is a switching element connected between said common data line and said capacitance means. 4. The capacitance charging unit according to claim 2, wherein the capacitance charging unit charges the capacitance unit in a state where the bit line selected by the bit line selection unit is connected to the common data line. Semiconductor storage device. 5. The word line selecting means sequentially selects a plurality of word lines while any one of the plurality of bit lines is selected by the bit line selecting means. The semiconductor memory device according to any one of the above. 6. A plurality of bit lines, a plurality of word lines arranged to cross the plurality of bit lines, and a memory provided at an intersection of the plurality of bit lines and the plurality of word lines. A method of operating a semiconductor memory device comprising: a cell; and a common data line provided commonly to the plurality of bit lines, the method comprising: selecting one of the plurality of bit lines; Connecting to a common data line, selecting one of the plurality of word lines for reading information from a memory cell to a corresponding bit line, and selecting a value of a capacitance added to the common data line. After charging the common data line with the selected bit line in the state where the first value is set, the value of the capacitance added to the common data line is reduced to a second value smaller than the first value. Letting And an operation method of the semiconductor memory device. 7. The step of charging includes: charging a capacitance unit; and charging the common data line and the selected bit line by connecting the charged capacitance unit to the common data line. 7. The operation of the semiconductor memory device according to claim 6, further comprising: after charging the common data line and the selected bit line by the capacitance unit, disconnecting the capacitance unit from the common data line. Method. 8. The semiconductor memory device according to claim 7, wherein said step of charging said capacitance means charges said capacitance means with said selected bit line connected to said common data line. How it works. 9. The method according to claim 1, wherein the step of selecting any one of the plurality of word lines includes sequentially selecting the plurality of word lines while the selected bit line is connected to the common data line. Item 9. The method for operating a semiconductor memory device according to item 7 or 8.