JP2001222517A - Distributed shared memory multiplex processor system having direction-separated duplex ring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a distributed shared memory multiplex processor system having direction-separated duplex ring structure while using a snooping system. SOLUTION: There are plural processor nodes arrayed in the shape of ring, any one of plural processor nodes generates a request signal to one data block and the remaining processor nodes snoop their own internal elements. Thus, there are plural processor nodes for supplying a data block from any one of the remaining processor nodes and there is a direction-separated duplex ring structure for supplying two opposite routes along with first and second ring paths while including the first and second ring paths by snooping the internal element of the remaining processor nodes. Then, this system is provided with the direction-separated duplex ring structure, to which the plural processor nodes are connected through the first and second routes, for performing the multi-address communication of the request signal through any one of routes to each of the remaining processor nodes and performing the single communication of the data block through any one of routes to the processor node, which generates the request signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a distributed shared memory multiprocessor system, and more particularly, to a distributed shared memory multiprocessor system having a direction-separated dual ring structure.

[0002]

2. Description of the Related Art In general, a multi-processor system uses a distributed memory structure that implements communication between processors using explicit message-passing.
-memoryarchitecture) and a shared memory structure (shared-memory a
At present, the most popular technology in the interconnection network of the shared memory multiprocessor system is the shared bus. Shared buses are widely used because of their low implementation complexity and low cost, but have the disadvantage that they cannot keep up with the speed of processors whose performance is improving rapidly. In addition, there are problems in scalability due to physical characteristics of the bus and bus bandwidth due to an increase in bus usage.

[0003] As a result of various attempts to overcome the limitations of such a bus structure, IEEE SCI using a unidirectional point-to-point link has been established as a standard. Up to four processors are connected by UMA (Uniform M
emory Access) in the form of SC
A general-purpose system has been disclosed which is connected by a unidirectional ring structure using an I-link and realized using a directory-based cache protocol. (Tom Lovett and Russ
ell Clapp's “STiNG: A CC-NUMA ComputerSystem f
or the Commercial Marketplace ”(In Proceedings
of the23th International Symposium on Compu
ter Architecture, pp. 308-317, May 1996).
As shown in the figure, a multiplexing system in which a processor in which up to four processors are connected in a unidirectional ring structure using SCI links with processor nodes provided in the form of UMA by a snooping bus is implemented using a snooping cache protocol. Processor system is "PANDA: Ring-Based Multiprocessor Syst"
em using New Snooping Protocol ”(In The Pro
ceeding of ICPADS 1998, pp.10-17, Dec.1998) (19
(See Japanese Patent Application No. 224423/98 filed on Aug. 7, 1998).

However, as the cracking speed of the processor and the local bus is increasing, the distributed shared memory multiprocessor system adopting such a high performance processor and the local bus is not suitable for single point link bandwidth and system. Extension needed. Therefore, in order to extend the point-to-point link bandwidth in the existing system, there is a method of simply using a link having twice the bandwidth, but the development of a new link having a bandwidth which is now doubled is developed. And applying it to commercialized products in a short time is actually difficult.

[0005]

SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a direction-separating dual to improve performance while maintaining cache coherency between processor nodes in a system using a snooping scheme. An object of the present invention is to provide a distributed shared memory multiprocessor system having a ring structure.

[0006]

According to the present invention, there is provided, in accordance with the present invention, a plurality of processor nodes arranged in a ring, and any one of the plurality of processor nodes may be one of the plurality of processor nodes. Generating a request signal for a data block and causing the remaining processor node to snoop its own internal element such that one of the remaining processor nodes supplies the data block; Including a ring bus, there is a direction separated double ring structure that provides two opposite paths along the first and second ring buses, and the plurality of processor nodes are connected via the first and second paths. The request signal is broadcast to each of the remaining processor nodes via any of the paths, and the data block is Distributed shared memory multiprocessor system comprising said direction separated dual ring structure is a single communication is provided to the processor node that generated the request signal via one of the.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings.

Referring to FIG. 3, a distributed shared memory multiprocessor system 100 based on a point-to-point direction-separating dual ring structure, eg, 90A and 90B, supporting a snooping scheme is shown. Heavy ring bus 9
0A and 90B are implemented using point-to-point links, and each of the point-to-point links can be implemented using an optical fiber, a coaxial cable, or an optical connection capable of transmitting a plurality of signals. According to a preferred embodiment of the present invention, distributed shared memory multiprocessor system 100 includes eight processor nodes, PN1-PN8 (10-80). PN1 (10) to PN8 (80)
Are connected via point-to-point directional splitting dual rings 90A and 90B that support snooping.

Here, the "direction-separated dual ring" has two separated ring buses whose traveling directions are opposite to each other, and includes a data request signal from a processor node or a data block corresponding to the request signal. In a first direction having a closest path, or in a second direction opposite to the first direction. As shown in FIG. 3, the direction separating dual ring structure includes a first ring bus 90A and a second ring bus 90B, and a request signal and a retrieved data block are requested by an attribute of the data block, for example, by a certain processor node. Depending on where the data block containing the stored data is stored in the even memory block address and the odd memory block address, the data block is transmitted via the first ring bus 90A or the second ring bus 90B.

FIG. 4 shows in more detail the configuration of any one of a plurality of processor nodes PN1 to PN8 (10 to 80) having the same configuration, for example, PN1 (10). I have. As shown in FIG. 4, PN1 (10) has a number of processor modules incorporating a cache,
Input / output (I / O) bridge 216 and local system bus 218
, A local shared memory 220, a node controller 222, a remote cache 224, a memory directory 226, a link bus 228, and a ring interface 230.

For convenience of description, only two processor modules, a first processor module 212 and a second processor module 214, are shown in FIG. 4 and include processor modules 212 and 214 and a local shared memory 220.
, The I / O bridge 216 and the node controller 222 are connected to each other through the local system bus 218.

The ring interface 230 includes two link controllers 230A and 230B, through which each processor node is connected to a directionally separated dual ring structure, ie, ring buses 90A and 90B, respectively. In this embodiment, the ring interface 230 is connected to the node controller 222 via the link bus 228.

The node controller 222 searches whether the data block corresponding to the request signal from one of the processor modules 212 and 214 is stored in the remote cache 224 or the local shared memory 220 in a valid state. As a result of the search, the data block is
If it is stored in a valid state in 4, the node controller 2
22 supplies the corresponding data block stored in the remote cache 224 to the processor module that generates the request signal, but if the data block is stored in the local shared memory 220 in a valid state, the local shared memory
220 supplies the data block to the processor module that generated the request signal.

The remote cache 224 and the local shared memory 2
In both cases, the data block is not stored in a valid state, and if the data block is an odd block address, that is, an odd block, a request signal for the data block is sent to the first ring controller via the first link controller 230A. Transmit to bus 90A. On the other hand, if the data block is an even block address, that is, an even block, a request signal for the data block is transmitted to the second ring bus 90B via the second link controller 230B. As described above, the node controller 222 transmits a request signal for a data block via the ring interface 230, that is, the first link controller 230A and the second link controller 230B, to the other processor nodes PN2 to PN.
Supply to N8 (20-80).

Subsequently, the other processor nodes PN2 to PN8 (2
0 to 80), a request signal for a data block is received via the first link controller 230A or the second link controller 230B, and the node controller 222 determines that the data block corresponding to the request signal is its own. Is searched in a valid state in the remote cache 224 or the local shared memory 220. As a result of the search, if the data block is stored valid in the remote cache 224 or the local shared memory 220, the node controller 222 transmits the data block from the remote cache 224 or the local shared memory 220 via the local system bus 218. And the first ring bus 90A or the second ring bus 90B having a path closest to the processor node that requested the data block.
Via the data block.

As shown in FIG. 4, each of the processor nodes PN1 to PN8 (10 to 80) further includes a memory directory 226 for storing status information for data blocks stored in the local shared memory 220, and includes a node controller 222 accesses memory directory 226 directly. Therefore, the node controller 222 effectively searches the memory directory 226 to find out in which state the data block requested by one of the processor modules 212 and 214 is stored in the local shared memory 220, and to read the other processor nodes.
It is possible to effectively search in which state the data block requested from any of PN2 to PN8 (20 to 80) is stored in its own local shared memory 220. More preferably, the memory directory 226 is located in FIG.
As shown in the two independent memory directories 226A
And 226B.

The first memory directory 226A responds to local shared memory access requests from the processor modules 212 and 214 transmitted over the local system bus 218, and the second memory directory 226B
The other processor nodes PN2 to PN8 (20) via a ring interface 230 connected to the node controller 222 via 28.
-80) responds to the remote shared memory access request transmitted. Through such a method, the local memory 220
Can be made in parallel.

The first link controller 230A and the second link controller 23
0B provides a data path connecting PN1 (10) to the direction-separating dual ring buses 90A and 90B and controls the overall data flow required for packet transmission. 1st link controller 230A
And the second link controller 230B form a packet having a request signal and a data block from the node controller 222, and
The signal is transmitted to other processor nodes PN2 to PN8 (20 to 80) via the ring bus 90A or the second ring bus 90B, and is transmitted to the other processor nodes PN2 to PN8 (20 to 80) via the first ring bus 90A or the second ring bus 90B. 20 to 80) are selected and transmitted to the node controller 222. When the request signal to be transmitted is a broadcast packet, the link interface 230 not only transmits the broadcast packet to the node controller 222 for snooping, but also transmits the transmitted broadcast packet to the next processor node PN2 ( 20) or bypass to PN8 (80). More specifically, the first link controller 230A transmits a broadcast packet transmitted from the adjacent processor node PN8 (80) via the first ring bus 90A to another adjacent processor node via the first ring bus 90A. PN2 (20), and the second link controller 230B transmits the broadcast packet transmitted from the adjacent processor node PN2 (20) via the second ring bus 90B to another adjacent neighbor via the second ring bus 90B. To the processor node PN8 (80).

On the other hand, the remote cache 224 caches only the data blocks stored in the local shared memories (hereinafter referred to as remote shared memories) of the other processor nodes PN2 to PN8 (20 to 80) except for itself. If any of the processor modules 212 and 214 connected to the local system bus 218 requests a data block stored in a remote shared memory of any of the other processor nodes PN2-PN8 (20-80), the data block Is a remote cache 22
Data blocks allocated to 4 and stored in local shared memory 220 are not cached. That is, as described above, the remote cache 224 of the processor node PN1 (10) caches only the data blocks stored in the remote shared memories of the other processor nodes PN2 to PN8 (20 to 80), thereby enabling the remote memory access. Time can be reduced.

The remote cache 224 is a processor node PN1
(10) MLI properties (Multi-Level Included) for caches in the processor modules 212 and 214 and remote shared memories in other processor nodes PN2 to PN8 (20 to 80).
on Property), another processor node PN2
PN8 (20 to 80) can perform a snoop filtering function for a remote shared memory reference request. Here, the MLI property is the lower hierarchy,
That is, a data block stored in a valid state in the local cache must be always stored in a valid state in an upper layer, that is, a remote cache. In order to guarantee such MLI characteristics, the data blocks stored in the upper-level cache are replaced (replaceme
nt), the data block must not be valid in any lower-level cache.

Accordingly, the remote cache 224 stores the remote data blocks stored in the caches in the processor modules 212 and 214 of the processor node PN1 (10) in a valid state. Other processor nodes PN2 to P
If a data block responding to the remote shared memory reference request signal from N8 (20 to 80) is not stored in the remote cache 224 in a valid state, it is necessary to transmit a request for the data block on the local system bus 218. Performs no snooping and filtering functions.

At this time, the preferred or remote cache 224
Includes a remote data cache 224-1 for storing the contents of a data block and a remote tag cache 224-2 for storing a part of the data block status and address, thereby enabling the status of the data block stored in the remote cache 224 to be stored. Updating or, if necessary, facilitating supply of the corresponding data block. More preferably, remote tag cache 224-2 includes two remote tag caches for storing addresses and status of remote data blocks, a first remote tag cache 224-2A and a second remote tag cache 224-2B. The first remote tag cache 224-2A responds to remote cache access requests by any of the processor modules 212 and 214, and the second remote tag cache 224-2B responds to any of the other processor nodes PN2-PN8 (20-80). To the remote cache access request. In this manner, access requests to the remote cache 224 can be processed in parallel.

The operation of the above-structured distributed shared memory multiprocessor system having the direction-separated dual ring structure of the present invention will be described in detail with reference to FIGS.

The data blocks stored in the remote cache 224 have four states: "Modified", "Modified-Shared", "Shared", and "Invalid (I
nvalid) "state. Each of the four states is described as follows. * Update: The data block is valid and updated, and is the only valid copy. * Update-Share: The data block is valid and updated, and another remote cache shares the data block. Can be. * Sharing: The data block is valid and another remote cache can share the data block. * Invalid: The corresponding data block is not valid.

Also, in the multiprocessor system according to the present invention, the first and second memory directories 226A and 226B maintain one of three states, namely, C (clean), S (share), and G (gone). This minimizes the amount of cache coherent traffic that responds to local shared memory access requests via the local system bus 218, reduces unnecessary transactions to the direction-separated dual ring buses 90A and 90B, and reduces Effectively handles demands, directional separation double ring bus 90A and 90B
Generates a snooping result that responds to the snooping request by. The details of these three states will be described below. * C (Clean): The data block is not stored in a valid state in any remote cache of another processor node. * S (Shared): The corresponding data block is valid and can be stored in a valid state that is not updated in any remote cache of another processor node. * G (Gone): The corresponding data block is not valid and is stored in a valid state updated in any remote cache of another processor node.

On the other hand, each of the processor nodes PN1 to PN8 (10 to 8
All communication on the direction-separating dual ring buses 90A and 90B that sequentially connect 0) are configured via packets, and the packets can be classified into request packets, response packets, and recognition packets. The request packet is a packet that is sent by any of the processor nodes PN1 to PN8 (10 to 80) that require a transaction to the direction-separating dual ring bus 90A and 90B, and is a broadcast packet. And a single communication packet. Of these, only broadcast packets are snooped by other processor nodes.

The response packet is always singly communicated by the processor node receiving the request packet. When the recognition packet is generated by the processor node that has received the response packet, it is singly communicated to the processor node that transmitted the response packet. A processor node that has communicated a single response packet maintains the response packet until a recognition packet corresponding to the response packet is received. According to another embodiment of the present invention, a case where a processor node that has single-communicated a response packet receives another request packet for the same data block from another processor node before receiving a recognition packet corresponding to the response packet Can request that the processor node retransmit the request packet, if necessary.

Referring to FIGS. 5 and 6, an exemplary operation of the distributed shared memory multiprocessor system is shown.

In the first case, the processor node PN1 (1
In the case where the first processor module 212 in (0) generates a read request for a data block, the request packet is
RQ12. If the corresponding data block corresponds to the remote shared memory and is not stored in a valid state in the remote cache 224 of the PN1 (10), the PN1 (10) is stored in the ring bus 90A or 90.
RQ1 to other processor nodes PN2-PN8 (20-80) via B
Broadcast 2 The data block corresponds to the local shared memory 220, but the local shared memory 2
If not stored in a valid state at 20, PN1 (10) is connected to another processor node via ring bus 90A or 90B.
RQ12 is reported to PN2 to PN8 (20 to 80). In this case, if the corresponding data block is an odd block, RQ12 is the first
If the data block is transmitted via the link controller 230A and the first link bus 90A and the data block is an even block, RQ12
Is transmitted via the second link controller 230B and the second ring bus 90B.

As a result, RQ12 for odd blocks
Circulates from PN2 (20) to PN8 (80) in the counterclockwise direction along the first ring bus 90A, as shown in FIG. On the other hand, RQ12 for the even-numbered block circulates clockwise from PN8 (80) to PN2 (20) along the second ring bus 90B as shown in FIG. While the RQ12 circulates along the ring bus 90A or 90B, each processor node checks the internal remote cache or memory directory in response to the RQ12 and performs snooping on the state of the corresponding data block and the like. At the same time, the RQ12 is bypassed to the next adjacent processor node.

For example, when RQ12 is supplied to PN4 (40), P
The node controller of N4 (40) snoops the remote cache and memory directory in PN4 (40). As a result, the corresponding data block is updated in the remote cache of PN4 (40).
Or, if stored in the "update-shared" state, PN4
The node controller of (40) determines that it is responsible for responding to RQ12. In this case, there is no processor node that stores the data block in the local shared memory in a valid state.

As a result, the node controller of the PN4 (40) transmits the response packet RSP42 including the corresponding data block to the PN1 (10) along the first ring bus 90A or the second ring bus 90B having the path closest to the PN1. A single communication. Also, PN4 (40)
Causes the remote cache state of PN4 (40) to change to a valid state that has not been updated, such as an "update-shared" or "shared" state.

If the corresponding data block is stored in a valid state in the local shared memory of PN4 (40), the PN4
The node controller of (40) takes responsibility for the response to RQ12,
The response packet including the data block is transferred to the first ring bus 90A or the second ring bus 9 having the route closest to PN1.
It transmits to PN1 (10) via 0B. Therefore, FIGS. 5 and 6
The PN4 (40) transmits the response packet RSP42 via the second ring bus 90B having the closest route to the PN1 (10).

At this time, the read request packet RQ12 is removed by the PN1 (10) after completing the tour. On the other hand, R
After receiving SP42, the processor node PN1 (10) has the first ring bus 90A or the second ring bus 90B having the closest path to the processor node PN4 (40), that is, the first ring bus 90A in FIGS. 5 and 6. Acknowledgment packet ACK14 via PN4 (40)
At the same time, the corresponding data block in the RSP 42 is transmitted to the first processor module 212 which issues a read request for the corresponding data block via the local system bus 218 of the processor node PN1 (10). If the data block corresponds to the remote shared memory, PN1
(10) stores the relevant data block in the remote data cache 224-1 in a valid state, and at the same time, updates the state of the remote tag cache 224-2 corresponding to the relevant data block to a valid state, and the relevant data block is If it corresponds to the shared memory 220, PN1 (10)
At the same time, the state of the memory directory 226 is updated to a state meaning that another processor node shares the corresponding data block, for example, the “S” state.

On the other hand, in the second case, the first in PN1 (10)
In this case, the processor module 212 issues a write request. In this case, FIGS. 5 and 6 are still valid, and the request packet at this time is also assumed to be RQ12 for simplicity. PN1
If (10) does not store the corresponding data block for the write request in a valid state anywhere in the remote cache 224 or the local shared memory 220, PN1 (10) will connect to another processor node PN2 via the ring bus 90A or 90B. ~ PN8 (20 ~ 80)
To RQ12. In this case, if the data block is an odd block, RQ12 is transmitted via the first ring bus 90A as shown in FIG. On the other hand, if the data block is an even block, RQ12 is
As shown in FIG. 6, the write request packet RQ12 transmitted via the second ring bus 90B is transmitted to the ring bus 90A or 90B.
While traversing through, each processor node responds to RQ12, checks the internal remote cache or memory directory, performs snooping on how the corresponding data block is stored, etc. To the next adjacent processor node.

For example, when RQ12 is supplied to PN4 (40), P
The node controller of N4 (40) snoops the internal remote cache and memory directory. As a result, whether the corresponding data block is stored in the PN4 (40) remote cache in an updated state, for example, in the `` update '' or `` update-shared '' state (in this case, the corresponding block is valid If the corresponding data block is stored in a valid state in the local shared memory, the node controller of PN4 (40) assumes responsibility for the response to RQ12. Response packet RS containing the data block requested to be determined to have
P42 is the first ring bus 90A having the path closest to PN1 (10)
Alternatively, the signal is transmitted via the second ring bus 90B. Figures 5 and 6
, The PN4 (40) transmits the response packet RSP42 via the second ring bus 90B having the closest route. Also, the node controller of PN4 (40) invalidates the state of the remote cache storing the corresponding data block,
For example, the state is changed to the “invalid” state or the state of the memory directory is invalidated, for example, updated to the “G” state. The write request packet RQ12 is transmitted to the ring bus 90A.
Alternatively, after circulating through 90B, it is removed by the processor node PN1 (10).

On the other hand, as a result of the snooping, the corresponding data block is connected to another processor node, that is, PN2 to PN3 (20 to 30).
If the remote cache of PN5-PN8 (50-80) is found to be stored in a valid state that has not been updated, e.g., in a `` shared '' state, the processor node, i.e., PN2-PN3 (20
30) and the remote cache state of PN5 to PN8 (50 to 80) are changed to an invalidated state, for example, an "invalid" state.

When PN1 (10) receives RSP42 from PN4 (40), PN1 (10) receives the first ring bus 90A having the path closest to PN4 (40).
Alternatively, the recognition packet ACK14 is sent to the PN4 (40) via the second ring bus 90B, for example, the first ring bus 90A in the case of FIGS. 5 and 6.
And the corresponding data block is transmitted to the processor module 212 which generates the write request via the local system bus 218 of the processor node PN1 (10). If the requested data block corresponds to the remote shared memory, PN1 (10) stores the remote data cache 2
If the corresponding data block is stored in the modified valid state, for example, "updated" state in 24-1 and the corresponding data block corresponds to the local shared memory 220, the PN1 (10) stores the corresponding data block in the local shared memory 220. At the same time, the state of the memory directory 226 is updated to a state meaning that the remote cache of another processor node does not share the corresponding data block, for example, the “C” state.

On the other hand, in the third case, the first in PN1 (10)
FIG. 5 illustrates a case where the processor module 212 generates a write request or an invalidation request for a data block.
6 is still valid in this case as well, and for convenience of explanation, the request packet is again represented by RQ12 in this case.

If PN1 (10) stores the corresponding data block in the valid state in the remote cache 224, for example, in the "shared" state, the request process is such that PN1 (10) stores the corresponding data block in the remote cache 224. This is performed in the same manner as when the data is not stored in a valid state anywhere in the local shared memory 220.

On the other hand, in FIG. 5 and FIG.
In response to a write request or invalidation request from any of the processor modules 212 and 214 of 1 (10), the processor node PN1 (10) stores the corresponding data block in the local shared memory 220 in a valid state, Alternatively, when the corresponding block is stored in the remote cache 224 in the “update-shared” state, the processor node PN1 (10)
An invalidation request packet is broadcast to the other processor nodes PN2 to PN8 (10 to 80) via A or the second ring bus 90B. At this time, if the data block is an odd block, an invalidation request is broadcasted via the first ring bus 90A as shown in FIG. On the other hand, if the data block is an even block, as shown in FIG.
An invalidation request is broadcast via the second ring bus 90B. While the request packet RQ12 circulates around the ring bus 90A or 90B, each of the processor nodes PN2 to PN8 (20 to 80)
In response to RQ12, the internal remote cache or memory directory is checked to perform snooping on the state of the corresponding data block and the like, and at the same time, RQ12 is transmitted to the next next processor node as described above. Bypass. The RQ12 is removed by the processor node PN1 (10) after traveling around the ring bus. On the other hand, if the result of snooping indicates that the corresponding data block is stored in a valid state that has not been updated in the remote cache of another processor node, that is, PN2 to PN8 (20 to 80), for example, in a `` shared '' state, , The state of the remote cache of PN4 (40) changes to an invalidated state, for example, an "invalid" state. When the corresponding data block corresponds to the remote shared memory, PN1 (10) updates the state of the corresponding data block stored in the remote data cache 224-1, for example,
When the state is changed to the "update" state and the corresponding data block corresponds to the local shared memory 220, PN1 (10) indicates that the state of the memory directory 226 is not shared by the remote cache of another processor node. Status,
For example, update to the “C” state.

In the fourth case, the processor node PN1 (1
This is the case where the state of the data block extracted by the data block replacement in the remote cache 224 of 0) is an updated state, for example, an “update” or “update-shared” state. In this case, PN1 (10) is extracted via a processor node having a local shared memory in which the corresponding data block should be originally stored, for example, via a ring bus 90A or 90B having a path closest to PN4 (40). Communicate a single packet containing a block. Then, PN4 (40)
Updates the internal data memory and memory directory in response to RQ12, and sends a response packet RSP42 to the first ring bus 90A.
Alternatively, single communication is performed with PN1 (10) via the second ring bus 90B. The PN1 (10) performs a single communication of the recognition packet ACK14 to the PN4 (40).

On the other hand, according to the preferred embodiment of the present invention, the processor node, for example, PN1 (10) can process requests for one or more data blocks according to the input order of applied packets. For example, before a response packet for a requested data block is received from the corresponding processor node, i.e., PN4 (40), a request packet for another data block is
When transmitted from one or more of the nodes 2 to PN8 (20 to 80), the processor node PN1 (10)
The operation corresponding to the response packet to the requested data block is performed according to the number of operations performed on the request packet transmitted from one or more of 8 (20 to 80).

Referring to FIGS. 7 to 10, there is shown another embodiment of a processor node used in the multiprocessor system having the direction-separated dual ring structure shown in FIG. 3 according to the present invention.

FIG. 7 shows a detailed view of the processor node 200-1 according to the second embodiment of the present invention. As shown in FIG.
The configuration of the processor node 200-1 is similar to that of the embodiment of the present invention shown in FIG. 4 except that the first link controller 230A and the second link controller 230B are directly connected to the node controller 222 without the link bus 228. This is the same as the configuration of the processor node according to 1.

FIG. 8 shows in detail a processor node 200-2 according to Embodiment 3 of the present invention. The configuration of the processor node 200-2 is such that the processor node 200-2 does not include the local shared memory and the memory directory. Other than that,
This is the same as the configuration of the processor node according to the first embodiment of the present invention shown in FIG.

FIG. 9 shows the details of the processor node 200-3 according to the fourth embodiment of the present invention.
Is the same as the configuration of the processor node according to the first embodiment of the present invention shown in FIG. 4 except that the processor node 200-3 does not include the remote cache.

FIG. 10 shows the details of the processor node 200-4 according to the fifth embodiment of the present invention.
4 is different from the embodiment 1 of the present invention shown in FIG. 4 except that the internal processor modules are connected to each other via some interconnection network 240 such as a ring or a crossbar switch instead of the local system bus. Is the same as the configuration of the processor node.

The structure of the embodiment shown in FIGS.
Since the configuration is almost the same as that of the embodiment, the description of the operation is omitted for convenience. According to the invention, the processor node PN
Each of 1 to PN8 (10 to 80) can be realized via a processor node having a configuration selected from FIGS.

Further, in the above description, the case where the remote cache has the "update" and "update-shared", "shared", and "invalid" states has been described. The present invention can be similarly applied to various cases including the case of having. In the embodiment of the present invention, the case where the directory for the local shared memory maintains the states of "C", "S", and "G" has been described. However, the present invention is applicable to various other states in which the directory is changed. It must be understood that the same can be applied when having.

In the above-described embodiment of the present invention, a case has been described where a response packet to a broadcast request packet and a recognition packet are transmitted via the first ring bus 90A or the second ring bus 90B having the shortest path. ,
According to the present invention, a response packet and a recognition packet for a broadcast request transmitted via the first ring bus 90A are transmitted via the first ring bus 90A, and the broadcast transmitted via the second ring bus 90B. The response packet to the request and the recognition packet are transmitted via the second ring bus 90B,
First ring bus 90A or second ring bus 90B in a predetermined order
It is clear that the same applies to the case where the response and the recognition packet are transmitted via the.

[0052]

Thus, according to the present invention, a distributed shared memory multiprocessor system can not only maintain cache coherency between processor nodes by using a snooping scheme, but also reduce ring bandwidth by two.
This provides an effect of providing further improved performance as compared with an existing system having a unidirectional ring bus doubled.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a distributed shared memory multiprocessor system having a snooping type single ring according to the related art.

FIG. 2 is a detailed configuration diagram of a processor node shown in FIG. 1;

FIG. 3 is a block diagram of a distributed shared memory multiprocessor system with a direction-separating dual ring according to the present invention;

FIG. 4 is a detailed configuration diagram of a processor node shown in FIG. 3 according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating an operation of the distributed shared multiprocessor system according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation of the distributed shared multiprocessor system according to the first embodiment of the present invention.

FIG. 7 is a detailed configuration diagram of a processor node shown in FIG. 3 according to a second embodiment of the present invention.

FIG. 8 is a detailed configuration diagram of a processor node shown in FIG. 3 according to Embodiment 3 of the present invention.

FIG. 9 is a detailed configuration diagram of a processor node shown in FIG. 3 according to Embodiment 4 of the present invention.

FIG. 10 is a detailed configuration diagram of a processor node shown in FIG. 3 according to Embodiment 5 of the present invention.

[Explanation of symbols]

 90A: First ring bus 90B: Second ring bus 212: First processor module 214: Second processor module 216: I / O bridge 218: Local system bus 220: Local shared memory 222: Node controller 224: Remote cache 224 -1: Remote data cache 224-2: Remote tag cache 224-2A: First remote tag cache 224-2B: Second remote tag cache 226: Memory directory 226A: First memory directory 226B: Second memory directory 228: Link Bus 230: Ring interface 230A: First link controller 230B: Second link controller

 ──────────────────────────────────────────────────続 き Continuing from the front page (71) Applicant 500170526 Kim Myeong-il, 206-304, Junggye-dong Municipal Apartment, Luwon-gu, Seoul, Korea (72) Inventor Zhang Xingtai 1 Jeongneung, Seongbuk-gu, Seoul, Korea 1015-dong Gyeongnam Apartment 103-1701 (72) Inventor Jeong-suk-po Korea 1-1, Dook-dong, Gangnam-gu, Seoul Special Apartment 1-103 (72) Inventor Kim Myeong-gil Junggye-dong, Awon-gu, Seoul, Republic of Korea Municipal apartment 206-304 F term (reference) 5B005 JJ01 KK14 MM01 NN53 PP21 PP26 5B045 BB13 BB17 BB24 BB28 BB29 BB47 DD01 DD12 GG01 5B060 KA01 KA06

Claims (13)

[Claims] 1. A distributed shared memory multiprocessor system, comprising: a plurality of processor nodes arranged in a ring, wherein one of the plurality of processor nodes generates a request signal for one data block; The remaining processor nodes snooping their own internal elements, the plurality of processor nodes supplying any of the data blocks among the remaining processor nodes, and the first and second ring buses; There is a direction-separated dual ring structure that provides two opposite paths along a two-ring bus, the plurality of processor nodes are connected via the first and second paths, and the request signal is To each of the remaining processor nodes, the data block being routed through any of the paths. Distributed shared memory multiprocessor system comprising: a said direction separated dual ring structure is a single communication to the processor node that generated the request signals. 2. The request signal is transmitted through the first ring bus or the second ring bus depending on where the data block is stored in an even or odd memory block address of an internal element of the plurality of processor nodes. 2. The distributed shared multiprocessor system according to claim 1, wherein the distributed shared multiprocessor system is transmitted. 3. A request signal for a data block different from the data block from at least one of the remaining processor nodes before the processor node that generated the request signal receives a corresponding signal corresponding to the request signal. Upon receipt, the processor node first performs an operation corresponding to a request signal transmitted from at least one of the remaining processor nodes, and then processes an operation corresponding to the response signal. 2. The distributed shared memory multiprocessor system according to 1. 4. Each of the plurality of processor nodes generates a request signal for the data block, a plurality of processor modules, a local shared memory storing a data block shared by each of the plurality of processor modules, In response to the request signal, investigate whether the data block corresponding to the request signal is stored in a valid state in the local shared memory, and store the data block in a valid state in the local shared memory. If the data block is not stored in the local shared memory in a valid state, the request signal is transmitted to the plurality of processor nodes. System that supplies the next processor node next to A link controller for interfacing the node controller with the direction-separating dual ring structure; and an interconnection network for interconnecting the plurality of processor modules, the local shared memory, and the node controller. 2. The distributed shared memory multiprocessor system according to claim 1, wherein 5. Each of the plurality of processor nodes includes: a plurality of processor modules for generating the request signal for the data block; a remote cache; and a data corresponding to the request signal in response to the request signal. Investigate whether a block is validly stored in the remote cache and, if the data block is validly stored in the remote cache, communicate the data block to the plurality of processor modules. And if the data block is not stored valid in the remote cache, the node controller supplies the request signal to an adjacent next processor node among the plurality of processor nodes. Link controller for interfacing a controller with the direction-separated dual ring structure , Distributed shared memory multiprocessor system according to claim 1, characterized in that it comprises an interconnect network interconnecting said plurality of processor modules and local shared memory and a node controller. 6. Each of the plurality of processor nodes includes: a plurality of processor modules for generating the request signal for the data block; a local shared memory for storing a data block shared by each of the plurality of processor modules; In response to the request signal, investigate whether the data block corresponding to the request signal is stored in the remote cache or the local shared memory in a valid state. Transmitting the data block to the plurality of processor modules, if the data block is validly stored in the remote cache or the local shared memory, the data block being valid in the remote cache or the local shared memory; Not stored in A node controller that supplies the request signal to an adjacent next processor node among the plurality of processor nodes; a link controller that interfaces the node controller and the direction-separated dual ring structure; 2. The distributed shared memory multiprocessor system according to claim 1, further comprising an interconnection network interconnecting the processor modules, the local shared memory, and the node controllers. 7. The distributed shared memory multiprocessor system according to claim 4, wherein each of the plurality of processor nodes further includes a memory directory including status information on data blocks stored in the local shared memory. . 8. The memory directory having two or more independent memory directories to process access requests to the local shared memory from the processor module and the remaining processor nodes in parallel. The distributed shared memory multiprocessor system according to claim 7, wherein 9. The remote cache includes a remote data cache including contents of the data block, and a remote tag cache storing a tag address and a status of the data block stored in the remote data cache. Claim 5 or Claim 6
3. The distributed shared memory multiprocessor system according to item 1. 10. The remote tag cache having two or more independent remote tag caches to process access requests to the remote cache from the processor module and the remaining processor nodes in parallel. 10. The distributed shared memory multiprocessor system according to claim 9, wherein: 11. The link controller according to claim 1, further comprising a first link controller and a second link controller connecting the first ring bus and the second ring bus to the node controller, respectively. 7. The distributed shared memory multiprocessor system according to any one of claims 4 to 6. 12. The first link controller and the second link controller each generate a packet including the request signal and the data block, thereby generating a corresponding ring bus connected to each controller. Transmitting the packet to the remaining processor node via the corresponding ring bus and selectively supplying the request or data block supplied from the remaining processor node via the corresponding ring bus to the node controller. Item 12. The distributed shared memory multiprocessor system according to item 11. 13. The distribution system according to claim 12, wherein each of the processor nodes further includes a link bus connecting the node controller to the first link controller and the second link controller. Shared memory multiprocessor system.