JP2001221836A - Testing apparatus and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a higher trouble coverage with a shorter test length by reducing the number of necessary hardwares. SOLUTION: Original test vectors stored in an ROM 4 are shifted alternately into two shift registers SR-A2 and SR-B3 on a vector basis. The vectors in the shift registers SR-A2 and SR-B3 are shifted into multiplexers MUX5-1, 5-2 and 5-3 alternately together with pseudo random vectors generated by an LFSR1, to be mutually multiplexed. The multiplexed vectors are mixed vectors, and are printed to a CUT6 separately from the multiplexers MUX5-1, 5-2 and 5-m.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus and method, and more particularly, to a test apparatus and method of an integrated circuit for detecting a fault occurring in an integrated circuit, for example, a delay fault.

[0002]

2. Description of the Related Art In recent years, as the logical scale of LSIs (Large Scale Integrated Circuits) has increased, VLSIs (Very Large Scale Integrated Circuits)
Integrated circuits referred to as are widely used. In general, as the scale of an integrated circuit becomes larger and more complex, the number of circuit portions that are difficult to access from external terminals increases dramatically. Therefore, a failure of a large-scale and complicated integrated circuit, that is, a VLSI is detected. Testing is difficult. For this reason, with the increase in the scale of the VLSI, various measures have been taken to reduce the time required for the test for detecting a failure or the like of the VLSI, reduce the cost, and improve the quality.

[0003] VLSI failures include, for example, delay failures (delay failures) and stuck-at failures. The delay failure is a failure in which the delay characteristic (AC characteristic) of the circuit is different from the expected one. As the delay fault, the logical value is 0
From 1 to 0, also from 1 to 0, a gate delay fault that slows down the operation speed of a specific element inside the circuit, and a signal propagation along a specific path inside the circuit. Delayed path delay faults are known. These failures cause the operating speed of the circuit to deviate from the expected speed. Further, a stuck-at fault is a fault in which a certain signal line inside a circuit is fixed to a certain specific value. The stuck-at fault includes a stuck-at-0 fault whose logic value is fixed at 0 and a stuck-at-1 fault whose logic value is also fixed at 1.

As one effective method for detecting a failure occurring in these VLSIs, a BIST (Built-In S
elf-Test) (hereinafter referred to as BIST method) has been proposed (S. Runyon, “Testing big chi
p becomes an internal affair, ”IEEE Spectrum, vo
l. 36, no. 4, pp. 49-55, Apr. 1999., Y. Zorian,
“Testing the monster chip,” IEEE Spectrum, Vol.
36, no. 7, pp. 54-60, July. 1999., Y. Zorian, E.
J. Marinissen, and S. Dey, “Testing embedded-core
-based system chips, ”IEEE Computer, Vol. 32, no.
6, pp. 52-60, June.1999.). FIG. 11 shows a configuration diagram of the BIST system. The BIST circuit 100 includes, for example, a test pattern generator 101, a circuit under test 102, an output pattern compressor 103, an expected value storage unit 104, and a comparator 105.

The outline of the BIST system will be described below. The test pattern generator 101 generates a random pattern test pattern of logical values 0 and 1. This test pattern is input to the circuit under test 102. The output value of the circuit under test 102 corresponding to the test pattern is sequentially compressed by the output pattern compressor 103. The final value of the sequentially compressed output value and the expected value stored in the expected value storage unit 104 are compared by the comparator 105, and the circuit under test 1
02 is detected.

In the BIST system, in addition to cost reduction of test equipment, improvement of test quality at actual operating speed can be expected. The test pattern generator 101 described above,
That is, the test pattern generation circuit for BIST (TPG: T
As an est pattern generator), it is desirable that a high fault coverage can be achieved with a small amount of hardware and a test length (test time) is as short as possible. The fault coverage is a measure of the quality of the test, and is expressed as: fault coverage = number of detected faults / (number of possible faults−number of redundant faults). Note that a redundant fault is a fault in which no detectable test vector exists.

[0007]

In the conventional BIST system, an automatic test pattern generation circuit (ATPG: Au
When using a test pattern generator (TPG) in which all test patterns obtained by the tomatic test pattern generator) are stored in ROM, 10
It is possible to achieve 0% fault coverage. However, the required hardware increases. Also, when a TPG that generates a pseudo random pattern using an LFSR (Linear Feedback Shift Register) is used, the required hardware is reduced. However, the circuit under test 102 described above, that is, the CUT (Circuit
Under Test), random pattern detection difficult (rpr:
If a random pattern resistant fault exists, 1
Achieving 00% fault coverage requires very long test lengths (M. Lempel, SK Gupta, an
d MA Breuer, “Test embedding with discrete log
arithms, ”in Proc. ofVLSI Test Symposium, pp .74-
80, Apr. 1994.).

On the other hand, in the BIST system for testing a stuck-at fault, various techniques have been proposed to shorten the test length. For example, a testability design method (HHS Gundlac, in which observation points are inserted into the CUT to reduce the number of rpr faults)
h and KD Muller-Glaser, “On automatic testpoint
insertion in sequential circuits, ”in Proc. of I
nternational Test Conference, pp. 1072-1079, Sept.
1990., M. Nakao, S. Kobayashi, K. Hatayama, K. Ii
jima, and S. Terada, “Low-overhead testpoint inse
ction for scan-based BIST, ”in Proc. of Internati
onal Test Conference, pp. 348-357, Sept. 1999.).

Also, a weighted pseudo-random pattern method (J. Sav.)
ir, “On chip weighted random patterns,” in Proc.
ofAsian Test Symposium, pp. 344-352, Nov. 199
7.), a bit fix method that fixes a specific logical value in a certain bit position (MF AlShaibi and CR Kime,
“MFBIST: A BIST method for random pattern resista
nt circuits, ”in Proc. of International Test Confe
rence, pp. 176-185, Oct. 1996., G. Kiefer and H.
J. Wunderlich, “Deterministic BIST with multiple
scan chains, ”in Proc. of International Test Conf
erence, pp. 1057-1064, Oct. 1998., C. Fagot, O. Gas
cuel, P. Girard, and C. Landrault, “A ring archit
ecture strategy for BIST test pattern generatio
n, ”in Proc. of Asian Test Symposium, pp. 418-423,
Dec. 1998.) and a bit flipping method that slightly changes the bit position of invalid patterns (G. Kiefe and H.
J. Wunderlich, “Using BIST control for pattern ge
nearation, ”in Proc. of International Test Confer
ence, pp. 347-355, Nov. 1997.) and a method to reseed the initial values of LFSR and counters (S. Hellebrand,
J. Rajski, S. Tarnick, S. Venkataraman, and B. Cou
rtois, “Built-in test for circuits with scan base
d on reseeding of multiple-polynomial linear feedb
ack shift resisters, ”IEEE Trans. on Computer, Vo
l. 44, no. 2, pp. 223-233, Feb. 1995., K. Chakraba
rty, BT Murray, and V. Tyengar, “Built-in test
pattern generation for high-performance circuits
using twisted-ring counters, ”in Proc. of VLSI Te
st Symposium, pp. 22-27, Apr. 1999.).

Further, a BIST TP using a vector obtained by ATPG (hereinafter, ATPG vector)
G has also been proposed (T. Asakawa and K. Iwasaki, “O
n using ATPG vectors for BIST TPG, ”The first IEE
E Asia Pasific Conferenceon ASICs, pp. 359-362, Au
g. 1999.). A logic synthesis method that can be easily tested with random patterns has also been proposed (NA Touba and EJ Mc
Cluskey, “RP-SYN: Synthesis of random pattern tes
table circuits with Test Point Insertion, ”IEEE T
rans. on Computer., Vol. 18, no.8, pp. 1202-121
3, Aug. 1999.).

Here, detection of a transition fault will be described as an example of a delay fault. The state transition of the target test location included in the circuit under test is tested according to the following procedure. First, when the state transits from the logical value 0 to 1, the following procedures 1 and 2 are continuously performed. Step 1: Input an input vector such that the state of the test location becomes 0 (initialization is performed). Step 2: An input vector is input so that the state of the test location changes (in this case, the logical value becomes 1).

On the other hand, when the state transits from the logical value 1 to 0, the reverse procedure is similarly taken. That is, Procedure 1: Input an input vector such that the state of the test location becomes 1 (initialization is performed). Step 2: An input vector is input so that the state of the test location changes (in this case, the logical value becomes 0).

Therefore, detection of a transition fault requires two vector sequences before and after a transition, respectively. The vector sequence is a continuous vector set having both vector values and meanings (the test pattern is also one of the vector sequences).
In detecting a transition fault requiring two consecutive vector sequences in this way, it is more difficult to detect an rpr fault than to detect a stuck-at fault.

Therefore, a method of exchanging the initial value of LFSR and a polynomial as a BIST for executing a test for a delay fault (X. Li and PYS Cheung, “Exploiting BIST”).
approach for two-pattern testing, ”in Proc. of
Asian Test Symposium, pp.424-429, Dec. 1998., K. F
ukuya, S. Yamazaki and M. Sato, “Evaluations ofvar
ious TPG circuits for use in two-pattern testin
g, ”in Proc. of Asian Test Symposium, pp. 242-24
7, Nov. 1994.), a method for testing delay faults at actual operating speeds (A. Kristic et al., “Testing high s
peed VLSI devices using slower testers, "in Proc.
of VLSI Test Symposium, pp. 16-21, Apr. 1999.). In these methods, the number of vector sequences effective for fault detection can be increased in a test pattern. However, achieving 100% delay fault coverage requires very long test lengths.

In view of the above, it is an object of the present invention to provide a method and an apparatus for testing an integrated circuit which require less hardware and can achieve a high fault coverage with a short test length. Further, although a test pattern is conventionally generated by LFSR, an object of the present invention is to generate a test pattern by mixing a pseudo random pattern from LFSR or the like and a pattern from a storage unit.
As a result, the present invention aims to significantly reduce the number of test patterns (test time), although the hardware is slightly increased. A further object of the present invention is to reduce the number of patterns stored in the storage unit by employing the algorithms "head position selection method" and "sampling method".

[0016]

According to a first aspect of the present invention, a storage unit storing a first test vector sequence for testing a state transition, and a first test vector sequence stored in the storage unit are stored. A test vector sequence is divided and input into first and second vector units, respectively, and first and second vector generators that output the first and second vectors, respectively, and a third that outputs a pseudo-random vector. And the outputs from the first and third vector generators are mixed together, and the outputs from the second and third vector generators are mixed together, so that the second test vector sequence And a multiplexing unit that outputs the data to a circuit under test.

According to a second solution of the present invention, a first test vector sequence for testing a state transition is a first test vector sequence.
And storing by dividing the first vector and the pseudo-random vector, and outputting the second vector and the pseudo-random vector in a mixed manner. And generating the test vector sequence and outputting the test vector sequence to the circuit under test.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Overview As the delay fault, a transition fault, a gate delay fault, a path delay fault, and the like are known. In the present invention, transition faults are the main target of the test, and fault coverage excluding redundant faults is used as a measure of test quality.
coverage).

In order to detect a transition failure,
Two consecutive test vector sequence (second pattern vector sequences) _{v i,} v i + ₁ must be entered. 2
In the pattern test, the arrangement of vectors is also important. 0 a signal line with internally by test vector v _i
Or set to 1. The signal line is transited to the opposite polarity by the subsequent vi _{+ 1} , and at the same time, the primary output (primary output)
output). v _i or _{v i + 1}
May be replaced with a random pattern.

The number of inputs of the circuit under test (CUT) is m,
The target transition fault is defined as ft (t = 1, 2,.
N), a vector that can detect the target transition fault ft
A set of pairs is represented as S (ft). 2 random patterns
The probability P (ft) that ft can be detected by the vector is P (ft) = | S (ft) | / (2^m× 2^m) It can be expressed as. Now, to explain this formula,
An m-bit wide vector has 2 m combinations. So
Therefore, the combination of two consecutive vectors is 2 ^m× 2
^mThere will be. The denominator is
Shows the total number of combinations. On the other hand, the molecule
Number of vector combinations effective for fault detection among combinations
Is shown. Therefore, the larger the molecule, the more detection
The number of valid vector combinations is large, that is,
Means that it is easy to detect
You. That is, as P (ft) is smaller, the random vector
, The probability of detecting ft decreases. P (ft) is small
Failure ft is a transition that makes random pattern detection difficult
(Rpr transition) Called a failure.

The set consisting of the entire binary m-dimensional vector is
V_mIt expresses. V_mThe sequence of length | V |₀, V₁, V₂,. . . , V_{| V | -1}  It expresses.

For the circuit C, an operation for obtaining a test vector sequence for a transition fault using an automatic test pattern generation circuit (ATPG) tool is performed by the ATPG.
(C) and represents, represents a sequence of the resulting n m-dimensional vector and V _c. n = | V _c |. Two pattern vector sequences (v ₀ , v ₁ ), (v ₁ , v ₂ ),. . . , _{(V n
-2} , vn _-1 ), a transition fault is detected. Fault efficiency achieved with V _c (the fault coverage) is defined as ATPG detection efficiency (ATPG coverage).

The function SIM (C, V) is given by
A fault simulation using the vector sequence V is performed to obtain a fault coverage. Function COVER (C, V)
Is a vector sequence V (= v ₀ ,
v ₁ ,. . . , _{V | V | -1)} performs a fault simulation using a subsequence of V that ATPG coverage is used to achieve a _{100% V '(= v 0} ,
v ₁ ,. . . , V _{| V '| -1} ). The function to V _c, is used to determine the smaller V '. Function ADD1 (V) is used to generate a pseudo-random vector _{v r} a mixed vector sequence ^{V *} generated by LFSR (Linear Feed-back Shift Register ) with respect to the vector sequence V. This operation is called pattern addition and is performed under the following conditions.

[0024] (1) to add a vector _{v i} per j number of vectors of V. The j / 2 or pseudo-random vectors _{v r,}
v _i to j / 2 pieces added. (J + 1) × | V
| Pattern appears. (2) adding a pseudo-random vector _{v r} and _{v i} are alternately.

FIG. 1 shows a pattern by the function ADD1 (V).
An example (j = 8) is shown. v_iNotice that j /
2 = 4 pseudorandom vectors v_rAnd j / 2 = 4
v_i, And a vector consisting of j = 8 vectors
Tor series (v_r, V_i, V_r, V_i, V_r, V_i,
v_r, V_i). Similarly v_{i + 1}Against
Tor series (v_r, V_{i + 1}, V_r, V_{i + 1}, V_r, V
_{i + 1}, V_r, V_{i +1}), V_{i + 2}Then (v_r, V
_{i + 2}, V_r, V_{i + 2}, V_r, V_{i + 2}, V _r, V
_{i + 2}). As a result, the vector sequence V^*No
The number of vectors is 9 × j.

FIG. 2 shows an example of pattern generation for a benchmark circuit. In this example, a circuit under test having a 5-bit input is assumed, and the original ATPG vector is 5 bi.
At t, (11001, 01111, 01100), j = 20 patterns are added to each. The function ADD ^-1 (V ^* ) obtains the original vector series V from the vector series V ^* generated by the function ADD1 (V). For example, in FIG. 1, ADD ^-1 (V ^* ) = V =. . . _{, V i, v i + 1} , v
_{i + 2,.} . . Becomes

2. Configuration of Test Pattern Generation Circuit (TPG) FIG. 3 shows a test pattern generation circuit (TP) according to the present invention.
G) shows an example of a configuration diagram. TPG10 is LFSR
(Third vector generation unit) 1 and a shift register (SR
_A, SR_B) (first and second vector generation units) 2
And 3, a storage unit (ROM) 4, and a multiplexer (M
UX) (multiplexing unit) 5-1 5-2, and 5-m.
The LFSR 1 has a plurality of flip-flops inside, and some of the outputs of the flip-flops are selectively subjected to exclusive OR (EXO) so that linear feedback is applied.
R) to generate a pseudo-random pattern.

Each control signal / clock in the figure has the following role. The clock ck_L indicates the clock of the LFSR, and similarly, the clock ck_A indicates the shift-in clock of the SR_A, and the clock ck_B indicates the shift-in clock of the SR_B. Also, the control signals SA, S
B and SL represent enable signals of inputs A, B and L to the multiplexers MUX5-1, 5-2 and 5-m, respectively. The ROM 4 stores the original test vector sequence. The test vector stored in the ROM 4 is
Two shift registers SR_A2 alternately in vector units
And SR_B3. Shift register S
The vectors of R_A2 and SR_B3 are alternately provided to the multiplexers MUX5-1, 5-2, and 5-m and multiplexed with the pseudorandom vectors generated by the LFSR1. The multiplexed vector sequence is a vector sequence obtained by mixing a pseudo random vector and an ATPG vector, and is a multiplexer MUX5-1, 5-2.
And 5-m are applied to the CUT 6 respectively.

FIG. 4 shows an example of an explanatory diagram of test pattern generation by TPG according to the present invention. Here, as an example, the number of inputs m = 2 in the CUT, the vector _{v i, v} i _{+ 1}
Is stored in the ROM and j = 8 is assumed. In this case, it appears pseudo-random vector _{v r} is j / 2 (= 4) times by vector per LFSR stored in ROM. With reference to the test clock frequency, MUX 5-1 and 5-
The control signals SA, SB, SL of No. 2 have a half frequency. Clock c of SR_A2, SR_B3, LFSR1
k_A, ck_B, and ck_L have a frequency of 1/4. That is, when the clock ck_A is clocking, data is loaded into SR_A2 and data is output from SR_B3 which has already been loaded. On the other hand, in the case of ck_B, the reverse is true.

Next, it is assumed that m = 5 and j = 20 (see FIG. 2). In this case, 20 additional patterns are generated during the scan-in of the 5-bit width test vector, so that 20 test clock frequencies are required for 5 bits, and the SR_A2, SR_
B is shifted four times (= 20/5 (bi
t)). That is, in this case, the shift clock is only required to be one fifth of the test clock.

Thus, in the TPG according to the present invention, m
While scanning in a bit-wide test vector, j
Since the additional pattern is generated twice, the test clock frequency / shift clock frequency = j / m.

The TPG method according to the present invention has the following features, particularly in terms of actual tests. (1) ATPG coverage can be achieved with a short test length. (2) Since the scan-in frequency is lower than the test clock, an actual operation speed test using a low-speed tester is possible.

3. Selection of vector set to be stored in ROM 3-1. Concept for selecting and compressing a vector sequence stored in ROM In the TPG method according to the present invention, ATP stored in ROM
Since a fault is detected by the subsequence of the G vector and the vector sequence added by adding a pattern, ATPG coverage is guaranteed. When the ATPG vector sequence is stored in the ROM and a pattern is generated by ADD1, there is a possibility that there is an ATPG vector that is unnecessary for failure detection. Therefore, in order to reduce the ROM capacity and the test length, it is effective to remove these unnecessary ATPG vectors.

First, a concept for selecting and compressing a vector sequence stored in the ROM will be described. Against ATPG vector sequence V _c the underlying, the optimal solution of the arrangement of the vector can be obtained as follows. All of the partial sequence of the V _c contrast, generated the permutation, ADD1
A test vector sequence is obtained by (V). Reordering where ATPG coverage cannot be achieved by reordering the vectors is excluded. What is necessary is just to select the arrangement | positioning which is the minimum vector number among the arrangements which achieve ATPG coverage.

However, the subset of V _c is 2 ⁿ ,
For each subset, the permutation is a factorial of the set size, so the complexity of this algorithm is O
(2 ⁿ × n!). When n is several tens or more, it is difficult to process in a realistic time. The complexity is O
(N) is a content that involves n operations in order (proportional to n)
The stands, O ^{(n 2)} is, represents the content (proportional to ^{n 2)} with the work order to ^{n 2} times.

3-2. O (n ² ) head position selection method and O
(N ² ) Sampling method Then, as a method of realistically finding a better arrangement method,
The O (n ² ) head position selection method and the O (n ² ) extraction method will be described. FIG. 5 is an explanatory diagram of the O (n ² ) head position selection method. As shown in FIG. 5, in the O (n ² ) head position selection method, a head position to be stored in the ROM is selected from an ATPG vector sequence arranged in a ring. By arranging the ATPG vectors in a ring, ATPG coverage for a case where an arbitrary head position is selected is guaranteed. Store only use the vector sequence to achieve the ATPG coverage _{(V ROM} in the figure) in the ROM. That is, the vector sequence stored in the ROM is compressed by discarding the others.

FIG. 6 is a flowchart showing the O (n ² ) head position selection method. First of all,
By using the ATPG tool and providing the circuit information of the circuit under test to the ATPG software, A
A vector sequence that achieves the TPG coverage is determined as V. Further, the vector sequence V stored in the ROM
_ROM, V, and _{V c} 'example, is initialized to _{V c} (step S101). Here, V and V _c ′ are vector sequences used temporarily, and are work areas for calculation. Next, a loop is initialized (step S10).
3).

A test vector sequence V ^* having a pattern added thereto is generated from the vector sequence V by the function ADD1 (V), and a subsequence V 'of the test vector sequence V ^* required to achieve ATPG coverage is generated by fault simulation.
(COVER (C, V)). Specifically, in general, a fault simulator is a simulator that can obtain a fault detection rate by giving circuit information of a circuit under test and a test pattern (test vector sequence).
Using this fault simulator, a test vector sequence V
^When the vector units of ^* are used in order and the fault detection rate is obtained, the value becomes 100% when a certain number or quantity of vector units are used. At this time, a vector sequence having a failure detection rate of 100% is defined as a partial sequence V ′.

Next, an original sequence for generating V ′ by adding a pattern is obtained by a function ADD ⁻¹ (V ′).
V (step S105). That is, step S1
At 05, an ATPG vector necessary to achieve 100% ATPG coverage is obtained by performing a simulation using a test pattern obtained by expanding the pattern.

If | V | is compressed with respect to | V _ROM |, V _ROM is updated to V (step S1).
07). That is, when the number of ATPG vectors obtained in step S105 is the smallest so far, this vector set is set as a vector set to be stored in the ROM. Next, the vector positioned at the end of V _c ′ is rearranged at the head, and the head position is updated (step S109). That is, an operation of shifting the head position one by one is performed.

Next, the selection of the head position is checked for all the vectors (step S111). If examined, ROM, what vector length is minimum among the vector sequence _{V ROM} obtained in step S105,107,109
(Step S113).

Here, the circuit C is fixed and the algorithm C
Think about complexity. Vector generation operation in ADD1 (V)
Work and COVER (C, V^*) Failure simulation
The operation is complicated because each is repeated (j + 1) × n times
The degree is O (n). ADD ^-1(V ') is the index
The complexity is O (1)
You. Steps S105, 107 and 109 are repeated n times
, The complexity of this procedure is O (n²).

Next, an O (n ² ) extraction method will be described. This is based on the vector sequence V obtained by the O (n ² ) head position selection method.
Further compression can be performed on the _ROM . In FIG.
4 shows a flowchart of an O (n ² ) sampling method.

O (n²) The sampling method is O (n²)lead
Vector sequence V obtained by position selection method _ROMEach vector
For unnecessary, the following procedure is used to find unnecessary
_ROMThis is to extract the vector more. Note that O
(N²) The sampling method is O (n²) What is the head position selection method?
It may be performed independently and separately. First, use temporarily
Vector series V_c’And V_ROM’Each V_c
And V_ROM(Step S201). here
And V_cIs a vector series obtained by the ATPG tool.
And V_ROMIs stored in ROM compressed by the head position selection method.
This is a vector series to be stored. Next, initialize the loop
(Step S203).

V_ROMThe i-th vector v of_iEvaluate vs
Elephant vector v_pAnd ADD2 (V, v_p), V
_cMore v_pAnd remove v_pInstead of v_p-1And v
_{p + 1}J for each, that is, a 2 × j length
Turns are added to generate a vector sequence V (step
S205). Also, the function ADD2 (V, v_p) Is Baek
Vector v from the tor sequence V_pAfter removing_pOf
Instead v_pTwo vectors v adjacent to_p-1, V
_{p + 1}For the vector (v_r, V_p-1, V _r, V
_p-1,. . . , V_p-1) And (v_r, V_{p + 1},
v_r, V_{p + 1},. . . , V_{p + 1}). add to
The pattern length is 2 × j. This function is a vector
v_pIs the pseudo-random vector v_rCan be replaced by
Used to determine gender. Next, as described above,
V is ATPG cover
Storage has been achieved (step S207) (SIM
(C, V)), vector v _pIs unnecessary, and
V_ROMMore v_pVector series V from which is temporarily removed
To ADD1 (V) to add a pattern to
Step S209).

Similarly, using a failure simulator
And if V achieves 100% fault coverage (S
Step S211) (SIM (C, V)), V_ROM’
Rev_pIs removed (step S213). Next, everything
When the evaluation is performed on the vector (step S215)
Correspond to steps S205, 207, 209, 211, 21
Vector series V repeatedly obtained from_ROM’To R
A vector series stored in the OM (step S21)
7). Steps S205 and S207 are performed in advance.
This step is performed to skip this step.
(However, the evaluation time becomes longer). Also,
Steps 205, 207, 209, 211 and 213
The order is one vector v from the original vector set._p
Is removed and evaluated. 1 failure coverage
If it remains at 00%, this vector v _pGet rid of
If the failure coverage is reduced,
This vector v_pWill be restored.

Consider the complexity of the algorithm by fixing the circuit C. ADD2 (V, v _p ) performs pattern addition 2 × j times. SIM (C, V) in step S207 is
n + 2 × j times and the SI in step S211
Since M (C, V) is executed only when there is a possibility that the evaluation target vector can be extracted, M (C, V) is constant.
Since the procedure of steps S205, 207, 209, 211, and 213 is repeated at most n times, the complexity of this procedure is O (n ² ).

In the above description, the case where the ATPG coverage and the fault coverage are 100% has been described. can do. Also, a shift register SR, a multiplexer MUX, a memory RO
M, a pseudo random pattern generator LFSR, and the like may be provided in an appropriate number.

4. Experiment and comparison 4-1. Experimental Method Here, experimental results obtained by applying the present invention to ISCAS'85 and full-scan ISCAS'89 benchmark circuits are shown. For the above-mentioned TPG, the ROM capacity and test length required to achieve 100% fault coverage were determined. Redundant faults were excluded from the list of faults. The vector series stored in the ROM was generated by the ATPG tool, and then compressed by the O (n ² ) head position selection method and the O (n ² ) sampling method. ATPG tool is a stuck-at fault AT
The PG tool has been extended for transition failures.

First, with respect to the number j of additional patterns per ATPG vector, the case where j = 4 × m and j = 8 × m was compared using several CUTs (m is the number of inputs of the CUT). As a result, when j = 8 × m, j = 4 × m
Although the test length is about twice as large as that in the case of, the stored vector is not so compressed. Therefore, j = 4 ×
The following evaluation was performed as m.

Regarding the evaluation of the hardware amount of TPG, refer to the literature (J. Savir, “On chip weighted random”).
patterns, ”in Proc. of Asian Test Symposium, pp. 3
44-352, Nov. 1997., C. Fagot, O. Gascuel, P. Girar
d, and C. Landrault, “A ring architecture strateg
y for BIST test pattern generation, ”in Proc. of
As in Asian Test Symposium, pp. 418-423, Dec. 1998.), the TPG circuit was evaluated by converting it to a gate. The ROM portion including the address decoder and the like has 22.6 bits per gate as an example based on mass-produced device information.

4-2. FIG. 8 shows the compression effect of the ATPG vector sequence.²) Head position selection method and O (n²) Extraction
The compression result of the ATPG vector series by the
FIG. In the figure, “CUT” indicates the type of CUT.
And the “number of test vectors” is 100% fault coverage
Indicates the number of test vectors needed to achieve
The “compression ratio” is the test vector generated by the ATPG vector.
Shows the compression ratio based on the vector number. red. 1
Is O (n ²) Shows the result of applying only the head position selection method
And red. 2 is O (n²) Head position selection method and O (n
²3) shows the results of applying both sampling methods.

For example, in C1355, the number of vectors is reduced to 164 (80.8%) by the O (n ² ) head position selection method for 203 test vectors that achieve 100% fault coverage generated by ATPG. Is done. O
When the O (n ² ) extraction method is performed in addition to the (n ² ) head position selection method, the number of vectors is compressed to 126 (62.1%).

ATPG by O (n ² ) head position selection method
The compression ratio of the vector set is 83.3% on average, plus O
(N ² ) The result was 72.8% when the sampling method was performed. As described above, it can be understood that the ROM capacity in the BIST and the used memory capacity when the external tester is used can be reduced.

4-3. Comparison with TPG by Primitive LFSR FIG. 9 is an explanatory diagram of a comparison result of the TPG according to the present invention with the primitive LFSR relating to fault coverage, test length, and hardware. In the figure, the number of target faults indicates the number of transition faults excluding redundant faults. For TPG, test length to achieve 100% fault coverage,
The ROM capacity (bit) and the hardware ratio are shown. The hardware ratio is the ratio to the primitive LFSR (TP of the present invention).
G hardware amount / primary LFSR hardware amount)
Is shown. For the primitive LFSR method, the test length and the fault coverage at the time when 90% fault coverage is achieved are shown. It also shows the test length and fault coverage that achieved the highest fault coverage in the evaluated range.

For example, in C880, T
The PG method achieves 100% fault coverage with a test length of 7017 and an R of 1740 (= 29 × 60) bits.
Requires OM capacity. The hardware ratio is 3.
2. On the other hand, in the primitive LFSR system, the test length is 951, the fault coverage is 90.1%, and the test length is 26.
At 2144, the fault coverage is 94.5%. Therefore, it is found that it is difficult for the TPG of the primitive LFSR method to achieve 100% fault coverage, whereas the TPG method according to the present invention can be achieved with a short test length. This result shows that the TPG method uses the primitive LFS
Although it requires about 3 to 4 times the amount of hardware as compared to R, the AT has a short test length for transition failures.
It has been shown that PG coverage can be achieved.

4-4. Actual operation speed test using low-speed tester FIG. 10 shows a configuration diagram of a tester in which a TPG and an external tester according to the present invention are combined. In addition, the code | symbol in a figure corresponds to the code | symbol of FIG. The vector series _VROM is stored in the memory 41 in the external tester 21 and has the scan clock c
k_A and ck_B are generated by the external tester 21. In this system, a scan clock that is slower than the internal clock of the CUT 6 can be used. That is, an actual operation test using the external tester 21 slower than the CUT 6 can be performed for the transition failure. Therefore, in the TPG method, since the scan-in frequency can be lower than the actual operation speed test clock, an actual operation speed test using a low-speed tester is possible, and this is an effective method in terms of BIST design and actual test. I can say.

It should be noted that a writable gate array (FPGA: field programmable gate a) is used instead of the external tester.
rray) and ROM (or non-volatile memory) can be used to realize an inexpensive test circuit. In addition, the split shift method (S.
Hellebrand, J. Rajski, S. Tarnick, S. Venkatarama
n, and B. Courtois, “Built-in test for circuits w
ith scan based on reseeding of multiple-polynomial
linear feedback shift resisters, ”IEEE Trans. on
Computer, Vol. 44, no.2, pp. 223-233, Feb. 199
Using 5.) increases the number of pins for scan-in, but can significantly reduce the test time.

[0059]

According to the present invention, the required hardware is small, and a high fault coverage can be achieved with a short test length. Further, according to the present invention, since it is not necessary to perform scan-in for each test clock, an actual operation speed test using a low-speed tester can be performed. Further, according to the present invention, a random pattern detection failure is detected by a partial sequence of an ATPG vector.
Fault coverage using all PG vectors can be achieved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a pattern addition example (j = 8) by a function ADD1 (V).

FIG. 2 is an explanatory diagram showing an example of pattern generation for a benchmark circuit.

FIG. 3 shows a test pattern generation circuit (TP) according to the present invention.
FIG.

FIG. 4 shows a test pattern generator (TP) according to the present invention.
FIG. 9 is an explanatory diagram of a test pattern generation example (j = 8) by G).

FIG. 5 is an explanatory diagram of an O (n ² ) head position selection method.

FIG. 6 is a flowchart of an O (n ² ) head position selection method.

FIG. 7 is a flowchart of an O (n ² ) sampling method.

FIG. 8 is an explanatory diagram of a compression result of an ATPG vector sequence by an O (n ² ) head position selection method and an O (n ² ) extraction method.

FIG. 9 is an explanatory diagram illustrating a comparison result of a TPG according to the present invention with a primitive LFSR relating to fault coverage, test length, and hardware.

FIG. 10 is a configuration diagram of a tester that combines a TPG and an external tester according to the present invention.

FIG. 11 is a general configuration diagram of a BIST.

[Explanation of symbols]

 1 LFSR 2 SR_A 3 SR_B 4 ROM 5-1 5-2, 5-m MUX 6 CUT 10 TPG

Claims (14)

[Claims] 1. A storage unit storing a first test vector sequence for testing a state transition, and a first test vector sequence stored in the storage unit is divided into first and second vector units. First and second vector generators that output first and second vectors, respectively, a third vector generator that outputs a pseudo-random vector, and the first and third vector generators And a multiplexing unit that creates a second test vector sequence by mixing outputs from the second and third vector generation units and outputs the second test vector sequence to the circuit under test. Test equipment. 2. A second test vector sequence generated by the multiplexing unit, wherein a first vector unit output from the first vector generator and a second test vector sequence output from the third vector generation unit are output. Pseudo-random vectors are arranged alternately,
Further, the second vector output from the second vector generator
2. The test apparatus according to claim 1, wherein the vector unit is generated by alternately arranging a vector unit of the first vector and a pseudo random vector output from the third vector generation unit. 3. The storage system according to claim 1, wherein the storage unit stores only a subsequence of the original test vector sequence necessary to achieve the required fault coverage as a first test vector sequence. A test device according to claim 1. 4. The storage unit according to claim 1, further comprising: a first test vector sequence excluding a vector unnecessary for achieving a required fault coverage.
4. The test apparatus according to claim 1, wherein the test apparatus stores the test vector series. 5. The apparatus according to claim 1, wherein said storage section, said first to third vector generation sections, and said multiplexing section are provided in the same chip as the circuit under test.
The test device according to any one of the above. 6. The apparatus according to claim 1, further comprising a plurality of said multiplexing units, wherein each of said multiplexing units mixes outputs from said first to third vector generation units and outputs the mixed signals to a circuit under test. The test device according to any one of the above. 7. The apparatus according to claim 1, wherein said third vector generator has a linear feedback shift register.
The test device according to any one of the above. 8. The apparatus according to claim 1, wherein said first and second vector generators include a shift register.
The test device according to any one of the above. 9. A step of dividing a first test vector sequence for testing a state transition into first and second vector units and storing the divided first test vector series, and outputting the first vector and the pseudo-random vector in a mixed manner. And generating a second test vector sequence by mixing and outputting the second vector and the pseudo-random vector, and outputting the second test vector sequence to the circuit under test. 10. A step of obtaining a subsequence necessary to achieve a required fault coverage from an original test vector sequence; and shifting the subsequence by shifting a vector unit of the original test vector sequence. 10. The method of claim 9, further comprising: performing a determining step; and selecting a subsequence of a minimum or relatively small length, wherein the selected subsequence is used as a first test vector sequence. Test method. 11. The method according to claim 1, further comprising: removing an arbitrary vector unit of the original test vector sequence; and generating a vector sequence by adding an adjacent vector unit to the removed vector unit. 11. The test method according to claim 9, wherein, when the coverage is achieved, a value excluding the removed vector unit is used as a first test vector sequence. 12. The test method according to claim 9, wherein original test data is input from an external pin. 13. The test method according to claim 9, wherein test data obtained by an automatic test pattern generation tool is used as the original test data. 14. The method according to claim 9, wherein said storing step scans in and stores the first test vector sequence at a speed lower than a speed at which the second test vector sequence is output to the circuit under test. 14. The test method according to any one of claims 13 to 13.