JP2001221831A - Semiconductor ic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor IC circuit which accomplishes a BIST(built in self test), whitout having to provide an exclusive test terminal. SOLUTION: The semiconductor IC circuit is provided with a CPU 11 (central processing unit) to execute a prescribed program, a memory 12 to store the program, data and the like, a logic circuit 13 which performs logic operations, a BIST circuit 14 which performs BIST, a reset terminal 15 to receive a reset signal from the outside, a clock terminal 16 to receive a clock signal from the outside, and an output terminal 17 to output a signal to the outside. The BIST circuit 14 receives the reset signal from outside through the reset terminal 15, and the operation thereof is controlled by the reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a CPU mounted on a chip.
(Central Processing Unit), a semiconductor integrated circuit including a memory, a logic circuit, and the like, in particular, a semiconductor integrated circuit capable of performing a BIST (Built In Self Test) of a CPU, a memory, and a logic circuit without providing a dedicated test terminal About.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit having a CPU, a memory, a logic circuit, and the like on a chip, a method of performing a non-defective test is to input a test vector from outside the semiconductor integrated circuit to operate an internal circuit. There are methods.

Further, as the size and complexity of a semiconductor integrated circuit increases, the amount of test vectors and the number of testers required for the test become enormous, and the test time and cost increase. A BIST for generating and inspecting a signal is employed. Below, BI
The details of a semiconductor integrated circuit employing ST will be described.

FIG. 2 is a schematic diagram showing a configuration of a conventional semiconductor integrated circuit. In FIG. 2, the semiconductor integrated circuit includes a CPU (Central Proc) for executing a predetermined program.
essingUnit) 21, a memory 22 for storing programs and data, a logic circuit 23 for performing logical operations,
A BIST circuit 24 for performing a BIST, a reset terminal 25 for receiving an external reset signal, a clock terminal 26 for receiving an external clock signal, an output terminal 27 for outputting a signal to the outside, and an external test control signal. Test input terminal 2 for output to receiving BIST circuit 24
8 is provided.

The BIST circuit 24 receives a test control signal from the outside via a test input terminal 28, generates a test signal based on the test control signal, and generates a BIS
The data is output to the CPU 21, the memory 22, and the logic circuit 23 which are the targets of T. The CPU 21, the memory 22, and the logic circuit 23 receive and process the test signal, and output a processing result to the BIST circuit 24. BIST circuit 24
Determines the test result for each component to be tested by compressing those processing results and comparing the result of the compression processing with a preset expected value. The test result is output from the BIST circuit 24 to the output terminal 27, and is output from the output terminal 27 to the outside.

As described above, the conventional semiconductor integrated circuit employing the BIST circuit 24 does not require an enormous test vector or an expensive tester, so that the time and cost required for the test can be reduced.

[0007]

However, in the conventional semiconductor integrated circuit, since the BIST circuit 24 is controlled by an external test control signal, a plurality of test input terminals 28 for receiving a test control signal are required. was there. In view of the above, an object of the present invention is to provide a semiconductor integrated circuit capable of performing BIST without providing a dedicated test terminal.

[0008]

In order to solve the above problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having a substrate, a CPU, a memory, and a logic circuit provided on the substrate. Test means for testing a CPU, a memory, and a logic circuit, and reset input means for receiving a reset signal and outputting the reset signal to the test means are provided.

Here, the test means may be controlled by a reset signal received from the reset input means. Further, the test means may start the operation when the reset signal is input, and may continue the operation while the reset signal is input. Further, the test means may execute the BIST.

Since the test means is controlled by the reset signal received from the reset input means, BIST can be performed without providing a special test dedicated terminal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to the present invention. In FIG. 1, this semiconductor integrated circuit includes a CPU (Central Proc) for executing a predetermined program.
essing unit) 11, a memory 12 for storing programs and data, and a logic circuit 13 for performing logical operations
And BIS for performing a BIST (Built In Self Test) for testing the CPU 11, the memory 12, and the logic circuit 13.
A T circuit 14, a reset terminal 15 for receiving a reset signal from the outside, a clock terminal 16 for receiving a clock signal from the outside, an output terminal 17 for outputting a signal to the outside,
It has.

The semiconductor integrated circuit receives an external reset signal at a reset terminal 15 and is reset by an edge when the reset signal is switched from a high signal to a low signal or from a low signal to a high signal.

The BIST circuit 14 receives a reset signal from the outside via a reset terminal 15, and its operation is controlled by the reset signal. When a reset signal is input to the reset terminal 15, the BIST circuit 14 operates. Here, while the reset signal is being input,
The BIST circuit 14 continues to execute BIST.

When turned on by a reset signal, the BIST circuit 14 outputs a test signal to the C
The data is output to the PU 11, the memory 12, and the logic circuit 13. The CPU 11, the memory 12, and the logic circuit 13
The test signal is received and processed, and the processing result is output to the BIST circuit 14. The BIST circuit 14 performs a compression process on the processing results, and compares the result of the compression processing with an expected value set in advance to determine a test result for each component that has been a test target. The test result is output from the BIST circuit 14 to the output terminal 17,
The signal is output from the output terminal 17 to the outside.

At this time, the BIST circuit 14 outputs a low signal (or high signal) from the output terminal 17 when the result of the BIST matches an expected value set in advance, and outputs a high signal (or low signal) when the result does not match. ) Should be output.

[0017]

As described above, according to the semiconductor integrated circuit of the present invention, since the BIST circuit is controlled by the reset signal, the BIST circuit is provided without providing a dedicated test terminal.
You can now do.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of a semiconductor integrated circuit of the present invention.

FIG. 2 is a schematic diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 11, 21 CPU 12, 22 Memory 13, 23 Logic circuit 14, 24 BIST circuit 15, 25 Reset terminal 16, 26 Clock terminal 17, 27 Output terminal 28 Test input terminal

Claims (4)

[Claims] 1. A substrate, and a CPU provided on the substrate
(Central Processing Unit), a semiconductor integrated circuit including a memory and a logic circuit, wherein: the CPU, a test unit for testing the memory and the logic circuit, and a reset input unit for receiving a reset signal and outputting the reset signal to the test unit. A semiconductor integrated circuit, comprising: 2. The semiconductor integrated circuit according to claim 1, wherein said test means is controlled by said reset signal received from said reset input means. 3. The semiconductor integrated circuit according to claim 1, wherein the test means starts operating when the reset signal is input, and continues the operation while the reset signal is input. circuit. 4. The test means includes a BIST (Built In
4. The semiconductor integrated circuit according to claim 1, wherein a self test is performed.