JP2001218222A - Digital video image magnification reduction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital video image magnification/reduction circuit, that can enhance a definition sense of color and display a high image quality video image, because magnification/reduction is attained by maximally utilizing information of a received color difference signal. SOLUTION: A luminance magnification reduction circuit 11 magnifies/reduces a luminance signal of a received digital video signal. Color difference magnification/reduction circuits 21, 22 magnify/reduce a color difference signal in the received digital video signal. A luminance magnification reduction control circuit 25 controls the luminance magnification/reduction circuit 11 and a color difference magnification reduction control circuit 26 controls the color difference magnification/reduction circuits 21, 22 on the basis of a size magnification αreceived from a terminal 16. When a digital video signal with the 4:2:2 format is received, the color difference magnification reduction control circuit 26 selects 2αonly for a pixel number magnification in the horizontal direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video enlargement / reduction circuit capable of arbitrarily enlarging or reducing an input digital video signal and displaying a high quality image.

[0002]

2. Description of the Related Art At present, in a television receiver or the like, a multi-screen display is generally performed in order to support a multi-media input. In the case of multi-screen display, a plurality of video signals to be displayed are enlarged or reduced to an arbitrary size and arranged at an arbitrary position on a display screen. In addition, CS digital broadcasting is currently being conducted, and 200
In 1990, BS digital broadcasting and terrestrial digital broadcasting began. In the future, when the digital broadcasting era becomes full-scale, the importance of the human interface will increase further in order to cope with the multi-channel characteristic which is a feature of the digital broadcasting era. For that purpose, a multi-screen can be arbitrarily operated according to the user's preference, and a display method of high image quality and arbitrary size is essential. The basis of this multi-screen display is a technique for enlarging or reducing a video signal.

FIG. 5 is a block diagram for explaining the principle of the scaling circuit. FIG. 5A shows the principle of the reduction, in which a video signal input from the input terminal 1, that is, a luminance signal Y, a color difference signal Cb, or a color difference signal Cr is first supplied to a filter (low-pass filter) 2. And the band is limited. This is because it is necessary to limit the band to に よ り or less of the sampling frequency in advance in order to remove aliasing distortion generated by thinning out pixels. The output signal of the filter 2 is supplied to the downsampling circuit 3, downsampled, and output from the output terminal 4. The downsampling is an operation of thinning out sampling so as to have a desired number of pixels.

FIG. 5B shows the principle of the enlargement. The video signals Y, Cb and Cr input from the input terminal 1 are
The signal is supplied to an up-sampling circuit 5, is up-sampled by an interpolation process, and then output from an output terminal 4 via an interpolation filter 6. Actually, the reduction is realized by thinning out and writing to the memory, but the expansion is performed by inserting a zero value when reading out from the memory, and an operation equivalent to upsampling is performed. Enlargement interpolation filter processing is performed. FIG. 5C shows the principle of integrating reduction and enlargement. Since downsampling and upsampling are actually equivalent to a memory device, this configuration can be adopted from the viewpoint of saving memory resources. Many.

[0005] The input video signal is a digital video signal, and its format is ITU-R Recommendation 601 (former CC).
4: 2: 2 according to (IR recommendation) is common. As is well known in the field of digital video signals, this represents the ratio between the sampling frequency of the luminance signal Y and the two color difference signals Cb and Cr. The 4: 2: 2 format is used in the horizontal direction (horizontal direction). To reduce the color information by half, the sampling frequency of Y is 13.5
In MHz, Cb and Cr are 6.75 MHz, and the ratio is 4: 2: 2. The 4: 4: 4 format is Y, Cb, Cr
Are all 13.5 MHz in a ratio of 4: 4: 4. In contrast, the 4: 2: 0 format is
Actually, the 4: 2: 0 line and the 4: 0: 2 line are repeated, but also in the horizontal direction (horizontal direction) and the vertical direction (vertical direction).
In addition, in order to reduce the color information by half, the color information becomes １ ／ of the luminance information.

FIG. 6 is a diagram for explaining a digital video signal in 4: 2: 2 format. FIG. 6 shows the arrangement of the luminance signal and the color difference signal on the first line and the second line.
Cb and Cr each correspond to two pixels, and therefore, the color difference signal has an information amount of の of the luminance signal. In actual video signal transmission, a method of transmitting a luminance signal and a color difference signal in byte parallel by sequentially arranging the color difference signals Cb and Cr, and a method of transmitting the luminance signal and the color difference signal to Cb, Y, Cr, and
There is a serial transmission method for transmitting sequentially, such as Y, Cb, Y, Cr,. The following description proceeds as a 4: 2: 2 signal.

FIG. 7 is a block diagram showing a conventional enlargement / reduction circuit. Luminance signal Y input from input terminal 10
Is supplied to a luminance enlargement / reduction circuit 11, which performs enlargement / reduction according to the principle described above, and outputs a processed output signal from an output terminal 12. Similarly, the color difference signals Cb and Cr input from the input terminal 13 are supplied to the color difference enlargement / reduction circuit 14, where the color difference signals are enlarged and reduced, and the processed output signal is output from the output terminal 15. On the other hand, the control signal of the size magnification (size scaling ratio) input from the input terminal 16 is supplied to the scaling control circuit 17. The enlargement / reduction control circuit 17 determines and outputs the enlargement / reduction ratio, and supplies it to the luminance enlargement / reduction circuit 11 and the color difference enlargement / reduction circuit 14, thereby controlling the two enlargement / reduction circuits at the same enlargement / reduction ratio. Accordingly, for example, when the size is reduced to １ ／, the reduced video is generated by reducing the number of pixels of both the luminance signal and the color difference signal to １ ／.

FIGS. 8, 9 and 10 are diagrams for explaining the operation of the conventional example. FIG. 8 shows a case where the size magnification = 1/2, FIG. 9 shows a case where the size magnification = 1, FIG. Is the case where the size magnification = 2. In FIG. 8, the input video signals Y, Cb, and Cr shown in FIG. 8A are band-limited by a low-pass filter, down-sampled, and Y, Cb,
Cr is thinned out to 1/2, as shown in FIG. 8 (B).
Further, since the size magnification is １ ／, the size is reduced to に in the time axis direction in accordance with the display clock, as shown in FIG. 8C.

Similarly, in FIG. 9, the input video signals Y, Cb, and Cr shown in FIG. 9A are band-limited by a low-pass filter, down-sampled, and
, And since the size magnification = 1, the direction of the time axis does not change, as shown in FIG. 9C. Similarly, in FIG. 10, the input video signals Y, Cb,
Cr is both interpolated twice, as shown in FIG. 10B, and furthermore, since the size magnification = 2, it is enlarged twice in the time axis direction in accordance with the display clock, and as shown in FIG. It becomes as shown in. As is clear from FIGS. 8 (C), 9 (C) and 10 (C), even if the size magnification changes, it is always 4: 2: 2.
Is output and displayed.

Although not mentioned in the above description,
Since the image needs to be considered two-dimensionally, the above contents are performed simultaneously in the horizontal and vertical directions. Therefore, the filter needs to be composed of a two-dimensional filter combining horizontal and vertical. If the horizontal and vertical directions are configured to be independently variable, the two-dimensional filter is configured to be variable independently.
Alternatively, it is necessary to separately prepare a horizontal scaling circuit and a vertical scaling circuit.

[0011]

By the way, in the conventional example described above, since the image is always displayed in the 4: 2: 2 format, especially on a reduced screen, luminance information and color information are thinned out and lost. Will be. However, in view of the future digital image era, higher image quality and higher definition image expression is required. The present invention has been made in order to solve the above-described problems, and it is possible to perform enlargement / reduction using information of an input color difference signal as much as possible. It is possible to reproduce an image full of a three-dimensional effect. In particular, in a reduced screen of 1/2 or less, since the band of the luminance signal and the band of the color difference signal are the same, the original 4:
It is an object of the present invention to provide a digital video scaling circuit capable of displaying 4: 4 video and displaying high quality video.

[0012]

In order to achieve the above object, (1) a luminance enlargement / reduction circuit for enlarging / reducing a luminance signal of an input digital video signal, and a luminance enlargement / reduction circuit of an input digital video signal A color difference enlargement / reduction circuit that enlarges / reduces the color difference signal of the above, a luminance enlargement / reduction control circuit that controls the enlargement / reduction size magnification and the number of pixels in the luminance enlargement / reduction circuit based on the input size magnification α, and the input size magnification a color difference enlargement / reduction control circuit for controlling the enlargement / reduction size magnification and the number of pixels in the color difference enlargement / reduction circuit based on α, and when a 4: 2: 2 format digital video signal is input, The luminance scaling control circuit sets the horizontal pixel number scaling factor and the vertical pixel number scaling factor to α, and the color difference scaling control circuit sets the horizontal pixel number scaling factor to α. α, a digital video scaling circuit characterized in that the vertical pixel number magnification is α, (2) a brightness scaling circuit for scaling a brightness signal of the input digital video signal; A color difference enlargement / reduction circuit for enlarging / reducing the color difference signal of the input digital video signal; and a luminance enlargement / reduction controlling the size enlargement / reduction circuit and the number of pixels in the luminance enlargement / reduction circuit based on the input size magnification α. A color difference enlargement / reduction control circuit for controlling the enlargement / reduction size magnification and the number of pixels in the color difference enlargement / reduction circuit based on the input size magnification α; When a video signal is input, the luminance enlargement / reduction control circuit sets the horizontal pixel number magnification and the vertical pixel number magnification to α, and performs the color difference enlargement / reduction control. Road is to provide a digital video scaling circuit characterized in that the 2α horizontal pixel count ratio and the vertical pixel number ratio.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1, the same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will be omitted. The luminance signal Y input from the input terminal 10 is supplied to a luminance enlargement / reduction circuit 11, which performs enlargement / reduction as in the conventional example, and outputs a processed output signal from an output terminal 12. Similarly, the color difference signals Cb, Cr input from the input terminal 13 are supplied to the Cb / Cr separation circuit 20. The Cb / Cr separation circuit 20 separates the Cb signal and the Cr signal,
And 22.

The color difference scaling circuit 21 scales the input color difference signal Cb and outputs the processed output signal from the output terminal 23. Similarly, the color difference enlargement / reduction circuit 22
Performs the scaling process on the input color difference signal Cr, and outputs the processed output signal from the output terminal 24. On the other hand, the control signal of the size magnification input from the input terminal 16 is supplied to the luminance enlargement / reduction control circuit 25 and the color difference enlargement / reduction control circuit 26. The brightness enlargement / reduction control circuit 25 uses the size magnification.
(Size enlargement / reduction rate) and pixel number magnification (pixel enlargement /
By determining and outputting the reduction ratio, and supplying it to the luminance enlargement / reduction circuit 11, the enlargement / reduction of the luminance signal is controlled.
Similarly, the color difference enlargement / reduction control circuit 26 determines and outputs the size magnification and the pixel number magnification separately, and outputs the color difference enlargement / reduction circuit 21.
And 22 controls the scaling of the color difference signal.

The luminance enlargement / reduction circuit 1 used here
1. The color difference scaling circuits 21 and 22 are almost the same as the scaling circuit described in the conventional example. Here, since the input digital video signal is assumed to be 4: 2: 2 byte parallel (16 bits) in which the color difference signals Cb and Cr are sequentially multiplexed, the Cb / Cr separation circuit 20 is required. This is not necessary if the input color difference signals Cb and Cr are already separated 24 bit inputs. A feature of the present invention is that two enlargement / reduction control circuits 25 and 26 for a luminance signal and a color difference signal are separately provided. Here, the size magnification of the display screen is α
In this case, the horizontal pixel magnification of the luminance signal is set to α, and the horizontal pixel magnification of the color difference signal is set to 2α. The magnification of the number of pixels in the vertical direction is α for both the luminance signal and the color difference signal. That is, the feature is that only the horizontal pixel magnification is set to 1: 2 for the luminance signal and the color difference signal.

For example, when displaying in the same format as the format of the input video signal (size magnification α = 1),
The number of pixels in the horizontal direction of the luminance signal is 1 and the number of pixels in the horizontal direction of the color difference signal is 2 (the number of pixels in the vertical direction is 1). Also, the format of the input video signal is 1 /
When the display is reduced to 2 (size magnification α = １ ／), the number of pixels in the horizontal direction of the luminance signal is set to 、, and the number of pixels in the horizontal direction of the color difference signal is set to 1 (vertical pixels). Both magnifications are 1).

FIGS. 2, 3 and 4 are diagrams for explaining the operation of the present invention. FIG. 2 shows a case where the size magnification α = 1/2, and FIG. 3 shows a case where the size magnification α = 1. FIG. 4 shows a case where the size magnification α = 2. In FIG. 2, in the input video signals Y, Cb, and Cr shown in FIG. 2A, only Y is band-limited by a low-pass filter, down-sampled and thinned out to 1/2, and Cb and Cr remain unchanged. 2B, and since the size magnification α is ２, the size is reduced to に in the time axis direction according to the display clock.
The result is as shown in FIG.

Similarly, in FIG. 3, the input video signals Y, Cb, and Cr shown in FIG.
Is interpolated and doubled, as shown in FIG. 3 (B), and since the size magnification α = 1, the time axis direction does not change.
The result is as shown in FIG. Similarly, in FIG.
In the input video signals Y, Cb, and Cr shown in (A), Y is interpolated twice and both Cb and Cr are interpolated four times, as shown in FIG. = 2, so that it is doubled in the time axis direction in accordance with the display clock.
It becomes as shown in. As is clear from FIGS. 2 (C), 3 (C), and 4 (C), even if the size magnification α changes, it is always 4:
A 4: 4 video signal is output and displayed.

In particular, in a reduced screen of α = １ ／ or less, the original 4: 4: 4 band in which the band of the luminance signal and the band of the color difference signal are the same.
It becomes a video. In the case of α = の or more, the pixel for the color difference signal is formed by interpolation, so that pseudo 4:
4: 4 images are obtained. However, in the prior art, when displaying, it is common to generate the color difference signal pixels between them by writing twice, so that the present invention can provide a more accurate color signal even on a display screen with α = １ ／ or more. It becomes an image. In the present embodiment, the color difference signals Cb and Cr are processed by separate circuits, but byte parallel processing in which Cb and Cr are sequentially arranged is also possible. In this case, since the color difference signal can be processed by one circuit, there is an advantage that the circuit scale of the system is reduced. However, the number of clocks after the resizing process needs to be doubled.

In the above description, a digital video signal of 4: 2: 2 format is input.
When a 0-format digital video signal is input, the color information in the vertical direction is also halved. Therefore, the pixel number magnification in both the horizontal direction and the vertical direction is set to 1: 2 for the luminance signal and the color difference signal. Needless to say, it should be set to. As described above, the present invention has the advantage that it is possible to perform enlargement / reduction by making maximum use of the information of the input color difference signal, and to reproduce a high-quality image. In the future digital broadcasting era, multi-channel and high image quality are important themes, and it is expected that the opportunity to enjoy high-quality images by multi-screen display will increase, and the present invention is very useful in such cases. Become.

[0021]

The digital video scaling circuit of the present invention is
Enlargement / reduction that makes full use of the input color difference signal information is possible, which enhances the color definition and enables the reproduction of images with a rich number of colors and full of a three-dimensional effect. On the screen, since the band of the luminance signal and the band of the color difference signal are the same, there is an extremely excellent effect that the original 4: 4: 4 image can be displayed and a high quality image can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the present invention.

FIG. 3 is a diagram for explaining the operation of the present invention.

FIG. 4 is a diagram for explaining the operation of the present invention.

FIG. 5 is a block diagram for explaining the principle of the scaling circuit.

FIG. 6 is a diagram for explaining a digital video signal of 4: 2: 2 format.

FIG. 7 is a block diagram showing a conventional scaling circuit.

FIG. 8 is a diagram for explaining the operation of the conventional example.

FIG. 9 is a diagram for explaining the operation of the conventional example.

FIG. 10 is a diagram for explaining the operation of the conventional example.

[Explanation of symbols]

 10, 13, 16 input terminal 11 luminance enlargement / reduction circuit 12, 15, 23, 24 output terminal 14, 21, 22 color difference enlargement / reduction circuit 17 enlargement / reduction control circuit 20 Cb / Cr separation circuit 25 luminance enlargement / reduction control circuit 26 color difference enlargement Reduction control circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/01 G09G 5/36 520E 11/06 H04N 11/06 11/24 F term (Reference) 5C023 AA01 AA02 AA21 BA15 CA01 CA02 CA08 DA04 DA08 5C057 AA06 AA11 BA02 DA03 EA02 EA07 EL01 GF03 5C063 AA02 AC01 CA36 CA40 5C066 AA03 BA02 CA05 ED09 EE02 GA02 GA05 HA03 HA04 KE16 5C082 AA02 BA34 CA10 CA33 MM

Claims (2)

[Claims] 1. A luminance enlargement / reduction circuit for enlarging / reducing a luminance signal of an input digital video signal, a color difference enlargement / reduction circuit for enlarging / reducing a color difference signal of an input digital video signal, and an input size A luminance enlargement / reduction control circuit for controlling the enlargement / reduction size magnification and the number of pixels in the luminance enlargement / reduction circuit based on the magnification α; And a color difference enlargement / reduction control circuit for controlling the number of pixels. When a 4: 2: 2 format digital video signal is input, the luminance enlargement / reduction control circuit controls the number of pixels in the horizontal direction and the number of pixels in the vertical direction. The pixel number magnification in the horizontal direction is α, and the color difference scaling control circuit sets the horizontal pixel number magnification to 2α and the vertical pixel number magnification to α. Digital video scaling circuit to be. 2. A luminance enlargement / reduction circuit for enlarging / reducing a luminance signal of an input digital video signal; a color difference enlargement / reduction circuit for enlarging / reducing a color difference signal of an input digital video signal; A luminance enlargement / reduction control circuit for controlling the enlargement / reduction size magnification and the number of pixels in the luminance enlargement / reduction circuit based on the magnification α; And a color difference enlargement / reduction control circuit for controlling the number of pixels. When a 4: 2: 0 format digital video signal is input, the luminance enlargement / reduction control circuit controls the number of pixels in the horizontal direction and the number of pixels in the vertical direction. And the color difference enlargement / reduction control circuit sets the horizontal pixel number magnification and the vertical pixel number magnification to 2α. Digital video scaling circuit that.