JP2001216157A5 - - Google Patents

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Publication number
JP2001216157A5
JP2001216157A5 JP2001023626A JP2001023626A JP2001216157A5 JP 2001216157 A5 JP2001216157 A5 JP 2001216157A5 JP 2001023626 A JP2001023626 A JP 2001023626A JP 2001023626 A JP2001023626 A JP 2001023626A JP 2001216157 A5 JP2001216157 A5 JP 2001216157A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001023626A
Other languages
Japanese (ja)
Other versions
JP2001216157A (ja
JP4405095B2 (ja
Filing date
Publication date
Priority claimed from US09/497,533 external-priority patent/US6892294B1/en
Application filed filed Critical
Publication of JP2001216157A publication Critical patent/JP2001216157A/ja
Publication of JP2001216157A5 publication Critical patent/JP2001216157A5/ja
Application granted granted Critical
Publication of JP4405095B2 publication Critical patent/JP4405095B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2001023626A 2000-02-03 2001-01-31 非順序プロセッサのための命令検索及びポート割り当て(fiap)回路とその方法 Expired - Fee Related JP4405095B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/497,533 US6892294B1 (en) 2000-02-03 2000-02-03 Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor
US09/497533 2000-02-03

Publications (3)

Publication Number Publication Date
JP2001216157A JP2001216157A (ja) 2001-08-10
JP2001216157A5 true JP2001216157A5 (enExample) 2006-11-30
JP4405095B2 JP4405095B2 (ja) 2010-01-27

Family

ID=23977240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001023626A Expired - Fee Related JP4405095B2 (ja) 2000-02-03 2001-01-31 非順序プロセッサのための命令検索及びポート割り当て(fiap)回路とその方法

Country Status (2)

Country Link
US (1) US6892294B1 (enExample)
JP (1) JP4405095B2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12517733B2 (en) * 2024-02-28 2026-01-06 Arm Limited Circuits and methods for picking multiple ready instructions per cycle

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838942A (en) 1996-03-01 1998-11-17 Hewlett-Packard Company Panic trap system and method
US5758178A (en) * 1996-03-01 1998-05-26 Hewlett-Packard Company Miss tracking system and method
US5761713A (en) 1996-03-01 1998-06-02 Hewlett-Packard Co. Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank
US5809275A (en) 1996-03-01 1998-09-15 Hewlett-Packard Company Store-to-load hazard resolution system and method for a processor that executes instructions out of order
US5796997A (en) 1996-05-15 1998-08-18 Hewlett-Packard Company Fast nullify system and method for transforming a nullify function into a select function
US5799167A (en) 1996-05-15 1998-08-25 Hewlett-Packard Company Instruction nullification system and method for a processor that executes instructions out of order
US5796975A (en) 1996-05-24 1998-08-18 Hewlett-Packard Company Operand dependency tracking system and method for a processor that executes instructions out of order
US5761474A (en) 1996-05-24 1998-06-02 Hewlett-Packard Co. Operand dependency tracking system and method for a processor that executes instructions out of order
US5748934A (en) 1996-05-31 1998-05-05 Hewlett-Packard Company Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words
US5875340A (en) 1996-05-31 1999-02-23 Hewlett-Packard Company Optimized storage system and method for a processor that executes instructions out of order
US6289437B1 (en) * 1997-08-27 2001-09-11 International Business Machines Corporation Data processing system and method for implementing an efficient out-of-order issue mechanism
US6308260B1 (en) * 1998-09-17 2001-10-23 International Business Machines Corporation Mechanism for self-initiated instruction issuing and method therefor

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