JP2001210091A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply and securely replace a defective memory cell by a redundant memory cell by improving a program process for a fuse element at the time of using a redundant circuit of a SRAM. SOLUTION: This device is provided with a plurality of normal address decoders 21a for selecting a normal memory cell, a plurality of redundant address decoders 21b for selecting a redundant memory cell, fuse elements 50 for programming provided at the output side of each normal address decoder and cut off to make the normal address decoder a non-selection state, and address registers 60x-600 provided corresponding to each normal address decoder, and generating a replacement address signal for specifying an address of a redundant address decoder by which a normal address decoder corresponding to the fuse element for programming is replaced in a state in which a fuse element for program is cut off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a redundancy circuit using a fuse element for programming.
M) Used for integrated circuits.

[0002]

2. Description of the Related Art In an SRAM, a redundancy circuit is mounted corresponding to a row and / or a column of a memory cell array, and a data read / write failure due to a row, a column or a cell failure for normal operation is defective. Occurs, the defective memory cell is replaced with a redundant memory cell.
In this case, by using a redundant circuit adapted to each failure scale, failures are relieved and the production yield is improved. In a conventional SRAM, in order to operate using a redundant circuit, when a defective address corresponding to a defective cell among the memory cells for normal operation is selected, the defective cell is deselected and the redundant circuit is turned off. Circuits such as a decoder provided for setting a selected state and a selected address of a redundant circuit to a set state must be programmed using a fuse element formed on the SRAM device. However, in the case of megabit generation SRAM, the scale of addresses corresponding to the number of device elements becomes enormous with the acceleration of ultra-miniaturization of semiconductor elements, and the size of defective cells can be repaired without exceeding the size of redundant cells. However, a decrease in manufacturing yield is accelerated due to an address programming error in a defective address storage circuit or the like for storing a defective address.

[0003]

SUMMARY OF THE INVENTION As described above, the conventional
The SRAM has a problem in that the production yield is accelerated due to an address program error in a defective address storage circuit or the like. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an improved semiconductor memory device capable of improving a programming process for a fuse element when a redundant circuit is used and replacing a defective memory cell with a redundant memory cell simply and reliably. The purpose is to provide.

[0004]

A first semiconductor memory device according to the present invention comprises a memory cell array including a normal memory cell for normal access and a redundant memory cell for repairing a defective memory cell, and a normal memory cell of the memory cell array. A plurality of normal address decoders, a plurality of redundant address decoders for selecting redundant memory cells of the memory cell array, and a plurality of normal address decoders provided corresponding to the output side of each of the normal address decoders. Are provided corresponding to the programming fuse elements that are cut off when programming to the non-selected state, and the normal address decoders, and correspond to the programming fuse elements when the program fuse elements are cut off. Redundancy that replaces the normal address decoder Characterized by comprising a redundancy address decoder specifying circuit for generating a redundant address decoder designating address signal for designating an address of the address decoder. As an example of the program fuse element, a pair of two fuse elements arranged in parallel with a minimum wiring interval so as to be cut by a single fuse blow is set as a set, and one-to-one is connected to the plurality of redundant address decoders. A plurality of fuse elements corresponding to each other are arranged in series, and one of the two fuse elements in the set is inserted and formed in series with the output signal line of the normal address decoder, and the other is formed. Can be connected to the redundant address decoder designating circuit.

Thus, when the fuse element for program is cut off, the redundant address decoder designating circuit can be enabled to output the redundant address decoder designating address signal. According to a second semiconductor memory device of the present invention, there is provided a memory cell array including a normal memory cell for normal access and a redundant memory cell for repairing a defective memory cell, and a plurality of normal addresses for selecting a normal memory cell of the memory cell array. A decoder, a plurality of redundant address decoders for selecting redundant memory cells of the memory cell array, and a plurality of redundant address decoders provided corresponding to the output side of each of the normal address decoders. A program fuse element to be cut and a redundant address decoder provided corresponding to each of the normal address decoders, and replacing the normal address decoder corresponding to the program fuse element when the program fuse element is cut. address A redundant address decoder designating circuit for generating a redundant address decoder designating address signal for designating a plurality of normal address decoders for controlling an enable / disable state of the corresponding normal address decoders And a plurality of fuse elements corresponding to the plurality of redundant address decoders on a one-to-one basis are arranged in series.

As an example of the program fuse element, the fuse address element is arranged separately from the output signal line of the normal address decoder, and the redundant address decoder designating circuit and the normal address decoder control provided corresponding to the normal address decoder are provided. It can be connected to a circuit. Accordingly, when the program fuse element is cut off, the redundant address decoder designating circuit is enabled to output the redundant address decoder designating address signal, and the control signal for setting the normal address decoder to a non-selected state. Can be generated from the normal address decoder control circuit.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. <First Embodiment> FIG. 1 shows a pattern layout on an SRAM chip according to a first embodiment of the present invention. The SRAM shown in FIG. 1 has four memory cell arrays (Cell Array) 11 employing a double word line system.
Each cell array 11 includes normal memory cells (not shown) for normal access and redundant memory cells (not shown) for repairing defective memory cells, and includes a plurality of redundant rows in addition to a large number of rows for normal operation. Row (R / D row) is added. Then, two cell arrays 11 adjacent in the row direction
A main row decoder 12 including a normal main row decoder group for selecting the normal memory cells and a redundant row decoder group for selecting the redundant memory cells is disposed in the middle part of the cell array. Are divided into a plurality (eight in this example) of sections Sec0 to Sec7. In a region between the normal main row decoder group and the sections Sec0 on both sides thereof, a fuse and address register including a program fuse element group and a row address register group which are a part of a redundant circuit is provided.
13 are provided.

FIG. 2 shows a group of normal main row decoders 21 and a group of fuse elements for programming arranged on one side thereof as an area corresponding to a quarter block in FIG.
22, address register group 23, main word line (redundant row
The detailed pattern layout is shown by extracting the group 24 (including the word line of R / D row) and eight sections Sec0 to Sec7. FIG. 3 shows a main row decoder group in FIG.
21 includes a normal main row decoder 21, a fuse element group 22 for programming, an address register group 23 corresponding to the row addresses Ax to A0, and a normal main word line NWL group 24.
FIG. 4 is a diagram showing a pattern layout by representatively extracting a part of the pattern layout. FIG. 4 shows a normal main row decoder, a program fuse element group 22, an address register group 23, a normal main word line NWL group, a redundant row decoder group 25, and a redundant main word line (in the main row decoder group 21 in FIG. 2). R / D NWL-1 to R / DNWL-4) groups and sections
It is a block diagram which extracts and shows typically a part (section selection gate Div NOR) of Sec0. FIG. 5 is a circuit diagram showing a part of FIG. 4 in detail. 2 to 5, each of the normal main row decoders 21a in the main row decoder group 21 receives an address signal (4 bits in this example) from a predecoder (not shown) for normal access, and outputs respective signals. The normal main word line MWL is connected to the side. Each normal main word line MWL extends on each section Sec0 to Sec7.

Each redundant row decoder comprises an address comparing circuit section 20 and a redundant main word line driving circuit 21b activated by the coincidence detection output of the address comparing circuit section 20, and a redundant main word line driving circuit 21b corresponding to the output side thereof. Word line R / DM
WL-1 to R / D MWL-4 are connected. In each of the sections Sec0 to Sec7, a plurality of bit line pairs (not shown) and a plurality of word lines WL are provided, and a large number of memory cells are connected to these. A section selection signal line SSL and a section selection gate Div NOR (Divided NOR) are provided in a region between two sections of each set, which is a set of two sections adjacent in the row direction.
Groups are arranged. The normal main word line MWL
And the section selection line SSL is an input to a group of normal section selection gates G1. The redundant main word lines R / D MWL-1 to R / D MWL-4 and the section selection line SSL are used as section selection gates for redundancy. G2 group input. Thereby, each section selection gate G1, G2
Is the section selection signal line SSL and each of the normal main word lines MWL or each of the redundant main word lines R / D
The logical product of MWL-1 to R / D MWL-4 is obtained, and the word line WL in one of the two sections forming one set is formed by the group of section select gates G1 and G2.
Is driven.

In addition, corresponding to the output side of each of the normal main row decoders 21a, there is arranged a programming fuse element which is cut off when the corresponding normal main row decoder 21a is programmed to a non-selected state. A decoder designating circuit (in this example, address registers 60x to 600) is provided. The program fuse element includes a plurality of redundant row decoders 21b as a set of two fuses including a disable fuse 51 and a redundant selection fuse 52.
A plurality of sets of fuses 50 corresponding to each other are arranged in series. The two fuses 51 and 52 forming a pair are formed close to each other, and in this example, the main word line MW
It is made of an aluminum fuse formed of the same aluminum wiring layer as that of L, and is arranged in parallel with a minimum wiring interval so as to be cut by a single fuse blow. Further, a window (not shown) for fuse blowing is opened above the two aluminum fuses in the insulating film (not shown) on the aluminum wiring layer. One disable fuse 51 of the pair of two aluminum fuses is formed by being inserted in series with the output signal line (normal main word line MWL) of the normal main row decoder 21a. The other redundant selection fuse 52 is connected to the address registers 60x to 600 via signal lines.

The disable fuse 51 is connected to the corresponding normal main row decoder 21a or the normal main word MWL, or the word line W selectively controlled by the corresponding normal main word MWL.
When it is determined that a defective cell is connected to L and is disconnected (programmed), the normal main word MW
L is cut off, and has a role of controlling the normal main row decoder 21a corresponding to the normal main word MWL to the non-selected state. When the redundancy selection fuse 52 is cut (programmed) in the same manner as the corresponding disable fuse 51, a set of (x + 1) address registers in the corresponding fuse & address register 13a is provided. (X + 1) -bit redundant address decoder designation address signals (replacement address signals) Ax to A0 from 60x to 600
Has the role of outputting The address register 60x
To 600 are the plurality of sets of fuse elements 5 for programming.
0, and a normal main row decoder 21a corresponding to the program fuse element 50 is provided.
Address signals Ax to A0 for designating the address of the redundant row decoder to be replaced (to be used)
Is held, and the enable / disable of the output of the replacement address signals Ax to A0 is controlled according to the disconnection / non-disconnection of the redundancy selection fuse 52.
That is, in the address registers 60x to 600, the output of the held replacement address signals Ax to A0 is enabled when any one of the corresponding four redundant selection fuses 52 is cut off.

On the other hand, the redundant row decoder 21b shown in FIG.
Address comparison circuit section (only one representative is shown)
Reference numeral 20 denotes an address signal Ax to A0 from an address buffer (not shown) and the fuse & address register 13a.
The replacement address signals Ax to A0 supplied from the group via the replacement address signal line 53 are input, the two inputs are compared, and a match detection signal that is activated when both inputs match is output, and the corresponding redundant main signal is output. It is supplied to the word line drive circuit 21b. The address comparison circuit section 20 includes inverter circuits 54x to 540 to which replacement address signals Ax to A0 supplied via the replacement address signal line 53 are input correspondingly, and grounds each input node of the inverter circuits 54x to 540. It has a pull-down resistive element 55 connected to the node. The output signals of the inverter circuits 54x to 540 correspond to one input and address signals Ax to A0 from the address buffer are input as the other input, and the output nodes are connected in common, and the common output node a Pull-up PMOS transistor 56 connected between the power supply node
And a resistance element 57 connected between the common output node a and the ground node, and has NMOS NAND gates 58x to 580 for detecting the coincidence of the H level of both inputs. Further, output signals of the inverter circuits 54x to 540 correspond to one input, and address signals Ax to A0 from an address buffer are input as the other input, and each output node is commonly connected to the node a. The pull-up PMOS transistor 56 connected between a common output node a and a power supply node;
And PMOS resistance gates 57x to 590 for detecting when the L level of both inputs coincide with each other.

Here, when a redundant row decoder is used, the common output node a is pulled up to the power supply voltage VCC by cutting a fuse formed between the resistance element 57 and the ground node. . Then, for example, the replacement address signal A0 supplied via the replacement address signal line 53
And the address signal A0 from the corresponding address buffer does not match, the NMOS NAND gate 580 (when both signals are at H level) or the PMOS NAND gate 590 (when both signals are at L level) The common output node a is pulled down to the ground potential. Conversely, if the replacement address signals Ax to A0 supplied via the replacement address signal line 53 and the address signals Ax to A0 from the corresponding address buffers all match, the common output node a is The voltage remains at the voltage VCC, and the redundant row decoder 21b is selected. FIG. 6 shows one bit (for example, A) of the address signals Ax to A0 supplied from one set of address registers 60x to 600 in FIG.
FIG. 3 is a circuit diagram representatively showing in detail a 1-bit address register 600 for generating (0).

In FIG. 6, signal lines 61 to 64 are respectively connected to the four redundant selection fuses 52 and also connected to, for example, a power supply node via resistance elements R. As a result, when the corresponding redundant selection fuse 52 is in the non-cut state, it is pulled down to the ground potential VSS, and when it is cut, it is pulled up to the power supply potential VCC. The latch circuit 65 is composed of two CMOS inverter circuits connected in anti-parallel and has an input node b
Is connected to either the power supply potential VCC node or the ground potential VSS node via the wiring 66, and the potential of the output node c is VCC (“H”) or VSS
(“L”). At this time, each output potential of each latch circuit 65 of one set of address registers 60x to 600 is set to the address comparison circuit section of the redundant row decoder to be used.
In order to correspond to the comparison input (address signals A0 to Ax) supplied to the latch circuit 20, the connection destination (VCC
Or VSS). The NMOS transistors 671 to 674 are connected to the signal line 61 corresponding to each gate.
To 64, each drain is connected in common and connected to the output node c of the latch circuit 65, and each source potential is correspondingly set in the address comparison circuit section 20.
Of the comparison input (address signals Ax to A0) are input as one bit A0.

The NMOS transistors 671 to 674
Is turned on when VCC is applied from the signal lines 61 to 64 connected to the respective gates to pass the output potential of the latch circuit 65 to the source, and when VSS is applied. Is turned off, the source potential becomes an electrically floating state (high impedance state), and has a role of controlling the enable / disable of the outputs of Ax to A0. the above
In the SRAM, when none of the four fuse elements 50 is disconnected (corresponding to the normal main row decoder 21)
a) is used, the outputs Ax-A0 of the corresponding set of address registers 60x-600 are disabled, and the corresponding redundant row decoder is not used. On the other hand, when the redundant circuit is used (when any of the redundant row decoders is used), four sets of the output side of the normal main row decoder 21a to which the normal main word line MWL to be relieved is connected are connected. A set of two aluminum fuses 51 and 52 of the fuse element 50 is cut (programmed) by a single fuse blow. As a result, one (first) disabling fuse 51 is inserted in series with the normal main word line MWL.
By cutting, the corresponding normal main row decoder 21a can be disabled.

The other (second) fuse 52 for redundancy selection has one end connected to the ground potential VSS and the other end connected to the corresponding address register via corresponding signal lines 61 to 62.
Since the enable control inputs are 60x to 600, by cutting, the address (repair address) of the normal main row decoder 21a to which the normal main word line MWL to be rescued is connected corresponds to the redundant row decoder. It is set in the address comparison circuit section 20. Therefore, after this, when the address signal input hits the rescue address during normal operation (when the address input is a defective address), the match detection signal output from the address comparison circuit unit 20 in which the rescue address is set is output. Activate the corresponding redundant main word line drive circuit
21b is activated and the corresponding redundant main word line R / D MW
L-1 to R / D MWL-4 will be selected. That is, in the SRAM of the above embodiment, a disable fuse and a redundancy selection fuse are provided on the output side of each normal main row decoder, and one set of the disable fuse and the redundancy selection fuse is provided. By performing the replacement program step of cutting, the defective main row decoder to be rescued can be directly set to the non-selection state, and the address of the redundant row decoder to be used (rescue address) can always be set in the address storage circuit unit. It has become.

This makes it possible to directly set the main row decoder to be rescued to a non-selected state, and to always set the address (rescue address) of the redundant row decoder to be used in the address comparison circuit section. That is, when a redundant circuit is used, the corresponding normal row decoder can be turned off simply by cutting the programming fuse element provided on the output side of the normal row decoder without programming the repair address of the replaced row decoder. At the same time, the redundant row decoder used for replacement can be set to a selectable state. In this state, if the address input hits a defective address (relief address) during normal operation, the redundant row decoder can be accessed immediately by the match detection output of the address storage circuit unit, and the match detection is performed as in the conventional example. Since it is not necessary to control the normal row decoder to be in the non-selection state by the output, the speeding up of the access time is not impaired. Therefore, only one type of programming fuse element (one set of disabling fuse element and redundant selection fuse element) needs to be cut off at the time of the replacement program. The programming process is significantly simplified as compared to the replacement programming process.

Further, since one set of the fuse element for disabling and the fuse element for redundancy selection can be cut off at the same time, the replacement program process is remarkably simplified. Reduced to a minimum. Moreover, by keeping the arrangement order of the plural sets of program fuse elements 50 arranged in series and the arrangement order of a plurality of redundant row decoders corresponding thereto, the address corresponding to the main row decoder to be relieved is maintained. It is possible to easily and reliably set the address of the redundant row decoder that wants to use (the rescue address) in the address storage circuit section. In this respect, the rescue error when using the redundant circuit due to a program error or the like is minimized. Will be reduced. <Second Embodiment> The SRAM redundancy circuit according to the first embodiment is connected to a normal main word line MWL as a program fuse element provided corresponding to the output side of each normal main row decoder 21a. And the corresponding normal main row decoder 21a is set in the non-selected state by cutting the disable fuse 52. It was set, but it is not limited to this. For other redundant circuits that realize the same function,
This will be described in a second embodiment.

FIG. 7 shows a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a specific example by extracting a part of an SRAM. The circuit shown in FIG. 7 is different from the circuits shown in FIGS. 3 to 6 in that (1) it is provided corresponding to each normal main row decoder 21a and controls the enable / disable state of the corresponding normal main row decoder. In that a plurality of normal address decoder control circuits 70 are added. (2) A plurality of fuse elements (aluminum fuses) 71 corresponding to the plurality of redundant row decoders on a one-to-one basis are arranged in series in the programming fuse elements provided corresponding to the output side of each normal main row decoder 21a. And
The points are arranged in parallel near (slightly away from) the normal main word line MWL. (3) Each fuse element 71 is connected to not only one set of address registers 60x to 600 provided corresponding to each normal main row decoder 21a but also one normal address decoder control circuit 70. Are different, and the others are the same. FIG. 8 shows a set of address registers 60x in FIG.
FIG. 6 is a circuit diagram showing a specific example of one of 600 to 600, a normal address decoder control circuit 70, a normal main row decoder 21a, and a normal main word line MWL.

Referring to FIG. 8, an address register 600
Has the same configuration as the address register 600 described above with reference to FIG. Normal address decoder control circuit 70
Is composed of a NOR gate 70 to which the potentials of the signal lines 611 to 614 connected to one ends of the four fuse elements 71 are inputted. The output signals of the NOR gate 70 enable / deactivate the corresponding normal main row decoder 21a. This becomes the disable control input. The operation of the SRAM shown in FIG. 7 and FIG. 8 is basically the same as the operation of the SRAM shown in FIG. 3 to FIG. That is, when none of the four fuse elements 71 is disconnected (when the corresponding normal main row decoder 21a is used), the signal line 611 is used.
614, the pull-down potential VSS is input to the NOR gate 70, and the corresponding normal main row decoder 21a is controlled to be selectable by the output potential VCC of the NOR gate 70. On the other hand, when any one of the four fuse elements 71 is cut, any one of the signal lines 611 to 614 corresponding to the cut fuse element 71 is cut.
From this, the pull-up potential VCC is input to the NOR gate 70, and the corresponding normal main row decoder 21a is controlled to be unselectable by the output potential VSS of the NOR gate 70 at this time.

The output of one set of address registers 60x-600 is enabled by the pull-up potential VCC from the signal line corresponding to the cut fuse element 71, and the replacement address signals Ax-A0 are output. , The corresponding redundant row decoder becomes available. According to the SRAM of the second embodiment, the SRAM of the first embodiment
Basically, the same effect as that of the SRAM can be obtained. In addition, since the fuse element for programming is one fuse element 71 for one redundant row decoder, the pattern area of the fuse element for programming can be small. <Third Embodiment> Another redundant circuit realizing the same function as the SRAM redundant circuit of the first embodiment will be described in the third embodiment.
An embodiment will be described. FIG. 9 is a circuit diagram showing a specific example of a part of the SRAM according to the third embodiment of the present invention, which corresponds to FIG. 5 in the description of the SRAM according to the first embodiment of the present invention. Is what you do. That is, the circuit diagram shown in FIG. 9 is a modified example of the circuit diagram shown in FIG. 5, which is a circuit diagram in which a part of FIG. 4 is extracted and shown in detail. Therefore, the description of the overlapping part will be omitted. The circuit shown in FIG. 9 is different from the circuit shown in FIG. 5 in that (1) only one set of programming fuse elements is connected to each normal main row decoder 21a.

(2) Each of the address registers 60x to 600 connected to the redundancy selecting fuse 52 is connected to only one of the four replacement address signal lines 53. Is different. In FIG. 9, corresponding to the output side of each normal main row decoder 21a, a programming fuse element which is cut when the corresponding normal main row decoder 21a is programmed to a non-selected state is arranged and a redundant address decoder is designated. Circuits (address registers 60x to 600 in this example) are provided. In the present embodiment, one set of address registers 60x
To 600 are provided corresponding to one redundant row decoder. That is, each normal main row decoder 21a
And the redundant row decoder that replaces it are associated in advance. In FIG. 9, four redundant row decoders are associated with each of the four normal main row decoders 21a. FIG. 10 shows one bit (for example, A) of the address signals Ax to A0 supplied from the set of address registers 60x to 600 in FIG.
FIG. 3 is a circuit diagram representatively showing in detail a 1-bit address register 600 for generating (0).

In FIG. 10, a signal line 61 is connected to the redundancy selecting fuse 52 and has a resistance element R
For example, to a power supply node. As a result, when the corresponding redundant selection fuse 52 is in the non-cut state, it is pulled down to the ground potential VSS, and when it is cut, it is pulled up to the power supply potential VCC. Latch circuit 65
Has two CMOS inverter circuits connected in anti-parallel and has an input node b connected to a power supply potential V
The output node c is connected to either the CC node or the ground potential VSS node.
("H") or VSS ("L"). At this time, each output potential of each latch circuit 65 of one set of address registers 60x to 600 corresponds to a comparison input (address signals A0 to Ax) supplied to the address comparison circuit unit 20 of the redundant row decoder to be used. In this way, the connection destination (VCC or VSS) of the wiring 66 on the input side of each latch circuit is selected and set. The signal line is connected to the gate of the NMOS transistor 67.
61 is connected, the drain is connected to the output node c of the latch circuit 65, and the source potential is one bit A0 of each of the comparison inputs (address signals Ax to A0) of the address comparison circuit unit 20. Enter as

The NMOS transistor 67 is turned on when VCC is applied from the signal line 61 connected to the gate, passes the output potential of the latch circuit 65 to the source, and when the VSS is applied. Has a role of controlling the enable / disable of the outputs of Ax to A0 by turning off the source potential to electrically float (high impedance state). On the other hand, when using the redundant circuit (when using any of the redundant row decoders),
A set of two aluminum fuses that are fuse elements 50 on the output side of the normal main row decoder 21a to which the normal main word line MWL to be relieved is connected.
Cut (program) 51 and 52 by one fuse blow. Normal main word line MWL to be relieved by cutting fuse 52 for redundancy selection
Is connected to the address comparison circuit section 20 corresponding to the redundant row decoder. Therefore,
Thereafter, when the address signal input hits the rescue address during normal operation (when the address input is a defective address), the match detection signal output from the address comparison circuit unit 20 in which the rescue address is set is activated. ,
The corresponding redundant main word line drive circuit 21b is activated, and the corresponding redundant main word lines R / D MWL-1 to R / DM
Select WL-4.

With this configuration, the number of fuse elements can be reduced as compared with the first and second embodiments, and an effect of reducing the chip area can be obtained. Also, by programming the redundant row decoders that rescue each normal main row decoder on a one-to-one basis, a system can be realized in which the redundant row decoders can be automatically allocated. In each of the above embodiments, an example has been described in which a main word line of an SRAM having a double word line configuration is rescued. However, the present invention is not limited to the above example. Applicable to memory.

[0026]

As described above, according to the semiconductor memory device of the present invention, it is possible to improve the programming process for a fuse element when a redundant circuit is used, and to simply and reliably replace a defective memory cell with a redundant memory cell. it can. That is,
A redundant circuit system can be realized in which only the fuse element for programming on the output side of the normal decoder need be selectively disconnected without programming the repair address of the decoder to be replaced when the redundant circuit is used. Therefore, the setting of enable / disable at the time of using the redundant circuit required in the conventional semiconductor memory device and the programming process are simplified as compared with the programming of the relief address. Is reduced to a minimum, and an improvement in yield can be expected. Further, since the normal decoder can be directly disabled only by selectively disconnecting the programming fuse element, an access delay when the redundant circuit is used is reduced to a minimum.

[Brief description of the drawings]

FIG. 1 is a view showing a pattern layout on an SRAM chip according to a first embodiment of the present invention;

FIG. 2 shows an area corresponding to a quarter block in FIG. 1 as a normal main row decoder group and a group of fuse elements for programming, an address register group, a main word line group and eight The figure which extracts a section and shows a detailed pattern layout.

FIG. 3 is a diagram showing a pattern layout by representatively extracting a part of a normal main row decoder, a program fuse element group, an address register group corresponding to row addresses Ax to A0, and a normal main word line group in FIG. 2; .

4 shows a normal main row decoder, a program fuse element group, an address register group, a normal main word line group, a redundant row decoder group, a redundant main word line group, and a part of a section in the main row decoder group in FIG. 2; The block diagram which takes out and shows typically.

FIG. 5 is a circuit diagram showing a part of FIG. 4 in detail.

FIG. 6 shows a representative example of a 1-bit address register for generating one bit (for example, A0) of an address signal supplied to the address comparison circuit unit from a set of address registers in FIG. FIG.

FIG. 7 is a circuit diagram showing a specific example by extracting a part of an SRAM according to a second embodiment of the present invention;

FIG. 8 is a circuit diagram showing a specific example of one of a set of address registers in FIG. 7, and a normal address decoder control circuit, a normal main row decoder, and a normal main word line.

FIG. 9 is a circuit diagram showing a specific example of an SRAM according to a third embodiment of the present invention, in which a part corresponding to a part of FIG. 4 is extracted;

FIG. 10 representatively extracts a 1-bit address register for generating one bit (for example, A0) of an address signal supplied to the address comparison circuit unit from a set of address registers in FIG. FIG.

[Explanation of symbols]

 MWL: Normal main word line, R / D MWL-1 to R / D MWL-4: Redundant main word line, 13: Fuse & address register, 20: Address comparison circuit, 21a: Normal address decoder, 21b: Redundant address Decoder, 50: fuse element for program, 51: disable fuse, 52: fuse for redundant selection, 60x to 600: address register.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B015 JJ00 KA28 KB44 KB52 NN09 QQ01 QQ15 5B018 GA10 HA24 MA06 NA03 PA01 5L106 AA02 CC04 CC13 CC17 CC21

Claims (15)

[Claims] A memory cell array including a normal memory cell for normal access and a redundant memory cell for repairing a defective memory cell; a plurality of normal address decoders for selecting a normal memory cell of the memory cell array; A plurality of redundant address decoders for selecting redundant memory cells, and a fuse for programming provided corresponding to an output side of each of the normal address decoders and cut when programming the normal address decoders to a non-selected state. An element, provided corresponding to each of the normal address decoders,
A redundancy address decoder designating circuit for producing a redundancy address decoder designation address signal for designating an address of a redundancy address decoder replacing a normal address decoder corresponding to the program fuse element when the program fuse element is cut off; A semiconductor memory device comprising: 2. The program fuse element according to claim 1, wherein two fuse elements arranged in parallel constitute one set, and a plurality of sets of fuse elements corresponding one-to-one with the plurality of redundant address decoders are arranged in series. 2. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor memory according to claim 2, wherein said pair of two fuse elements are arranged in parallel with a minimum wiring interval, and are each cut by a single fuse blow. apparatus. 4. One of the two fuse elements in the set is inserted in series with an output signal line of the normal address decoder, and the other fuse element is connected to the redundant fuse element. 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is connected to an address decoder designating circuit and, when disconnected, enables the redundant address decoder designating circuit to output the redundant address decoder designating address signal. . 5. The arrangement order of the plurality of fuse elements arranged in series and the arrangement order of the plurality of redundant address decoders corresponding to the plurality of sets of fuse elements are the same. 5. The semiconductor memory device according to any one of 2 to 4. 6. A memory cell array including normal memory cells for normal access and redundant memory cells for repairing defective memory cells, a plurality of normal address decoders for selecting normal memory cells in the memory cell array, and the memory cell array A plurality of redundant address decoders for selecting redundant memory cells, and a fuse for programming provided corresponding to an output side of each of the normal address decoders and cut when programming the normal address decoders to a non-selected state. An element, provided corresponding to each of the normal address decoders,
A redundancy address decoder designating circuit for producing a redundancy address decoder designation address signal for designating an address of a redundancy address decoder replacing a normal address decoder corresponding to the program fuse element when the program fuse element is cut off; , Provided corresponding to the plurality of normal address decoders.
A plurality of normal address decoder control circuits for controlling a disable state, wherein the program fuse element includes a plurality of fuse elements corresponding to the plurality of redundant address decoders in a one-to-one correspondence, arranged in series. A semiconductor memory device characterized in that: 7. The program fuse element is arranged separately from an output signal line of the normal address decoder, and is provided in the redundant address decoder designating circuit and the normal address decoder control circuit provided corresponding to the normal address decoder. The redundant address decoder designating circuit outputs the redundant address decoder designating address signal in accordance with the connected and disconnected state, and the normal address decoder control circuit generates a control signal for setting the normal address decoder to a non-selection state. 7. The semiconductor memory device according to claim 6, wherein: 8. The arrangement order of the plurality of fuse elements arranged in series and the arrangement order of the plurality of redundant address decoders corresponding to the plurality of fuse elements are the same. 8. The semiconductor memory device according to 7. 9. The redundant address decoder designating circuit is provided in a set corresponding to the normal address decoder, and a redundant address decoder designating address signal for designating an address of a redundant address decoder to be replaced with the normal address decoder. And an address register for controlling the enable / disable of the output of the redundant address decoder designation address signal in accordance with disconnection / non-disconnection of the corresponding program fuse element. 9. The semiconductor memory device according to any one of 1 to 8. 10. The comparison circuit for comparing a redundant address decoder with a substantially same address signal as the normal address decoder and a redundancy address decoder designation address signal supplied from the redundancy address decoder designation circuit. 10. The semiconductor memory device according to claim 1, further comprising: a redundant word line drive circuit activated by a match detection output of the semiconductor memory device. 11. The semiconductor memory device according to claim 1, wherein said redundant memory cell has a plurality of rows or a section scale. 12. The program fuse element is provided for each of the plurality of normal address decoders, and corresponds to one redundant address decoder of the plurality of redundant address decoders. The semiconductor memory device according to claim 1. 13. The semiconductor memory device according to claim 1, wherein said redundant address decoder designating circuit corresponds to one redundant address decoder of said plurality of redundant address decoders. 14. The program fuse element comprises a pair of two fuse elements arranged in parallel, and
13. The fuse element according to claim 1, wherein the fuse elements are arranged with a minimum wiring interval.
13. The semiconductor memory device according to item 9. 15. One of the pair of two fuse elements is formed in series with an output signal line of the normal address decoder, and the other fuse element is formed of the redundant fuse element. 15. The semiconductor memory device according to claim 14, wherein said semiconductor memory device is connected to an address decoder designating circuit and, when disconnected, enables said redundant address decoder designating circuit to output said redundant address decoder designating address signal.