JP2001203738A - Bus control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus control system for a fast LAN interface capable of performing data transfer with fast Ethernet by using a plurality of data transfer buses in a system which holds a plurality of internal buses for data transfer and houses a fast Ethernet LAN such as gigabit Ethernet. SOLUTION: This system has bus bridge circuits 90 and 100 for distributing data transfer to the plurality of data transfer buses 50 and 60 and controlling the data transfer, an internal bus 105 connecting the circuits 90 and 100, a master that makes the circuits 90 and 100 perform master/slave operation and nonmaster instruction signals 106 and 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system, and more particularly to a bus control system for speeding up data transfer of a LAN (Local Area Network) interface using a plurality of buses.

[0002]

2. Description of the Related Art LAN such as Ethernet
Is 10Mbp in 10BASE-T
s, 200BASE-TX (at full-duplex communication) even in 100BASE-TX, and the transfer capacity of the internal data transfer bus in the system (in general, 20M for a 32-bit internal data bus).
B / S〜133 MB / S).
Systems that monitor the problem of the data transfer capacity of LAN data include LAN devices such as workstations (WS), personal computers (PC), and routers. The router can be considered to be a WS or PC having two LAN interfaces. In such a device, data input from the LAN is converted into software (S
/ W) and output to another LAN. Here, the processing capacity of the S / W is a bottleneck rather than the data transfer capacity, and the problem regarding the transfer capacity of the data transfer bus was not discussed.

In recent years, switching hubs and the like have
A device that transfers data between LANs in hardware without passing through the Internet has appeared. Such a LAN interface is connected to an internal data bus, and can perform high-speed data switching (switching) without using S / W within the data transfer capacity of this bus. In addition, a LAN interface having a data transfer capacity of 2000 Mbps, such as a gigabit Ethernet, has appeared, and the demand for a faster data transfer bus has been increasing.

In order to meet the demand for improving the transfer performance of such a data transfer bus, for example, Japanese Patent Laid-Open Publication No. Hei 3-188553 discloses a "dual bus system of a multiprocessor system" as shown in FIG. This system includes a first bus forming a system bus 1 and a processor (M).
PU) 2, 3, and 4 and a second bus 5 for connecting the main memory 6 to the main bus. Further, bus controllers 8 and 9 are connected to these buses 1 and 5, respectively, and an I / O 7 is connected to the system bus 1.
The main memory 6 is divided into a first main memory (buffer memory) 10 and a second main memory 11 by an address, and is connected to the first and second buses 1 and 5, respectively, on a one-to-one basis. When the processors 2 to 4 access the main memory 6, the first and second main memories 10 and 11 to which the first and second main memories 10 and 11 are connected are designated by addresses.
Select and acquire buses 1 and 5, perform memory access,
Enables synchronous access to divided memory. Thereby, the speed of the buses 1 and 5 is improved. That is, in the prior art disclosed in this prior art document, MPUs 2 to 4
The main memory is divided into two memories 10 and 11 by an address, and connected to the corresponding system buses 1 and 5 to connect to the two main memories 10 and 11 of the processors 2 to 4. By enabling simultaneous access, the speed of the bus is improved.

Japanese Patent Laid-Open Publication No. 4-333947 discloses "I / O access control method in dual bus system", which discloses an I / O access control method as shown in FIG. That is, two shared buses B1 and B2 and a plurality of input / output units (I / O) 6 connected to the shared buses, respectively.
-1, 6-2 and a plurality of bus masters 1-1, 1-2 capable of accessing the respective shared buses B1, B2, in an I / O access control system in a dual bus system, each bus master 1-1, 6-2. 1-2 is a processor unit 2-
1 and 2-2, and a monitoring circuit 3 for comparing whether or not the I / O that these processor units are trying to access and the I / O currently being accessed through the shared bus are the same.
1, 3-2, and two gate circuits 4-1 for a bus access request signal that is opened and closed by these monitoring circuits,
4-2, 5-1 and 5-2, and the monitoring circuit 3-
The gate circuit is closed when the comparison results of 1 and 3-2 are the same, and the gate circuit is opened when the comparison results are not the same. The prior art disclosed in the prior art document does not require switching of I / O connection and other complicated control, and enables each bus master to efficiently access I / O.

[0006] Further, Japanese Unexamined Patent Publication No. 10-84368 discloses a technique of providing a dedicated bus for receiving data of an uplink port by Gigabit Ethernet for a transmission port of 100 MHz Ethernet in "switching hub with uplink". are doing.

However, the above-mentioned prior art aims to speed up the access of the MPU to the main memory or the I / O device, and the means for speeding up data transfer using a plurality of data transfer buses is as follows. Same, but not intended to accommodate a high-speed LAN interface. Also, instead of using a plurality of data transfer buses, there are techniques for increasing the bit width of the data transfer bus itself (32 bits → 64 bits) and for increasing the clock frequency (33 MHz → 66 MHz). It is not practical because it requires a complete hardware change. Also, even in the last prior art described above,
Since a dedicated bus is provided and the transmission capacity is compensated for in this portion, it is necessary to completely change the existing hardware. Furthermore, since a means (address resolution circuit) for determining a transmission port for received data is used for each reception port, the circuit scale is increased.

[0008]

In a switching hub, there are "terminals" connected by Ethernet in a group called "port number". This port number is
It is also used to determine the data transfer bus present in the switching hub. When performing communication between terminals connected under the switching hub, "terminal number (MAC
Address) "and" port number "must be unique. This is a very important rule to detect the movement of the terminal between the ports and to prevent the broadcasted data from being retransmitted to the broadcast source and from being permanently looped. This rule is followed.

However, in order to increase the data transfer capacity in the existing system, a plurality of data transfer buses must be held,
Although there is no other means than increasing the capacity, the addition of a bus bridge for this causes the addition of a port number. Gigabit Ethernet supports full-duplex communication, and it is considered to be effective to configure one bus bridge for transmission and one bus bridge for reception in total. However, this is "terminal number (MAC address)
And port numbers do not match. "

[0010]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a bus control system which enables high-speed data transfer with Ethernet.

[0011]

According to the bus control method of the present invention, a plurality of bus bridge circuits connected to a switching processor connected to a buffer memory via a data transfer bus and mutually connected by an internal bus are provided. A gigabit Ethernet LAN control circuit and the like are connected to these bus bridge circuits via a reception data transfer bus and a transmission data transfer bus, respectively. The bus bridge circuit has a master mode instruction for operating in a master mode and a non-master mode, respectively. A signal and a non-master mode instruction signal are input.

According to a preferred embodiment of the present invention, the switching processor is further connected to one or more LAN ports via a LAN port bus bridge circuit. Further, a search memory, which is a search table memory for deriving an arbitrary port number, is connected to the switching processor via an address resolution circuit for determining a transmission destination. Further, a plurality of entries including a MAC address, a port number, and the like to be searched by the address resolution circuit are set in the search memory. In addition, a switching hub having a plurality of ports connected to a plurality of clients via a shared cable and a port connected to a server device via an optical cable is configured.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above-mentioned objects, features and advantages of the present invention, the structure and operation of a preferred embodiment of a bus control system according to the present invention will be described in detail with reference to the accompanying drawings. explain.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a bus control system according to the present invention. This bus control method includes a buffer memory 10, a switching processor 20, an address resolution circuit 30, a search memory 4
0, bus bridge circuit (1) 90, bus bridge circuit (2) 100, LAN port (1) 120, bus bridge circuit 110 of LAN port (1), LAN port (2) 140, bus of LAN port (2) Bridge circuit 130, Gigabit Ethernet LAN control circuit 150
And a Gigabit Ethernet LAN port 180.

[0015] The bus control method of this specific embodiment is based on a gigabit Ethernet LAN, one line, 100 Mbps.
The switching hub accommodates two Ethernet LANs. The buffer memory 10 temporarily stores the packet data in the switching hub. The switching processor 20 manages data received from each LAN port using the buffer memory 10. Upon receiving an address resolution request from the switching processor 20, the address resolution circuit 30 determines a destination port from a DA (destination address) included at the beginning of the packet. The search memory 40 is a search table memory for the address resolution circuit 30 to execute a search using DA as a key and derive an arbitrary port number.

The switching processor 20 has a first data transfer bus 50, a second data transfer bus 60, a third data transfer bus 70, and a fourth data transfer bus 80.
First to fourth data transfer buses 50, 60, 70 and 8
0 is the switching processor 20, the bus bridge circuit (1) 90, the bus bridge circuit (2) 100, L
Bus bridge circuit 110 and LA of AN port (1)
It is connected between the bus bridge circuit 130 of the N port (2). These data transfer buses 50 to 80 are:
For example, it has a data width of 32 bits and operates with a synchronous clock of 33 MHz.

The bus bridge circuit (1) 90 connects the Gigabit Ethernet LAN port to the first data transfer bus 50.
It is a circuit for bridging with. The bus bridge circuit (2) 100 is a circuit for bridging a gigabit Ethernet LAN port with the second data transfer bus 60. Bus bridge circuit 110 of LAN port (1)
Is the 100Mbps LAN port (1) 120 as the third
This is for bridging with the data transfer bus 70. LA
The bus bridge circuit 130 of the N port (2)
The bps LAN port (2) 140 is a circuit for bridging with the fourth data transfer bus 80. The LAN port (1) 120 and the LAN port (2) 140 are both 100 Mbps LAN ports. The bus bridge circuit (1) 90 and the bus bridge circuit (2) 100 are connected by an internal bus 105. A master mode instruction signal 106 for operating this circuit in the master mode is input to the bus bridge circuit (1) 90.
Further, a non-master mode instruction signal 107 for not operating this circuit in the master mode is input to the bus bridge circuit (2) 100.

The reception data transfer bus 160 is a bus for transferring reception data from the gigabit Ethernet LAN control circuit 150 to the bus bridge circuit (1) 90, has a data width of, for example, 32 bits, and uses a synchronous clock of 33 MHz. Operate. The transmission data transfer bus 170 is a bus for transmitting transmission data from the bus bridge circuit (2) 100 to the gigabit Ethernet LAN control circuit 150, has a data width of, for example, 32 bits, and operates with a synchronous clock of 33 MHz. The Gigabit Ethernet LAN control circuit 150 is a Gigabit Ethernet L
It is connected to AN port 180.

In a switching hub as shown in FIG. 1, a port number is used to identify a port in the system. The port number is usually about 8 bits (00 in hexadecimal).
Or about 256 types of FFs). In this embodiment, the Gigabit Ethernet LA
The port number “10” is assigned to the N port 180. "20" is assigned to the LAN port (1) 120,
It is assumed that the port number “21” is assigned to the LAN port (2) 140. Address resolution circuit 3 in FIG.
0, Gigabit Ethernet LAN control circuit 150, L
The details of the bus bridge circuit 110 of the AN port (1) and the bus bridge circuit 130 of the LAN port (2) are well known to those skilled in the art, and are not directly related to the present invention, so that the detailed description thereof will be omitted. I do.

FIG. 2 shows the external connection of the switching hub 300 shown in FIG. The gigabit Ethernet LAN port (port number “10”) is connected to the server device 310 via the optical cable 360. The client (PC1) 320 and the client (PC2) 330 are connected to the 100 Mbps port with the port number “20” by a shared cable 370. The client (PC3) 340 and the client (PC4) 350 are connected to the 100 Mbps port with the port number “21” by a shared cable 380.

FIG. 3 shows a configuration example of information arranged in the search memory 40 shown in FIG. In one entry,
MAC address 40 searched by address resolution circuit 30
0 (for example, 6 bytes) and the port number 410 (for example, 2 bytes)
Bytes), VLAN (virtual LAN) information, etc.
It is composed of information 420 (for example, 2 bytes) indicating transmission permission / non-permission of the packet. Here, entry (1)
Indicates the MAC address of the server device and the port number “1”.
0 "is set. The entry (2) contains the MAC address of the client (PC4) and the port number “2”.
1 "is set. The entry (3) has the MAC address of the client (PC2) and the port number “2”.
"0" is set. In the entry 4, the MAC address of the client (PC1) and the port number “20” are set. In the entry (5), the MAC address of the client (PC3) and the port number “21” are set. These entries are set in advance by S / W. Since this setting method is not directly related to the present invention, the detailed description thereof is omitted.

FIG. 4 shows an example of the format of data input to the switching processor 20 from each LAN port in FIG. This is configured in the Ethernet frame format. That is, a destination address (MAC address: media access control address) of 6 bytes from the top. Following this MAC address is a 6-byte source address and a 2-byte type field. Finally, it is well known that it is composed of data and an error detection code (FCS).

Hereinafter, the operation of the preferred embodiment of the present invention shown in FIGS. 1 to 4 will be described as a unicast reception operation from a 100 Mbps port, a unicast reception operation from a gigabit Ethernet port, and a broadcast reception operation from a 100 Mbps port. And a broadcast receiving operation from a Gigabit Ethernet port will be described in this order.

(1) Unicast Reception Operation from 100 Mbps Port First, the unicast packet data received from the 100 Mbps LAN port (2) 140 is transmitted at 100 Mbps.
The operation of switching to the sLAN port (1) 120 will be described. [1] The port number and the received data are output from the 100 Mbps LAN port (2) 140 to the fourth data transfer bus 80 by the bus bridge circuit 130. [2] The switching processor 20 fetches this data, and stores this data at an arbitrary address in the buffer memory 10. Then, the address (referred to as a pointer) of the buffer memory 10 is stored. [3] At the same time, the DA (destination address), SA (source address) and the received port number included in the head of the packet are transmitted to the address resolution circuit 30. [4] The address resolution circuit 30 searches the information stored in the search memory 40 for a corresponding port number. [5] The address resolution circuit 30 returns the read port number to the switching processor 20. [6] The switching processor 20 determines the data transfer bus based on the port number (in this case, the third data bus 70), and transmits the pointer of the buffer memory 10. [7] The bus bridge circuit 110 requests the pointer of the buffer memory 10 from the switching processor 20 and extracts data to be transmitted from the buffer memory 10. [8] The bus bridge circuit 110 receives the data and
It transmits to the 00 Mbps LAN port (1) 120. [9] The bus bridge circuit 110 transmits a pointer of the buffer memory 10 and a buffer release instruction to the switching processor 20 to release the buffer memory 10 upon completion of the transmission. [10] The switching processor 20 releases the buffer memory 10. [11] The switching processor 20 transmits a packet transmission completion instruction to the bus bridge circuit 130 of the reception LAN port (2) 140.

(2) Unicast Reception Operation from Gigabit Ethernet Support Next, the unicast packet data received from the Gigabit Ethernet LAN port 180 is 100 Mb.
The operation of switching to the psLAN port (1) 120 will be described. In order to maximize the data transfer capability of the Gigabit Ethernet, the load of received data is distributed to the bus bridge circuit (1) 90, and the load of transmitted data is distributed to the bus bridge circuit (2) 100. [1] Received data is output from the gigabit Ethernet LAN port 180 to the first data transfer bus 50 by the bus bridge circuit (1) 90 via the receive data bus 160. Note that the bus bridge circuit (1) 90 receives the port number (in this case, “1
0 ") is valid. The operations [2] to [5] are the same as the operation (1) described above. [6] The switching processor 20 calculates, from the port number,
Determine the data transfer bus (in this case, the first data bus 5
0), the stored pointer of the buffer memory 10 is transmitted. [7] The bus bridge circuit (1) 90 includes the buffer memory 1
0 pointer is received and the bus bridge circuit (2) 10
0, using the bus bridge internal bus 105,
The pointer of the buffer memory 10 is transmitted. [9] The bus bridge circuit (2) 100 requests the pointer of the buffer memory 10 from the switching processor 20, and extracts the data to be transmitted from the buffer memory 10. (Note that the bus bridge circuit (2) 100 is instructed by the non-master instruction signal 107 that the port number is not valid.) [10] The bus bridge circuit (2) 100 sends the Gigabit Ethernet LAN control circuit 150 Transmission data bus 17
Send the transmission data via 0. [11] Gigabit Ethernet LAN control circuit 150
Sends data. [12] The bus bridge circuit (2) 100 transmits the pointer of the buffer memory 10 and the buffer release instruction to the switching processor 20 to release the buffer memory 10 when the transmission is completed. [13] The switching processor 20 releases the buffer memory 10. [14] The switching processor 20 transmits a packet transmission completion instruction to the bus bridge circuit (1) 90 of the reception port.

(3) Broadcast Reception Operation from 100 Mbps Port An operation in which broadcast packet data received from a 100 Mbps LAN port (2) 140 is switched to all ports other than its own will be described. [1] to [3] are the same as the above-described operation (1). [4] In the address resolution circuit 30, DA is "FFFFFF"
(Broadcast address), and searches all the corresponding port numbers from the information stored in the search memory 40. [5] The address resolution circuit 30 returns all the read port numbers (in this case, “20” and “10”) to the switching processor 20. [6] The switching processor 20 determines the data transfer bus from the port number (in this case, the first data bus 50
And the third data bus 70), and transmits the pointer of the buffer memory 10. [7] The bus bridge circuit 110 requests the pointer of the buffer memory 10 from the switching processor 20 and extracts data to be transmitted from the buffer memory 10. [7] 'The bus bridge circuit (1) 90 is connected to the internal bus 105
Is used to transmit the pointer of the buffer memory 10 to the bus bridge circuit (2) 100. The bus bridge circuit (1) 90 requests the pointer of the buffer memory 10 from the switching processor 20, and extracts data to be transmitted from the buffer memory 10. [8] The bus bridge circuit 110 receives the data and
It transmits to the LAN port (1) 120 of 0 Mbps. [8] ′ The bus bridge circuit (2) 100 receives the data and transmits the data to the Gigabit Ethernet LAN control circuit 150 using the transmission data bus 170. [9] The bus bridge circuit 110 transmits the pointer of the buffer memory 10, the buffer memory release instruction, and the port number “20” to the switching processor 20 to release the buffer memory 10 when the transmission is completed. [9] 'The bus bridge circuit 100 transmits the pointer of the buffer memory 10, the buffer memory release instruction, and the port number “10” to the switching processor 20 to release the buffer memory 10 when the transmission is completed. [10] The switching processor 20 outputs “10” and “2”
After confirming that the two ports “0” have transmitted the broadcast, the buffer memory 10 is released. [11] The switching processor 20 transmits a packet transmission completion instruction to the bus bridge circuit 130 of the reception port.

(4) Broadcast Reception Operation from Gigabit Ethernet Support An operation in which broadcast packet data received from the Gigabit Ethernet LAN port 180 is switched to all ports other than the own port will be described. In order to maximize the data transfer capability of the Gigabit Ethernet LAN, the received data is transmitted by the bus bridge circuit (1) 90, and the transmitted data is transmitted by the bus bridge circuit (2).
Load distribution. [1] to [3] are the same as the operation of (2) described above. [4] In the address resolution circuit 30, DA is "FFFFFF"
(Broadcast address), and searches all the corresponding port numbers from the information stored in the search memory 40. [5] The address resolution circuit 30 returns all the read port numbers (in this case, “20” and “21”) to the switching processor 20. [6] The switching processor 20 determines the data transfer bus from the port number (in this case, the third data bus 70
And the fourth data bus 80), and transmits the stored pointer of the buffer memory 10. [7] Bus bridge circuit 11 of LAN port (1) 120
0, the bus bridge circuit 130 of the LAN port (2)
Requests the pointer of the buffer memory 10 to the switching processor 20, and stores the data to be transmitted in the buffer memory 1.
Take from 0. [8] Bus bridge circuit 11 of LAN port (1) 120
0, bus bridge circuit 13 of LAN port (2) 140
No. 0 receives data and transmits the data to the LAN port (1) 120 and the LAN port (2) 140 of 100 Mbps. [9] Bus bridge circuit 11 of LAN port (1) 120
0, bus bridge 130 of LAN port (2) 140
Transmits the buffer memory 1 to the switching processor 20 in order to release the buffer memory 10 when the transmission is completed.
0 pointer, buffer release instruction and port number "2"
"0" and "21" are transmitted. [10] The switching processor 20 determines “20” and “2”
After confirming that the two ports “1” have transmitted the broadcast, the buffer memory 10 is released. [11] The switching processor 20 transmits a packet transmission completion instruction to the bus bridge circuit (1) 90 of the reception port.

In the operations (1) and (2) and the operations (3) and (4), the operations from [2] to [5], that is, the operations of the switching processor 20 and the address resolution circuit 30 are the same. This is a feature of the present invention.
In Gigabit Ethernet, transmission 1024Mbps
(128 MB / s), 1024 Mbps (1
28 Mbytes / sec), requiring a total of 256 Mbytes / sec data transfer. However, it is generally difficult to achieve a data transfer rate of 100 megabytes / second or more with a 32-bit data transfer bus. Therefore, in the present invention, load sharing of data transfer is performed by using the two bus bridge circuits (1) 90 and (2) 100. However, the general switching processor 20 is based on the premise that the reception port and the transmission port are the same. This is because a conventional bus bridge circuit such as a 100 Mbps LAN determines the number of ports to be accommodated in accordance with the upper limit of the capacity of the data transfer bus. In fact,
A bus bridge circuit accommodating four 100 Mbps LANs has been commercialized, but even in this case, 800 Mbps
(100 megabytes / second), and there is no need to distribute the data transfer bus.

In the present invention, the bus bridge circuit (1) 90
Are recognized by the switching processor 20 and the address resolution circuit 30. Then, it is considered that the problem can be solved by setting a port number of “11” to the bus bridge circuit (2) 100 and rewriting the entry 1 of the port number 410 in the search memory 40 of FIG. However, this causes a problem that the movement of the terminal cannot be detected. The address resolution circuit 30 searches the port number from the DA,
At this time, the port numbers are compared, and if the port numbers are different, processing for changing the contents of the search memory 40 is performed.
This means that the movement of the terminal has been detected.

The client (PC4) 350 in FIG.
Although connected to port “21”, this is connected to port “2”.
When the address is moved to “0” and the packet is transmitted, the address resolution circuit 30 can detect the MAC address of the client (PC 4) 350 in the entry (2) of the search memory 40. However, the received port number is "20"
Whereas the port number stored in the search memory 40 is “21”. In this case, it is determined that the terminal has moved, and the port number is rewritten to “20”. For this operation, after rewriting the entry (1) in the search memory 40 to “11” and receiving a packet from the Gigabit Ethernet LAN port 180, the bus bridge circuit (1) 90 On the other hand, the port number “10” reports the reception of the packet, and the address resolution circuit 30
It incorrectly recognizes that the terminal has moved. As described above, the fact that “the reception port number and the transmission port number are different” greatly affects the basic operation of the switching hub.
However, it is very effective to distribute the load of the data transfer bus in order to improve the data transfer capability. Therefore, it can be said that using a plurality of bus bridge circuits and a plurality of data transfer buses with the same port number of the present invention to improve performance is a very effective means.

The configuration and operation of the preferred embodiment of the bus control system according to the present invention have been described above in detail. However, such embodiments are merely examples of the present invention and do not limit the present invention in any way. For example, in the above-described embodiment, the example in which the gigabit Ethernet LAN is distributed by two data transfer buses has been described. However, the transfer capacity of the data transfer bus itself is further reduced (the data width is reduced to about 8 bits). , Lower the clock frequency from 33MHz to about 13MHz) 100Mbps Ethernet and 10Mbp
It may be applied to s. A high effect can be expected as a means for accommodating a high-speed LAN with a technology one rank lower.

[0032]

As can be understood from the above description, according to the bus control system of the present invention, a plurality of load-balanced bus bridge circuits are connected by an internal bus, and only the master bus bridge assigns port numbers. Based on this basic configuration, there is a practically remarkable effect that a high-performance bus control method in which a high-speed Ethernet LAN such as a gigabit Ethernet is accommodated in existing switching hub hardware can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hardware configuration of a switching hub according to a preferred embodiment of a bus control system of the present invention.

FIG. 2 is a configuration diagram of a system including the switching hub of FIG. 1;

FIG. 3 is a diagram showing contents of a search memory in FIG. 1;

FIG. 4 is a diagram showing the contents of packet data in the switching hub of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a conventional multiprocessor system.

FIG. 6 is a configuration diagram of a conventional dual bus system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Buffer memory 20 Switching processor 30 Address resolution circuit 40 Search memory 50 to 80 Data transfer bus 90, 100 Bus bridge circuit 105 Internal bus 106 Master mode instruction signal 107 Non-master mode instruction signal 110, 130 Bus bridge circuit for LAN 120, 140 LAN port 150 Gigabit Ethernet LAN control circuit 160 Receive data transfer bus 170 Transmission data transfer bus 180 Gigabit Ethernet LAN port 300 Switching hub 310 Server device 320-350 Client 360 Optical cable 370, 380 Shared cable

Claims (5)

[Claims] A switching processor connected to a buffer memory is provided with a plurality of bus bridge circuits connected to each other via a data transfer bus and mutually connected by an internal bus. A gigabit Ethernet LAN control circuit and the like are connected via a reception data transfer bus and a transmission data transfer bus, and the bus bridge circuit receives a master mode instruction signal and a non-master mode instruction signal for operating in a master mode and a non-master mode, respectively. A bus control method characterized by being input. 2. The switching processor further comprises L
One or more LANs via a bus bridge circuit for AN port
The bus control method according to claim 1, wherein the port is connected. 3. A search memory, which is a search table memory for deriving an arbitrary port number, is connected to the switching processor via an address resolution circuit for determining a transmission destination. 3. The bus control method according to 1 or 2. 4. The bus control method according to claim 3, wherein a plurality of entries including a MAC address, a port number and the like searched by said address resolution circuit are set in said search memory. 5. A switching hub comprising a plurality of ports each connected to a plurality of clients via a shared cable and a port connected to a server via an optical cable. A bus control method according to any one of claims 1 to 4.