JP2001202242A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor capable of high speed processing at the time of decoding a variable length code with bit units such as a Huffman code or operating the rotation processing of a bit map. SOLUTION: A microprocessor is provided with an instruction for converting the leading variable length code among variable length encoded data aligned in word length into the corresponding code length. Also, this microprocessor is provided with a vector shift function and a function for obtaining carry data at the time of vector shift as a result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor or a coprocessor associated therewith, and more particularly to a microprocessor or a coprocessor associated therewith for decoding variable length codes such as Huffman codes. It relates to high-speed processing of high-speed processing and bitmap rotation processing.

[0002]

2. Description of the Related Art Conventionally, a microprocessor is assumed to process word-length data. When decoding a variable length code in bit units such as Huffman code, 1
In order to determine and decode the bit on / off bit by bit,
Processing time was very long. In order to process this at high speed, it has been proposed to decode a variable-length code into a prescribed equal-length value with one instruction. As a result, it is not necessary to determine whether each bit is on or off.

When a bit map is rotated by a microprocessor, data before rotation is loaded word by word, only one pixel information of a line after rotation is extracted from the word, and a bit after rotation is extracted. Processing for forming a map image has been performed in a loop. For example, a loop was processed 1024 times to rotate a bitmap image of 32 pixels × 32 pixels.

[0004]

When decoding the variable length code in bit units such as the Huffman code in the former case, a bit shift is necessary to align the next decode in order to continue decoding. Since the code has a variable length, the shift amount also differs each time. In the above-described conventional proposal, the shift amount is obtained by referring to the table using the decoded value. However, since the table access requires memory access, it is slow when a cache miss occurs in the cache. There was a problem that said.

[0005] The latter bitmap rotation process is one of the processes that affect the performance of the entire device, and high-speed processing is required. In order to speed up the bitmap rotation processing by the microprocessor, it is necessary to reduce the number of bitmap rotation processing loops.

Accordingly, a first object of the present invention is to provide a microprocessor capable of high-speed processing when decoding a bit-length variable-length code such as a Huffman code or a coprocessor attached to the microprocessor. .

A second object of the present invention is to provide a microprocessor (which may be accompanied by a coprocessor) capable of high-speed processing when performing a bitmap rotation process.

[0008]

In order to achieve the first object, the present invention provides a method for encoding a variable-length coded data arranged in a word length from a head variable-length code to a corresponding code. The present invention employs a microprocessor having an instruction to convert the length into a length.

According to the present invention, the coprocessor associated with the microprocessor further comprises an instruction for converting the first variable length code of the variable length coded data aligned to the word length into a corresponding code length. Is adopted.

In order to achieve the above-mentioned second object, the present invention employs a microprocessor having a vector shift function and a function of obtaining carry data at the time of vector shift as a result. It is.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a microprocessor with a coprocessor according to a first embodiment of the present invention. In FIG. 1, first, an instruction is obtained in an instruction fetch stage 101, and then the instruction is decoded in an instruction decode stage 102 and a coprocessor instruction decode 106. If the instruction is an integer instruction, the instruction is executed in the integer instruction execution unit 103, the memory is accessed in the memory access stage 104, and the result is reflected in the register in the write back stage 105.

If the instruction is an instruction to be executed by a coprocessor and is an instruction to decode to a value (DECV),
Decoding to the value of the variable length code is executed. If the instruction is to decode to the code length (DECS), the variable length code decoding unit 108 executes the decoding of the variable length code to the code length, and the coprocessor memory access stage. At 109, the memory is accessed, and at the write-back stage 110, the result is reflected in the register.

FIG. 2 is a table showing the function of the variable length code decode instruction. The DECV instruction outputs a value corresponding to each code as a result according to the upper bits of the source data rs.
Output d. In the DECS instruction, rd is output as a result of the code length corresponding to each code according to the upper bits of the source data rs.

FIG. 3 is a list of assembler programs of the Huffman code decoding program using the variable length code decoding instruction of the first embodiment.

(Embodiment 2) FIG. 4 is a block diagram showing a configuration of a microprocessor according to Embodiment 2 of the present invention. FIG.
First, an instruction is obtained in an instruction fetch stage 101, and then the instruction is decoded in an instruction decode stage 102. If the instruction is an integer instruction, the instruction is executed at the integer instruction execution unit 103 and at the execution unit 103.

If the instruction is a variable-length code decoding instruction and an instruction to decode (DECV), the variable-length code decoding unit 107 executes decoding to a variable-length code value, and decodes to a code length. If (DECS), the variable-length code decoding unit 108 decodes the variable-length code into a code length. Subsequently, the memory is accessed in the memory access stage 104, and the result is reflected in the register in the write-back stage 105.

FIG. 5 is a list of assembler programs of the Huffman code decoding program using the variable length code decoding instruction of the second embodiment.

(Embodiment 3) FIG. 6 is a block diagram showing a configuration of a microprocessor according to Embodiment 3 of the present invention. FIG.
First, the instruction memory 201
If the instruction is a normal instruction, data is extracted from the register file 202, an integer operation is performed by the integer operation execution unit 203, data is written back to the data memory 204, and data is returned to the register. , Then store the result in register file 202
Write back to

If the instruction is a vector shift instruction, vector shift is performed in a shiftable register, and carry data is collected into a word length, passed through a memory stage, and input to the register file 202.

FIG. 7 is a schematic diagram showing the operation of the left vector instruction added in this embodiment. In FIG. 7, when the left vector shift instruction is executed, all the values of the shiftable register 205 in the coprocessor are shifted left by one bit,
SB is supplemented with 0. Bits overflowing as carry are aligned in word length, and
Updated to the register specified by the operand.

FIG. 8 is a schematic diagram showing the operation of the right vector shift instruction added in this embodiment. In FIG. 8, when the right vector shift instruction is executed, all the values of the shiftable register 205 in the coprocessor are shifted right by one bit, and the MSB is supplemented with 0. Bits overflowing as carry are aligned in word length and stored in register file 20.
2 is updated to the register specified by the operand.

FIG. 9 is a schematic diagram showing the operation of the bit inversion instruction added in this embodiment. In FIG. 9, when the bit inversion instruction is executed, the MSB of the data stored in the source register of the register file 202 is changed to the LSB,
B is converted to MSB, and the result is written to the destination register specified by the operand.

FIG. 10 shows an example of the instruction extension using the instruction extension of this embodiment.
9 is an assembler program list for a process of rotating a 2-bit × 32-bit bitmap by 270 degrees. FIG.
First, in the loading process starting from the "LOAD:" label, the data of the original bitmap is loaded into the shiftable resist file 205 in the coprocessor, and the counter is initialized. In the subsequent rotation processing loop starting from the “ROTATE:” label, a left vector shift is performed first, the carry is bit-inverted, and the result is stored in the memory. This produces the first row of the bitmap with the first column rotated 270 degrees. Further, the loop counter is updated, the loop counter is updated, and it is determined whether or not the loop continues. This loop is executed 32 times. As a result, all the bits are stored in the bit map memory at the position rotated by 270 degrees.

(Embodiment 4) FIG. 11 is a block diagram showing a configuration of a microprocessor according to this embodiment. In FIG. 11, first, an instruction is fetched from the instruction memory 201. If the instruction is a normal instruction, data is fetched from the register file 202.

If the instruction is a vector shift instruction, vector shift is performed by the vector shift unit 601, and if the instruction is a carry extraction instruction, the carry extraction unit 60
2. Extract the carry. Subsequently, the data memory 204
If the data is to be written back to the register and the data is to be written back to the register, the result is then written back to the register file 202.

FIG. 12 is a schematic diagram showing the operation of the carry extraction instruction added in this embodiment. In FIG. 12, a carry extraction unit 602 for simultaneously processing eight 1-byte data sets data 8 to be carried out during vector shift.
The bit is updated in the destination register as the operation result.

FIG. 13 is a schematic diagram showing the operation of the left vector shift instruction added in this embodiment. In FIG. 13, 1
A vector shift unit 601 that processes eight pieces of byte data at the same time performs a shift, and updates the operation result to a destination register.

[0029]

As described above, according to the present invention,
Since the code length of the variable-length code can be obtained without requiring memory access, decoding of the variable-length code can be performed at high speed.

Further, according to the present invention, the number of loops of the program in the bitmap rotation processing can be reduced, so that the rotation processing can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a microprocessor with a coprocessor according to a first embodiment of the present invention.

FIG. 2 is a table showing functions of a variable length code decode instruction.

FIG. 3 is a list of assembler programs of a Huffman code decoding program using a variable length code decoding instruction according to the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of a microprocessor according to a second embodiment of the present invention.

FIG. 5 is a list of assembler programs of a Huffman code decoding program using a variable length code decoding instruction according to the second embodiment.

FIG. 6 is a block diagram illustrating a configuration of a microprocessor according to a third embodiment of the present invention.

FIG. 7 is a schematic diagram showing an operation of a left vector instruction added in the embodiment.

FIG. 8 is a schematic diagram showing an operation of a right vector shift instruction added in the embodiment.

FIG. 9 is a schematic diagram illustrating an operation of a bit inversion instruction added in the embodiment.

FIG. 10 is a diagram showing an example in which the instruction extension of the present embodiment is used.
9 is an assembler program list of a process of rotating a bit map of bits × 32 bits by 270 degrees.

FIG. 11 is a block diagram illustrating a configuration of a microprocessor according to the present embodiment.

FIG. 12 is a schematic diagram showing an operation of a carry extraction instruction added in the embodiment.

FIG. 13 is a schematic diagram showing an operation of a left vector shift instruction added in the embodiment.

[Explanation of symbols]

 101 Instruction Fetch Stage 102 Instruction Decode Stage 103 Integer Instruction Execution Unit 104 Memory Access Stage 105 Write Back Stage 106 Coprocessor Instruction Decode Stage 107 Variable Length Code Decode Unit (DECV) 108 Variable Length Code Decode Unit (DECS) 109 Coprocessor Memory Access Stage 110 coprocessor write back stage 201 instruction memory 202 register file 203 integer operation execution unit 204 data memory 205 shiftable register file 601 vector shift unit 602 carry extraction unit

Claims (15)

[Claims] 1. A microprocessor having an instruction for converting a variable length code at the head of variable length coded data arranged in a word length to a corresponding code length. 2. The microprocessor according to claim 1, further comprising an instruction for converting a leading variable-length code among variable-length coded data arranged in word length into a value corresponding thereto. Microprocessor. 3. A coprocessor attached to a microprocessor, comprising an instruction for converting a variable length coded data at the head of variable length coded data arranged in a word length into a code length corresponding thereto. Coprocessor. 4. The coprocessor according to claim 3, further comprising an instruction for converting a leading variable length code among variable length coded data arranged in word length into a value corresponding thereto. Processor. 5. A microprocessor provided with a coprocessor, comprising: an instruction fetch unit provided in the microprocessor for acquiring an instruction; and a coprocessor provided in the coprocessor for decoding an instruction from the instruction fetch unit. When the instruction decoding means determines that the instruction is not an integer instruction, the coprocessor instruction decoding means copes with the first variable length code of the variable length coded data arranged in the word length of the instruction provided in the coprocessor. First variable-length code decoding means for converting to a code length to be converted, and variable-length coding provided in the coprocessor and arranged to the word length of the instruction when the coprocessor instruction decoding means determines that the instruction is not an integer instruction. A second variable-length code for converting the first variable-length code of the data into a value corresponding thereto. And a decoding means. 6. An instruction fetch unit for acquiring an instruction, an instruction decode unit for decoding an instruction from the instruction fetch unit, and when the instruction decode unit determines that the instruction is not an integer instruction, the instruction is aligned with the word length of the instruction. First variable-length code decoding means for converting the first variable-length code of the obtained variable-length encoded data into a corresponding code length, and when the instruction decoding means determines that the instruction is not an integer instruction, the word length of the instruction And a second variable-length code decoding means for converting a variable-length code at the head of the variable-length coded data sorted into a value corresponding thereto. 7. A microprocessor having a vector shift function and a function of obtaining carry data at the time of vector shift as a result. 8. The microprocessor according to claim 7, further comprising a bit inversion function. 9. The microprocessor of claim 7, wherein said microprocessor performs said vector function by having a shiftable register file. 10. The microprocessor according to claim 9, wherein a coprocessor is attached to the microprocessor, and the shiftable file is provided in the coprocessor. 11. The microprocessor according to claim 9, further comprising a bit inversion function. 12. A method for rotating a bitmap image, comprising:
In a microprocessor with a coprocessor, an instruction memory means for storing instructions, and a shiftable register file means for performing a vector shift when it is determined that the instruction from the instruction memory means is a vector shift instruction And a register file means for storing carry data generated as a result of the vector shift by the shiftable register file means into a word length collectively. 13. The microprocessor according to claim 12, wherein said shiftable register file means is provided in a coprocessor, and said register file means is provided in said microprocessor. 14. The microprocessor according to claim 12, further comprising bit inversion means for performing bit inversion of carry data stored in said register file means. 15. A microprocessor for rotating a bitmap image, comprising: an instruction memory means for storing an instruction; and a vector shift instruction when the instruction from the instruction memory means is determined to be a vector shift instruction. Vector shift unit means for performing, and when the instruction from the instruction memory means is determined to be a carry extraction instruction, carry extraction unit means for updating data to be carried out during vector shift to a destination register and performing carry extraction And updating means for updating a result of vector shift by the vector shift unit means to a destination register.