JP2001197502A - Decoder for coded image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoder for an image that is high-efficiently coded image that can correctly decode an image after transition in the transition from still display of an image in compliance with the MPEG 2 to a usual decoding operation. SOLUTION: A decoding means 1 that decodes a high-efficiently coded image is provided with a memory means 30 whose area is divided into areas 31-1, 31-3 that store a reference image used by decoding other image for the reference image and an area 32 that stores one non-reference image not used for the reference image, a write area control means 18 that selects a storage destination of a decoded image, and a rearrangement read means 19 that reads the image data stored in the memory means in the order of display different from the data in the order of decoding. In the decoder 3 that includes the decoding means 1 and sets one of the images stored in the memory means to a still display state upon the receipt of a still display instruction, only the reference image in the decoded images is stored in a reference image storage area upon the receipt of a still instruction while reading the non-reference image and the non-reference image is aborted without being stored in the memory means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coded image decoding means for decoding image data coded based on a high-efficiency coding method such as the MPEG2 standard, and a means for displaying the decoded data. The present invention relates to an installed encoded image decoding / display device.

[0002]

2. Description of the Related Art Image data transmission and recording techniques occupy a large part of human information activities. In recent years, as these techniques, high-efficiency coding techniques for digitizing image data and compressing and coding data by removing temporal and spatial redundancy have been used,
The cost required for transmission or recording is reduced. As one of such coding techniques, ISO
The MPEG2 system (ISO / IEC 31-2818-2) standardized by / SC29 / WG11 is known. MPEG2 is used as a high-efficiency encoding method for various digital satellite broadcasts, and as a large-capacity recording medium, DVD-
It has been adopted as an encoding system for recording image data on ROMMPEG2 or DVD-RAM, and is becoming the mainstream of high-efficiency encoding technology for digital image transmission and recording.

In image coding based on the MPEG2 system,
Image data is processed in image units called frames. Generally, image data is constituted by displaying a plurality of images continuously, and in MPEG, it is general that one still image is treated as one frame. There are three types of frames, an I frame (IntraFrame) coded by removing only the spatial redundancy in the frame without using other frames as reference images, and referring to a past frame in display order. A predicted value is derived, and using this, a P frame (Predictive Frame) encoded by removing spatial and temporal redundancy, and prediction is performed from the average by referring to a past frame and a future frame in display order. B-frames (Bidirectionally Predi) which are derived and used to remove spatial and temporal redundancy
activeFrame) exists. I frame and P
The frame is used as a reference image when decoding other P frames and B frames. The I frame and the P frame are collectively called an anchor frame.

When a B frame is encoded, both a reference image of a past frame and a reference image of a future frame must exist at the time of encoding the B frame. Frame and the future frame are encoded prior to the B frame, and are arranged in the encoded data sequence.

[0005] The decoding / display device for data encoded by the above method decodes the transmitted encoded image data in the order of encoding. At this time, the past and future frames used as reference images when encoding the B frame are also required as reference images for decoding the B frame, so the past and future reference images are used before the B frame. Is decrypted. That is, decoding is performed in the order of a past frame, a future frame, and a B frame therebetween. However, after decoding, these frames need to be displayed in the order of a past frame, a B frame, and a future frame. Therefore, it is necessary to rearrange the frames after decoding, and for this purpose, the decoding / display device temporarily stores the decoded image in the memory.

As described above, the decoded image data of the anchor frame must be used as a reference image for decoding the B frame existing between the two frames in the display order. Therefore, until the decoding of the corresponding B frame is completed,
It is necessary to hold the image data of the anchor frame for two frames in the memory. Furthermore, since image data is encoded in units of one frame, if one frame is composed of two interlaced fields as in a current television signal, the image data of the decoded frame is Must be converted to field data. Therefore, it is necessary to temporarily store the decoded B frame in the memory.

[0007] These image storage memories are called frame memories.

[0008] In MPEG2, image data is subdivided into units called macroblocks, and encoding / decoding is performed for each macroblock. In the case of the 4: 2: 0 image format, a macroblock is composed of luminance data of 16 pixels (horizontal) × 16 pixels (vertical) and 8 × 8 color difference (two components of CB and Cr).

FIG. 15 shows the inter prediction coding for each macro block. FIG. 15A shows an encoded image 70C to be encoded, and FIG. 15B shows a reference image 70R used for encoding. For each macroblock, a luminance 16 × 16 pixel, a CB8 × 8 pixel, a Cr8 ×
The reference area 72 of 8 pixels is selected, and the relative vector in the screen of the macroblock 71 and the reference area 72 of the encoded image 70C and the prediction error thereof are encoded. This relative vector is called a motion vector 73. At the time of decoding, a 16 × 1
Reads 6 pixel (8 × 8 pixel in case of color difference) data,
This is added to the prediction error to decode the macroblock 71. Decoding a macroblock from the motion vector 73 and the prediction error is called motion compensation.

[0010] In addition, MPEG2 motion prediction is performed in half-pixel units. For this reason, when performing motion compensation with half-pixel accuracy, 17 × 17 pixels (9 in the case of color difference) are used as reference data.
The data of (× 9 pixels) is read out, and the average value between the pixels is calculated to obtain reference data of 16 × 16 pixels (or 8 × 8 pixels).

FIG. 16 shows the structure of MPEG2 encoded image data. The encoded image data is hierarchized,
The sequence layer 80, the group of picture (GOP) layer 81, the picture layer 82, the slice layer 83,
It is divided into a macro block layer 84 and a block layer 85. The sequence layer 80 includes a sequence header 80h and one or more GOP layer data 81d. Similarly,
The GOP layer 81 includes a GOP header 81h and one or more picture layer data 82d, the picture layer 82 includes a picture header 82h and one or more slice layer data 83d, and the slice layer 83 includes a slice header 83h and one or more macroblocks. From the layer data 84d, the macroblock layer 84
Is composed of a macro block header 84h and four block layer data 85d, and the block layer 85 is composed of a macro block header 85h and four block layer data 86d.

FIG. 17 shows the structure of the header of each layer. Each header h is composed of a header start code h1 and a header body h2. The header start code h1 is assigned a unique value for each layer, and the decoder obtains the start code h1 to identify the layer of the subsequent encoded data.

FIG. 18 shows a general configuration of an apparatus for receiving / decoding and displaying an encoded image broadcast according to the MPEG2 system.
The receiving / decoding / displaying device 5 for coded image broadcasting is an MPEG
A decoder 10 having two decoding means, a frame memory means 30, an antenna 51, a tuner 52, a demultiplexer 53, a CPU 54, a ROM 55, and a RAM.
56 and a digital / analog converter (DAC) 57
And a display device 58. A decoder is formed by the decoder 10 frame memory means 30.

The decoder 10 has a variable length code decoder (VL).
D) 11, an inverse quantizer (IQ) 12, an inverse discrete cosine transformer (IDCT) 13, an adder 14, a motion compensation circuit (MC) 17, a write area control unit 18, a reordering read And a part 19.

The frame memory 30 has an anchor frame frame memory area 31 and a B frame memory area 32.

A tuner 52 restores a digital coded data sequence from a broadcast wave received by an antenna 51, and a demultiplexer 53 extracts coded image data of an arbitrary channel and inputs the coded image data to a decoder 10.

In the decoder 10, the input coded image data is first subjected to variable length decoding by a variable length code decoder (VLD) 11. After this is inversely quantized by an inverse quantizer (IQ) 12, an inverse discrete cosine transform (IDCT) 13 performs an inverse discrete cosine transform process to obtain a macroblock prediction error. At the same time, the frame memory 31-for the anchor frame (for the reference image) in the frame memory 30 connected to the outside.
A macroblock is decoded by reading a reference area of 16 × 16 pixels from 1 and 31-2 using a motion vector, and adding them by an adder 14. Of the obtained decoded images, the writing area control unit 1
8 is the first anchor frame memory 31-1.
Or the second anchor frame frame memory 31-
2, and the B frame is stored in the B frame frame memory 32. The rearrangement readout unit 19 reads out the stored images in the display order, and as a display image, uses a digital / analog converter (D / A converter, DA
C) The data is sent to 57 and subjected to D / A conversion processing, and
Output to Further, the motion compensator (MC) 17 reads the anchor frame as a reference image, and the adder 14 adds it to the prediction error of another frame. The operations of these components are controlled by the CPU 54.

A memory means 3 such as a frame memory
0 is generally connected to the outside of the decoder 10 as shown in FIG.

A general MPEG2-encoded image decoding apparatus has a still display function of repeatedly displaying one of the images. The still display function mainly plays the following roles.

The first is to display only one of the images. Second, when decoding of an image has failed, an image for which decoding has already been completed is repeatedly displayed so that an image for which decoding has failed is not displayed.

The configuration of a decoding / display device and an example of a display processing procedure for displaying only one image will be described with reference to FIG. This decoding / display device has the same configuration as the decoding / display device 3 shown in FIG.
Is omitted. When the CPU 54 issues a still command to the reordering / reading unit 19, the reordering / reading unit 19 stores the image designated by the CPU 54 in the first anchor frame memory 31-1, 31- regardless of the encoding order or the display order. 2. Repeatedly read from any of the B frame frame memories 32. As a result, an image pause function is realized.

In the case where decoding of an image has failed, the structure of the decoding / display apparatus and the display processing procedure in the case where the already decoded image is repeatedly displayed to prevent the image whose decoding has failed from being displayed are displayed. An example will be described with reference to FIG. This decoding / display device 3 is characterized in that an error detection unit 20 is added to the decoding / display device 3 shown in FIG. 18, and illustration of a CPU, a ROM, and a RAM is omitted. Variable length code decoder (VLD) 1 for decoding
1. If decoding failure occurs in the inverse quantizer (IQ) 12, the discrete cosine inverse transformer (IDCT) 31-2, the motion compensation circuit (MC) 17, etc., the error detection unit 20 detects it. , And sends a still command to the reordering / reading unit 19.
The reordering / reading unit 19 repeatedly reads the decoded image from any of the anchor frame frame memories 31-1 and 31-2 and the B frame frame memory 32 irrespective of the encoding order or the display order. As a result, only images that have been successfully decoded are displayed. afterwards,
When decoding of a new image is completed correctly, the error detection unit 20 cancels the still command, and the sorting and reading unit 19 reads the images in the display order.

During the above-described still display period, decoding of the encoded image is generally stopped in order to avoid overwriting a new decoded image on the storage area of the image being displayed in the still display. . During this time, the encoded image data input to the decoder 10 is discarded. For this reason, when shifting from the still display to the normal operation, the reference image necessary for decoding the encoded image is stored in the first anchor frame memory 31-1 and the second anchor frame memory 3.
1-2, the image after the transition to the normal operation cannot be correctly decoded.

A method of setting a larger number of frame memories in the frame memory 30 to prevent the decoding from being stopped even during the still period is conceivable. However, the capacity of the frame memory 30 increases and the cost of the entire system increases. Become.

[0025]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and correctly decodes an encoded image without increasing the capacity of the frame memory 30 even when shifting from a still display to a normal decoding operation. A decoding means is proposed.

[0026]

[MEANS FOR SOLVING THE PROBLEMS] The MPE proposed in the present invention
The G2 encoded image decoding means continues to decode the encoded image even during the still display period. The rearrangement reading unit 19 inputs information of the frame memory in which the still-displayed image is stored to the writing area control unit 18. When the frame memory in which the still-displayed image is stored is the B-frame frame memory, the writing area control unit 18 discards the decoded B-frame data without storing it in the B-frame frame memory, and Only the frame is stored in the anchor frame memory. Also,
If the frame memory in which the still-displayed image is stored is an anchor frame frame memory, the decoded B frame data is discarded without being stored in the B frame frame memory, and only the anchor frame is anchored. A frame memory that is different from the still-displayed frame memory of the frame memories;
It is stored in the frame memory for frames. As a result, it is possible to keep storing only the anchor frame in the frame memory without losing the image to be displayed as a still image, and to correctly decode the image after the transition from the still display to the normal decoding operation.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the block diagram of FIG. 1, a high-efficiency coded image decoding device 1, a decoding / display device 3, and a receiving / decoding / display device 5 according to a first embodiment of the present invention. Will be described. In this embodiment, the input is MP
The EG2 encoded image data and output are digital decoded images to be sent to the D / A converter. The frame memory required for the decoding process is connected outside the decoder.

In this embodiment, during the still display period of the B frame, the anchor frame of the decoded image is stored in the anchor frame frame memory, and the data of the B frame is discarded without being stored in the frame memory. Features.

The receiving / decoding / display device 5 according to the present invention
Comprises a decoding / display device 3, a tuner 52, and a demultiplexer 53. The decoding / display device 3 includes a decoding device 1 for a high-efficiency coded image, a CPU 54, a ROM
55, a RAM 56, a DAC 57, and a display device 58. The high-efficiency encoded image decoding device 1 includes a high-efficiency encoded image decoder 10 and a frame memory 30.

The decoder 10 includes a header analysis / variable length code decoder (VLD) 11, an inverse quantizer (IQ) 12, an inverse discrete cosine transformer (IDCT) 13, and an adder 14.
, A data bus 15, a memory I / F 16, a motion compensation circuit (MC) 17, a write area control unit 18, and a rearrangement read unit 19. The decoder 10 has a CP
Controlled by U54.

The frame memory 30 includes a first anchor frame memory 31-1 configured as a memory area for storing an anchor frame, and a second anchor frame frame configured as a memory area for storing an anchor frame. It has a memory 31-2, a B frame frame memory 32 configured as a memory area for storing B frames, and an ES buffer 33 configured as an area for storing encoded image data.

Hereinafter, the configuration of the decoding device for a high-efficiency coded image will be described in detail with reference to FIG.

In FIG. 1, the coded image data from the demultiplexer 53 is input to the decoder 10. The encoded image data is transferred to the frame memory 30 via the data bus 7 and the memory I / F 8 and stored in the ES buffer 21. The coded image data stored in the ES buffer 21 is read out again by the memory I / F 8 and analyzed via the data bus 7 to analyze the header and decode the variable length code. The header analysis / variable length code decoder (VLD) 11 Is forwarded to

Header analysis / variable length code decoder (VLD)
Reference numeral 11 denotes variable-length decoding of the encoded image data, and inputs the image data composed of the discrete cosine transform coefficients obtained by the decoding to an inverse quantizer (IQ) 12. Also, the quantization coefficient of the macroblock to be decoded from each header of the encoded image data, the prediction mode signal, the motion vector, and the frame type (I
Or P or B), and an inverse quantizer (IQ) 1
2, writing area control unit 18, motion compensation circuit (MC) 1
7 is input as side information.

In the inverse quantizer (IQ) 12, the input discrete cosine transform coefficient image data is inversely quantized based on the quantized coefficient, and the inverse cosine transform (IDC) is performed.
T) 13.

In the discrete cosine inverse transformer (IDCT) 13, the image data is subjected to an inverse cosine transform process, whereby image data before motion compensation (prediction error) is obtained.
The prediction error is calculated by a motion compensation circuit (MC) 17 by a process described later.
Is added by the adder 14 to the reference data generated by
Decoded image data is obtained.

Based on the frame type, the still signal, and / or the display frame information, the writing area control unit 18 stores the frame memory for storing the decoded image in the first anchor frame frame memory 31-1 and the second anchor frame One of the frame memory 31-2 and the B frame frame memory 32 is selected, and the signal of the selected frame memory is input to the memory I / F 8.

The decoded image obtained by the adder 14 is stored in the frame memory selected by the writing area control unit 18 through the data bus 7 and the memory I / F 8.

The reordering / reading unit 19 stores the decoded images stored in the first anchor frame memory 31-1, the second anchor frame memory 31-2, and the B frame memory 32 in the memory. I
/ F8, read out in the display order via the data bus 7, and output to the D / A converter (DAC) 57 as the output of the decoder. In addition, during the still display period, the rearrangement reading unit 19 writes a signal indicating that still display is being performed (still signal) and a signal indicating a frame in which still display is being performed (display frame memory signal) to write area control. Input to the unit 18.

The reference data supplied to the adder 14 is generated by the motion compensation circuit (MC) 17 as follows.

In MPEG2, image data is subdivided into units called macroblocks (MB).
Encoding / decoding is performed every time. In the case of the 4: 2: 0 image format, the MB is composed of luminance data of 16 pixels (horizontal) × 16 pixels (vertical) and 8 × 8 color difference (two components of CB and Cr).

The image data before motion compensation obtained by the inverse discrete cosine transform (IDCT) 13 has a maximum of four motion vectors as side information. This motion vector is sent to a motion compensation circuit (MC) 17, which includes a first anchor frame memory 31-1, a second anchor frame memory 31-2, and a B frame Of the images stored in the frame memory 32, the luminance component 16 × 16, the CB component 8 × 8, and the Cr component 8 × 8 at the position corresponding to the motion vector in the image corresponding to the reference image of the image currently being decoded. Read the reference data. Thereby, the motion compensation circuit (MC)
Reference numeral 17 denotes a maximum of four MB reference image data (the luminance component 1
6 × 16, CB component 8 × 8, Cr component 8 × 8) are obtained from the frame memory 30. The average of these MB reference image data is taken, and the obtained reference image (luminance component 16 × 16,
The CB component 8 × 8 and the Cr component 8 × 8) are input to the adder 14.

Here, the B frame frame memory 32
At some point during the display of the B frame image in the
, A still command is input to the reordering and reading unit 19. At this time, the rearrangement reading unit 19 repeatedly reads the image in the B-frame frame memory 32 displayed at that time, and performs still display. at the same time,
The still signal is set to “1” to notify the writing area control unit 18 that the still display period is in progress. Further, it outputs a display frame memory signal and notifies the writing area control unit 18 of information that the B frame frame memory 32 is repeatedly displayed for still display.

FIG. 2 shows the correspondence between the frame memory for still display and the value of the display frame memory signal output from the rearrangement readout unit 19. The display frame memory signal takes a value “2” when the image of the B frame frame memory 32 is displayed as a still image.

FIG. 3 shows the relationship between the frame type input to the writing area control unit 18, the still signal and the display frame memory signal, and the frame memory selection signal to be output. When the still signal is “0”, the writing area control unit 18 alternately switches between the first anchor frame memory 31-1 and the second anchor frame memory 31-2 when storing the anchor frame. When selecting and storing the B frame, the B frame frame memory 32 is selected. When the still signal is “1” and the display frame memory signal is “2”, the writing area control unit 18 stores the first anchor frame memory 31-1 and the second anchor frame when storing the anchor frame. The frame memory 31-2 is alternately selected, but in the case of the B frame, the storage frame memory is not selected. As a result, the data of the B frame is discarded without being stored in the frame memory.

As a result, the anchor frame is correctly decoded even during the still display period of the B frame, so that the image after the transition from the still display to the normal operation can be correctly decoded.

FIG. 4 shows the correspondence between the frame memory for still display and the value of the display frame memory signal output from the rearrangement readout unit 19 in the second embodiment of the high efficiency encoded image decoding apparatus according to the present invention. FIG. FIG. 5 shows a frame type still image signal and a display frame memory signal to be input to the writing area control unit 18 and a frame memory selection to be output in the second embodiment of the high efficiency encoded image decoding apparatus according to the present invention. FIG. 3 is a diagram illustrating a relationship between signals.

In this embodiment, during the still display period of the anchor frame, the anchor frame of the decoded image is stored in the first anchor frame memory 31-1.
And the second anchor frame frame memory 31-2 is stored in the frame memory different from the one displaying the still image and the B frame frame memory 32, and the B frame data is not stored in the frame memory. It is characterized by being discarded.

Also, in the present embodiment, the configuration of the decoder 10 is such that the rearrangement read unit 19 and the write area control unit 18
Except for this, it is assumed that the second embodiment is the same as the first embodiment.

As shown in FIG. 4, the rearrangement readout unit 1
9 is a first anchor frame memory 31-
In the case of still display of 1, "0" is written as a display frame memory signal. In the case of still display of the second anchor frame memory 31-2, "1" is written as a display frame memory signal. Input to the control unit 18.

As shown in FIG. 5, the write area control unit 1
8 alternately selects the first anchor frame memory 31-1 and the second anchor frame memory 31-2 when the anchor signal is stored when the still signal is "0", and stores the B frame. Is stored, the B frame frame memory 32 is selected.

When the anchor signal is stored when the still signal is "1" and the display frame memory signal is "0", it is different from the still display frame memory 31-1 for the first anchor frame. Frame memory for anchor frame, that is, frame memory for second anchor frame 31-2 and frame memory for B frame 32
Are alternately selected, but in the case of the B frame, the storage frame memory is not stored. Thereby, the anchor frame is stored in the second frame memory for anchor frame 31-2 and the frame memory for B frame 32, and the data of the B frame is discarded without being stored in the frame memory.

When the still signal is "1" and the display frame memory signal is "1", to store the anchor frame, the frame memory for the anchor frame in the still display is stored in the second frame memory 31 for the anchor frame.
The frame memory 31-1 for the first anchor frame and the frame memory 32 for the B frame, which are different from -2, are alternately selected. Thus, the anchor frame is stored in the first anchor frame memory 31-1 and the B frame memory 32, and the data of the B frame is discarded without being stored in the frame memory.

Thus, the anchor frame is correctly decoded even during the still display period of the anchor frame.
The image after the transition from the still display to the normal operation can also be correctly decoded.

With reference to FIG. 6, the configuration of the writing area control section 18 in the third embodiment of the high efficiency encoded image decoding apparatus according to the present invention will be described. Write area control unit 1
Reference numeral 8 includes a writing area selection unit 181 and a register 182 for holding information of a still-displayed frame memory. FIG. 7 shows the correspondence between the frame memory for still display and the value of the display frame memory signal output by the rearrangement readout unit 19 in the third embodiment of the high-efficiency encoded image decoding apparatus according to the present invention. FIG.

In the present embodiment, when the anchor frame is decoded according to the first or second embodiment even during the still display, after the display is shifted from the still display to the normal display, the B frame is stored in the frame memory for the still display. Is stored.

Further, in the present embodiment, the configuration of the decoder 10 is such that the rearrangement readout unit 19 and the write area control unit 18
Except for the above, it is the same as the first or second embodiment.

As shown in FIG. 7, the rearrangement readout unit 1
Reference numeral 9 denotes "0" as a display frame memory signal when the first frame memory 31-1 for the first anchor frame is displayed as a still image, and when the frame memory 31-2 for the second anchor frame is displayed as a still image. In the case where “1” is displayed as the display frame memory signal and “2” is displayed as the display frame memory signal in the case where the B frame frame memory 32 is displayed in the still mode, the write area control unit 18 is input.

The register 182 of the write area control unit 18 shown in FIG.
9 holds the value of the display frame memory signal that is input from. The held value is input to the writing area selection unit 181 when the display shifts from the still display to the normal display.

FIG. 8 shows the relationship between the frame type, the still signal, the display frame memory signal and the value of the register 182 input to the write area selector 181 and the frame memory selection signal to be output.

When the still signal is "0" and the value of the register 102 is "0", it indicates that the frame memory which was still displayed immediately before was the first anchor frame memory 31-1. At this time, the writing area selection unit 18 sets the second anchor frame memory 31-2 and B as the area for storing the anchor frame.
The frame memories 32 for frames are alternately selected, and the first frame memory 31-1 for anchor frames is selected as an area for storing B frames. Similarly, when the still signal is “0” and the value of the register 182 is “1”, the first anchor frame frame memory 31-1 and the B frame frame memory 32 are alternately selected as an area for storing an anchor frame. The second anchor frame frame memory 31 is used as an area for storing the B frame.
-2, when the still signal is "0" and the value of the register 182 is "2", the first anchor frame memory 3 is used as an area for storing the anchor frame.
1-1 and second anchor frame frame memory 31
-2 are alternately selected, and the B frame frame memory 32 is selected as an area for storing the B frame.

When the still signal is “1” and the display frame memory signal is “0”, the write area selection unit 181
Stores the anchor frames alternately in the second anchor frame memory 31-2 and the B frame memory 32, and discards the B frames without storing them. Similarly, when the still signal is “1” and the display frame memory signal is “1”, the writing area selecting unit 181 stores the anchor frame in the first anchor frame memory 31.
-1 and the B frame are alternately stored in the frame memory 32, and the B frame is discarded without being stored.
When the display frame memory signal is "2", the writing area selection unit 181 stores the anchor frames alternately in the first anchor frame memory 31-1 and the second anchor frame memory 31-2. B frames are discarded without being stored. This operation is the same as in the first or second embodiment.

Thus, when the anchor frame is correctly decoded during the still display period according to the first or second embodiment, the image after the transition from the still display to the normal operation can also be correctly decoded.

With reference to FIG. 9, the configurations of the decoding device 1, decoding / display device 3, and receiving / decoding / display device 5 of the high-efficiency coded image according to the fourth embodiment of the present invention will be described. In this embodiment, the input is MPEG2-encoded image data, and the output is a digital decoded image to be sent to a D / A converter. The memory required for the decoding process is connected outside the decoder.

In the present embodiment, during the still display period of the B frame, the encoded data of the B frame among the input encoded image data is discarded, and only the anchor frame is decoded and stored in the anchor frame memory. Features.

In the present embodiment, the rearranging and reading section 19
Is output to the header analysis / variable length code decoder (VLD) 11 and the configuration of the header analysis / variable length code decoder (VLD) 11 is changed. In other respects, the configuration is almost the same as that of the apparatus shown in FIG.

FIG. 10 shows the header analysis and
1 shows a configuration of a variable length code decoder (VLD) 11. The header analysis / variable length code decoder (VLD) 11 includes a header start code detection unit 111, a header analysis unit 112,
It has a variable length decoding unit 113.

The start code detecting section 111 detects the start code of the header in the encoded data, and identifies which layer of the MPEG2 encoded image the subsequent header and the encoded data are. The header analysis unit 112 receives the layer information of the data from the start code detector 111, and analyzes the header following the start code based on the layer information. The variable length decoding unit 113 receives layer information from the start code detection unit 111 and header information such as a frame type from the header analysis unit 112, and performs variable length decoding on encoded data following the header.

Here, the B frame frame memory 32
At some point during the display of the B frame image in the
, A still command is input to the reordering and reading unit 19. At this time, the rearrangement reading unit 19 repeatedly reads the image in the B-frame frame memory 32 displayed at that time, and performs still display. at the same time,
The still signal is set to “1”, and the variable length decoding unit 113 and the writing area control unit 18 are notified that the still display period is being performed. Further, it outputs a display frame memory signal and notifies the writing area control unit 18 of information that the B frame frame memory 32 is repeatedly displayed for still display.

The correspondence between the frame memory for still display and the value of the display frame memory signal output from the rearrangement readout unit 19 is shown in FIG. 2, as in the first embodiment.
The display frame memory signal takes a value “2” when the image of the B frame frame memory 32 is displayed as a still image.

FIG. 11 is a state transition diagram that defines the operation of the variable length decoding unit 113. Arrows in the figure indicate transition conditions in each state, and ellipses indicate operations of the variable length decoding unit 113 in each state.

First, the detection of the sequence header start code is notified from the start code detection unit 111, and the sequence layer is decoded. Next, the detection of the GOP header start code is notified, and the GOP layer is decoded.

Thereafter, when the detection of the picture header start code is notified, the variable length decoding section 113 checks the still signal input from the rearrangement reading section 19. When the still signal is “0”, the variable length decoding unit 113 performs decoding of the picture layer and lower as usual. Thereafter, when a sequence, GOP, and picture header detection notification is received, the process proceeds to decoding of the next sequence layer, GOP layer, and picture layer.

If the still signal is “1” when the picture header start code is detected, the header analysis unit 11
Check the frame type input from 2. Frame type is anchor frame (I or P frame)
If the frame type is a B frame, the start code detection unit 111
Until the detection of the detection of any of the start codes of the sequence header, the GOP header, and the picture header,
Discard the encoded image data without performing variable length decoding. As a result, during still display, only the variable-length decoded data of the anchor frame is sent to the inverse quantizer (IQ) 12, and the encoded data of the B frame is discarded.

FIG. 12 shows the relationship between the frame type, still signal, and display frame memory signal input to the writing area control unit 18 and the frame memory selection signal to be output. When the still signal is "0", the writing area control unit 18 stores the anchor frame in the first anchor frame memory 31-1.
And the second anchor frame memory 31-2 are alternately selected, and when storing the B frame, the B frame frame memory 32 is selected. When the still signal is “1” and the display frame memory signal is “2”, the writing area control unit 18 uses the decoded anchor frame as a storage area and the first anchor frame memory 31-1 and the second anchor frame. The frame memories 31-2 for frames are alternately selected. Since the B frame is discarded by the variable length decoding unit 113 without being decoded,
In No. 2, an area for storing a B frame during still display is not defined.

Thus, the anchor frame is correctly decoded even during the still display period of the B frame, so that the image after the transition from the still display to the normal operation can also be correctly decoded. Further, the header analysis / variable length code decoder 111
At some point when the still signal is displaying the B frame image, C
When a still instruction is input from the PU 54 to the rearrangement reading unit 19, the still signal is set to “1” and the variable length decoding unit 11
3, the decoding of the B frame is not performed, so that the inverse quantizer (IQ) 1
2. There is no need to perform the decoding process by the discrete cosine inverse transformer (IDTC) 13, and the burden on the CPU 54 can be reduced.

FIG. 13 shows a frame type and a still signal and a display frame memory signal input to the writing area control unit 18 and a frame to be output in the fifth embodiment of the high efficiency encoded image decoding apparatus according to the present invention. FIG. 5 is a diagram showing a relationship between memory selection signals.

In this embodiment, during the still display period of the anchor frame, the anchor frame of the decoded image is stored in the frame memory for the anchor frame, which is different from the still display frame memory, and the B frame. It is stored in the frame memory, and the data of the B frame is discarded without being stored in the frame memory.

In the present embodiment, the correspondence between the frame memory for still display and the value of the display frame memory signal output from the rearrangement readout unit 19 is shown in FIG. 4, as in the second embodiment.

In the present embodiment, the configuration of the decoder 10 is such that the rearrangement read unit 19 and the write area control unit 18
Except for this, it is assumed that the fourth embodiment is the same as the fourth embodiment.

As shown in FIG. 4, the rearrangement readout unit 1
9 is a first anchor frame memory 31-
To display 1 as a still image, input “0” as a display frame memory signal, and to display the second anchor frame frame memory 31-2 as a still image, input “1” as a display frame memory signal to the writing area control unit 18. I do.

As shown in FIG. 13, when the still signal is "0", the writing area control section 18 stores the first anchor frame memory 31-1 and the second anchor frame when storing the anchor frame. The frame memory 31-2 is alternately selected, and when storing the B frame, the frame memory 32 for the B frame is selected.

When the still signal is “1” and the display frame memory signal is “0”, the decoded anchor frame is
A second anchor frame memory 31-2 and a B frame memory 3 different from the first anchor frame memory 31-1 that are still displayed.
2 are stored alternately. When the still signal is “1” and the display frame memory signal is “1”, the decoded anchor frame is stored in the first anchor frame for the first anchor frame, which is different from the still-displayed second anchor frame memory 31-2. The frame memory 31-1 and the B frame frame memory 32 are stored alternately. In either case, since the B frame is discarded by the variable length decoding unit 113 without being decoded, an area for storing the B frame during the still display is not defined in FIG.

Thus, the anchor frame is correctly decoded even during the still display period of the anchor frame.
The image after the transition from the still display to the normal operation can also be correctly decoded.

In the sixth embodiment of the present invention,
The configuration of the decoder 10 is shown in FIG. 9 as in the fourth embodiment. The configuration of the write area control unit 18 is assumed to be as shown in FIG. 6, as in the third embodiment.

In the present embodiment, when the anchor frame is decoded by the third or fourth embodiment even during the still display, the still display is shifted to the normal display, and then the B frame is stored in the still displayed frame memory. Is stored.

In this embodiment, it is assumed that the configuration is the same as that of the fourth or fifth embodiment except for the configuration of the rearrangement readout unit 19 and the write area control unit 18.

In the present embodiment, the correspondence between the frame memory for still display and the value of the display frame memory signal output by the rearranging and reading section 19 is represented in FIG. 7, as in the third embodiment.

As shown in FIG. 7, the rearrangement readout unit 1
9 is a first anchor frame memory 31-
When still display 1 is "0" as the display frame memory signal, when displaying still the second anchor frame frame memory 31-2, "1" as the display frame memory signal, and B frame frame memory 32 Is displayed as a still image, "2" is input to the writing area control unit 18 as a display frame memory signal.

FIG. 14 shows the relationship between the frame type, still signal, display frame memory signal and the value of the register 182 input to the writing area selector 181 and the frame memory selection signal to be output. When the still signal is "0" and the value of the register 182 is "0", it indicates that the frame memory which was still displayed immediately before was the first anchor frame memory 31-1. At this time, the writing area selection unit 181 alternately selects the second anchor frame memory 31-2 and the B frame memory 32 as areas for storing the anchor frame, and sets the first frame memory as the area for storing the B frame. Is selected for the anchor frame memory 31-1.

Similarly, when the still signal is "0" and the register 1
When the value of 82 is “1”, the first anchor frame frame memory 31-1 and the B frame frame memory 32 are alternately selected as the area for storing the anchor frame, and the second frame is stored as the area for storing the B frame. 2 is selected, and when the still signal is “0” and the value of the register 182 is “2”, the first anchor frame memory 31-2 is used as an area for storing the anchor frame. The first and second frame memories for anchor frame 31-2 are alternately selected, and the frame memory for B frame 32 is selected as an area for storing the B frame.

When the still signal is “1” and the display frame memory signal is “0”, the write area selection unit 181
Stores the anchor frames in the second frame memory for anchor frames 31-2 and the frame memory for B frames 32 alternately. Similarly, when the still signal is “1” and the display frame memory signal is “1”, the writing area selecting unit 181 stores the anchor frame in the first anchor frame memory 31-1 and the B frame memory 32. When the still signal is “1” and the display frame memory signal is “2”, the write area selection unit 18
1 alternately stores the anchor frames in the first anchor frame memory 31-1 and the second anchor frame memory 31-2.

In each case, since the B frame is not decoded and is discarded by the variable length decoding unit 113, an area for storing the B frame during the still display is not defined in FIG. This operation is the same as in the fourth or fifth embodiment.

Thus, when the anchor frame is correctly decoded during the still display period according to the fourth or fifth embodiment, the image after the transition from the still display to the normal operation can also be correctly decoded.

In each of the above embodiments, the external CPU 54
Although the still display is performed by the instruction from the above, the present invention is effective even when the still display is performed by detecting the decoding failure internally.

In addition, the present invention is also effective when receiving, decoding, and displaying the protected content proposed in the MPEG-4 standard. Normal moving image display, frame dropping display (for example, skipping of B frame) for an encoded stream having a viewing right for a limited time
In the case where it is required to switch temporally between still display and still display, it is possible to correctly shift to normal moving image display by continuing to decode only I frames and P frames even during still display.

[0097]

According to the present invention, the following effects can be obtained.

By continuing to decode only the I frame and the P frame during the still display, it is possible to correctly decode the image after the transition from the still to the normal operation without increasing the capacity of the frame memory 30.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a table showing values of a display frame memory signal during still display according to the first embodiment of the present invention.

FIG. 3 is a table showing write area control during still display according to the first embodiment of the present invention.

FIG. 4 is a table showing values of a display frame memory signal during still display according to the second embodiment of the present invention.

FIG. 5 is a table showing write area control during still display according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a writing area control unit 18 according to a third embodiment of the present invention.

FIG. 7 is a table showing values of a display frame memory signal during still display according to the third embodiment of the present invention.

FIG. 8 is a chart showing write area control during normal operation and still display according to the second embodiment of the invention.

FIG. 9 is a block diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a header analysis / variable length code decoder (VLD) 11 according to a fourth embodiment of the present invention.

FIG. 11 is a state transition diagram showing an operation of a variable length decoding unit 303 according to a fourth embodiment of the present invention.

FIG. 12 is a chart showing write area control during still display according to the fourth embodiment of the present invention.

FIG. 13 is a chart showing write area control during still display in the fifth embodiment of the present invention.

FIG. 14 is a chart showing write area control during still display according to the sixth embodiment of the present invention.

FIG. 15 is a diagram showing an outline of motion prediction in MPEG2.

FIG. 16 is a diagram showing a data structure of an MPEG2-encoded image.

FIG. 17 is a diagram showing the structure of each header in MPEG2-encoded image data.

FIG. 18 is a block diagram showing a configuration of a general device for decoding and displaying an MPEG2-encoded image.

FIG. 19 is a block diagram showing a case where a still display is commanded from the outside in the MPEG2 decoding / display apparatus.

FIG. 20 is a block diagram showing a case in which a decoding failure is detected and still display is performed in the MPEG2 decoding / display apparatus.

[Explanation of symbols]

 Reference Signs List 1 decoding device 3 decoding / display device 5 receiving / decoding / display device 10 decoder 11 header analysis / variable-length code decoder (VLD) 12 inverse quantizer (IQ) 13 discrete cosine inverse transformer (IDCT) 14 adder Reference Signs List 15 data bus 16 memory I / F 17 motion compensation circuit (MC) 18 write area control unit 19 rearrangement read unit 20 error detection unit 30 frame memory 31 frame memory for anchor frame 32 frame memory for B frame 33 ES buffer 51 antenna 52 Tuner 53 Demultiplexer 54 CPU 55 ROM 56 RAM 57 D / A converter 58 Display device 111 Start code detection unit 112 Header analysis unit 113 Variable length decoding unit 181 Writing area selection unit 182 Register

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK08 MA00 MA05 MA14 MA23 MC11 MC38 ME01 PP01 PP05 PP06 PP07 RF01 RF09 SS16 UA05 UA34 UA36 UA38

Claims (7)

[Claims] A memory means divided into a reference image storage area for storing two images used as reference images when decoding another image and a non-reference image storage area for storing one image not used as a reference image A high-efficiency coded image decoding device that decodes high-efficiency coded image data and outputs the decoded image to an image display device, wherein when storing the decoded image data in the memory unit, the decoded image is read. When the still command is received, only the image used as the reference image among the decoded images is stored in the reference image storage area in the memory unit, and the reference image decoded after receiving the still command is received. A high-efficiency coded image decoding apparatus for discarding an image that is not used as an image without storing it in the memory unit. 2. An image display apparatus comprising: a variable-length decoding unit; an image data inverse conversion unit; a motion compensation unit; and a reference image data position shift unit. Means for outputting a decoded image, a memory means for storing decoded image data, a writing area control means for selecting in which area of the memory means the decoded image is to be stored, and an image stored in the memory means. A rearrangement reading unit that reads data from the memory unit in a display order different from a decoding order, wherein the memory unit stores two images to be used as reference images when decoding another image; The writing area control unit has a function of independently storing a plurality of images in the memory unit; The decoding device having a function of still-displaying one of the images stored in the memory device in response to a still-display command from inside or outside of the device. When a still command is received during reading of an image not used as a reference image at the time of decoding of the image, the rearrangement reading unit writes the information of an area in the memory unit in which the image to be displayed as a still image is stored. An input to the area control unit, the writing area control unit stores only the image used as the reference image among the decoded images in the area for storing the reference image in the memory unit, and stores the image not used as the reference image in the area. A high-efficiency encoded image decoding apparatus characterized by discarding without storing in a memory means. 3. The high-efficiency coded image decoding / display device according to claim 2, further comprising: the rearranging and reading unit that reads out an image used as a reference image when decoding another image. Upon receiving the command, the rearrangement and reading unit inputs information of an area where an image to be displayed as a still image is stored in the memory unit to the writing area control unit, and the writing area control unit Only the image used as the reference image among the images is not used as the reference image and the other of the two reference image storage regions in the memory unit that is different from the region input from the rearrangement reading unit. A high-efficiency coded image decoding apparatus, wherein an image stored in an image storage area is discarded without storing an image not used as a reference image in the memory unit. 4. The high-efficiency coded image decoding apparatus according to claim 2, wherein said writing area control means displays an image used as a reference image when decoding another image in a still image. During the operation, the information of the area in which the still-displayed reference image is stored, which is input from the rearrangement reading unit, is held. After the still-display instruction is released, the information is held. A high-efficiency coded image decoding apparatus, wherein an image not used as a reference image is stored in an area that has been used as a reference image, and an image used as a reference image is stored in two other image storage areas. 5. An image display apparatus comprising a variable length decoding unit, an image data inverse conversion unit, a motion compensation unit, and a reference image data position shift unit. Means for outputting a decoded image, a memory means for storing decoded image data, a writing area control means for selecting in which area of the memory means the decoded image is to be stored, and an image stored in the memory means. And rearranging and reading means for reading data from the memory means in a display order different from the decoding order. The variable-length decoding means, based on a result of variable-length decoding of the encoded image data, Has a function of detecting encoded data of an image that is not used as a reference image when decoding an image, and the memory unit stores an image used as a reference image when decoding another image. It is divided into an area for storing two images and an area for storing one image not used as a reference image, and has a function of storing a plurality of images in the memory means independently by the writing area control unit. The rearranging and reading means is configured to output one of the images stored in the memory means in response to a still display command from inside or outside the apparatus.
A decoding device having a function of displaying still images, wherein the rearrangement reading unit receives a still command while reading an image not used as a reference image when decoding another image, Among the input variable-length coded image data, coded data of an image not used as a reference image when decoding another image is discarded without being sent to the image data inverse conversion unit, and the other image data is discarded. Only the coded data of the image used as the reference image at the time of decoding is sent to the image data inverse conversion means, and the rearrangement reading means writes the information of the area where the still display image is stored in the memory means. An input to an area control unit, wherein the writing area control unit stores an image used as a decoded reference image in an area for storing a reference image in the memory unit. Decoding apparatus of high efficiency coded image. 6. The high-efficiency coded image decoding device according to claim 5, further comprising: the rearrangement and reading unit performs still image reading while reading an image to be used as a reference image when decoding another image. Upon receiving the instruction, the variable-length decoding unit converts the encoded data of the input variable-length encoded image data, which is not used as a reference image when decoding another image, into the image data inverse conversion. The image data is discarded without being sent to the means, and only the encoded data of the image used as the reference image when decoding another image is sent to the image data inverse transforming means. The information of the area in which the image to be stored is stored is input to the writing area control unit, and the writing area control unit converts the decoded reference image into two of the reference image storing areas in the memory unit. Decoding apparatus of high efficiency coded image, wherein the region different from the region input from the serial sorting reading means, to be stored in the storage area for the image that is not used as a reference picture. 7. The high-efficiency coded image decoding device according to claim 5, wherein the writing area control unit further includes an image used as a reference image when decoding another image. During the still display, the information of the area in which the still-displayed reference image is stored, which is input from the rearrangement reading means, is held. After the still display command is released, the information is stored. A high-efficiency coded image decoding apparatus, wherein an image not used as a reference image is stored in a retained area, and an image used as a reference image is stored in two other image storage areas.