JP2001196902A - Chopper type comparator and analog/digital converter using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an analog/digital converter using a chopper type comparator where deterioration in the precision of an amplification operation can surely be prevented. SOLUTION: The configuration of a latch circuit 3 that is inserted to a post-stage of a comparator 1 is which a clocked inverter 2 is incorporated, for the purpose of timing adjustment and of an amplification operation adopts a circuit configuration following the configuration of the clocked inverter 2 in the inside of the comparator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a chopper type comparator used for a to Digital (hereinafter, abbreviated as A / D) comparator.

[0002]

2. Description of the Related Art An A / D converter for converting an analog signal into a digital signal is an indispensable electronic device in the fields of consumer electronic devices such as measurement, control, communication, and video. Chopper type comparators are often used in high-speed A / D converters having a conversion frequency of several tens of MH or more.

An example of the circuit operation of a parallel A / D converter, which is a typical example of a high-speed A / D converter, will be described. In the case of N bits, (2 ^N -1) comparators are arranged, the reference voltage Vr that matches the input voltage is divided by 2 ^N equal resistors, and each voltage is applied to the comparator as a comparison voltage. The analog input voltage is commonly applied to all comparators, and the comparator compares the comparison voltage with the input voltage to find a comparison voltage closest to the input voltage. More specifically, the comparator compares the comparison voltage with the input voltage,
For example, if the input voltage is higher than the comparison voltage, "1" is output, and if the input voltage is opposite, "0" is output, so that a digital output can be obtained by the encoder circuit. Thus, the comparator is an important key device when configuring the A / D converter.

First, the operation of a conventional chopper type comparator will be described with reference to FIGS. Vi is the analog input voltage, Vr is the reference voltage, Vo is the comparator output, S
1-4 are switches, C1 and C2 are capacitors, A1 and A2 are C
MOS inverter, CMOS inverter is PMO
It comprises an S transistor M1 and an NMOS transistor M2.

When the switches S3 and S4 shown in FIG.
The input and output of the MOS inverters A1 and A2 are short-circuited. On the other hand, the input / output characteristics of the CMOS inverter (Vin-
Vout) is as shown in FIG. 7, and when the input and the output are short-circuited, the bias is applied at a point X in the figure.
This point is the point having the highest gain, and is usually set to about half of the power supply voltage, but is set to Va here.

When the switch S1 is turned on in this state, the capacitor C1 is charged with (Vi-Va). Thereafter, even when the switches S1, S3, and S4 are turned off, the charge held in the capacitor C1 does not change according to the law of charge storage. The period from when these switches S1, S3, S4 are turned on until they are turned off is auto-zero (hereinafter referred to as AZ).
Called the period.

Next, when the switch S2 is turned on, the capacitance C
Since there is no route for charging / discharging the charge of No. 1, the potential change on the left side of the capacitor C1 becomes (Vi−Vr),
The signal is transmitted to the input terminal of the S inverter A1. Therefore,
If (Vi−Vr) is positive (> 0), the output of A1 decreases and is inverted at A2, so that the output Vo of the comparator becomes “High”. In the opposite case, Vo becomes “Low (GN).
D) ". A period from when the switch S2 is turned on until the comparator compares the analog input voltage with the reference voltage is referred to as a comparison (hereinafter, referred to as Comp) period.

Here, the problem of the conventional chopper type comparator will be described with reference to the same figure. The chopper type comparator is biased to a point where the gain of the CMOS inverter is the highest in the AZ period, but as shown in the input / output characteristics (Vin-Iout) of FIG.
Then, the current flowing through the CMOS inverter is the largest. Therefore, power consumption consumed by the comparator during the AZ period is a significant problem.

As a measure for solving such a problem, Japanese Patent Application Laid-Open No. 61-84110 and Japanese Patent Application Laid-Open No. 61-19661 are known.
No. 4, JP-A-8-46495,
It has been reported that a clocked inverter is provided inside a comparator to reduce current consumption.

Next, a problem of a conventional chopper type comparator using a clocked inverter will be described with reference to FIG. As shown in FIG. 8, the configuration of the latch circuit is such that two inverters have the other input as the other output. In this case, the clocked inverter and the inverter in the latch have different circuit configurations, and therefore have different input / output characteristics.

In FIG. 9A, since the input / output characteristics are the same, when the output of the comparator becomes the input of the latch, it is amplified at the point having the highest gain. However, if the input / output characteristics in the latch are different as shown in FIG. 9 (b), the amplification point shifts, so that a high amplification degree as shown in FIG. 9 (a) cannot be obtained and the comparison accuracy as a comparator decreases. Would.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an A / D converter using a chopper type comparator which can accurately prevent precision deterioration in an amplification operation.

[0013]

According to a first aspect of the present invention, there is provided a chopper type comparator having a clocked inverter, wherein a latch circuit for performing a timing adjustment and an amplifying operation is provided at a stage subsequent to the chopper type comparator. is there.

In the A / D converter according to the second invention,
In a chopper type comparator having a clocked inverter, a latch circuit that performs a timing adjustment and an amplification action at a stage subsequent to the chopper type comparator,
And an encoding circuit for receiving an output of the latch circuit.

In the A / D converter according to the third invention,
In a chopper type comparator having a clocked inverter, a latch circuit that performs a timing adjustment and an amplification action at a stage subsequent to the chopper type comparator,
It comprises a resistance element constituting the R interpolation and an encoding circuit for receiving an output of the latch circuit.

In the A / D converter according to the fourth invention,
In a chopper type comparator having a clocked inverter, a latch circuit that performs a timing adjustment and an amplification action at a stage subsequent to the chopper type comparator,
It comprises a capacitance element constituting C interpolation and an encoding circuit for receiving the output of the latch circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 First Embodiment A first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are circuit diagrams showing the configuration of the chopper type comparator according to the first embodiment. The features of the first embodiment are as follows.
The input / output characteristics of the inverters are made the same by eliminating the deterioration of precision in the amplification operation by adopting a circuit configuration following the clocked inverter inside the comparator for the configuration of the latch circuit inserted for the timing adjustment and amplification operation after the comparator. High accuracy.

In the figure, 1 is a chopper type comparator, 2 is a clocked inverter, C1 and C2 are capacitors, 3
Is a latch circuit, M1 and M3 are PMOS transistors, M
2, M3 are NMOS transistors, Vi is an analog input voltage, Vr is a reference voltage, Do is a latch circuit output, G1,
G2 is a transmission gate for performing switching control of the analog input voltage Vi and the reference voltage Vr, and φAZ is a control signal therefor.

In the chopper type comparator shown in FIG. 1, a latch circuit 3 inserted in the subsequent stage for timing adjustment and amplifying action has the following circuit configuration following the clocked inverter 3 inside the comparator 1. ing. That is, the PMOS transistors M1 and M3 and the NMOS transistors M4 and M2 are connected in series with their sources and drains connected to each other to connect the power supply VDD and the ground portion GN.
D, a pair of a first transistor series connection body 4 and a second transistor series connection body 5 forming a pair connected to each other;
The input from the comparator 1 is connected to the connection point between the PMOS transistor M3 and the NMOS transistor M4 of the first transistor series connection 1, and the gate of the PMOS transistor M1 and the gate of the NMOS transistor M2 of the second transistor series connection 5 And a connection point between the PMOS transistor M3 and the NMOS transistor M4 of the second transistor series connection unit 5 is connected to the output terminal DO of the latch circuit 3, and the gate of the PMOS transistor M1 of the first transistor series connection unit 5 is connected. And the control signal φAZ connected to the gate of the NMOS transistor M2 and the first transistor
Connected to the gate of the PMOS transistor M3 and the gate of the PMOS transistor M3 of the second transistor series connection, and outputs the inverted signal of the control signal φAZ to the gate of the NMOS transistor M4 of the first transistor series connection 4 and the second transistor It is connected to the gate of the NMOS transistor M4 in the series connection. The clocked inverter 2 of the comparator 1 also has such a circuit configuration.

In the chopper type comparator shown in FIG. 2, a latch circuit 3 inserted in the subsequent stage for timing adjustment and amplifying operation has the following circuit configuration following the clocked inverter 3 inside the comparator 1. It has been. That is, in the chopper type comparator shown in FIG. 2, the PMOS transistors M3 and M1 and the NMOS transistors M2 and M4 are connected in series with each other at their sources and drains to connect the power supply VDD and the ground portion GN.
D, a pair of a first transistor series connection body 4 and a second transistor series connection body 5 forming a pair connected to each other;
The input from the comparator 1 is connected to the connection point between the PMOS transistor M3 and the NMOS transistor M4 of the first transistor series connection 1, and the gate of the PMOS transistor M1 and the gate of the NMOS transistor M2 of the second transistor series connection 5 And a connection point between the PMOS transistor M3 and the NMOS transistor M4 of the second transistor series connection unit 5 is connected to the output terminal DO of the latch circuit 3, and the gate of the PMOS transistor M1 of the first transistor series connection unit 5 is connected. And the control signal φAZ connected to the gate of the NMOS transistor M2 and the first transistor
Connected to the gate of the PMOS transistor M3 and the gate of the PMOS transistor M3 of the second transistor series connection, and outputs the inverted signal of the control signal φAZ to the gate of the NMOS transistor M4 of the first transistor series connection 4 and the second transistor It is connected to the gate of the NMOS transistor M4 in the series connection. The clocked inverter 2 of the comparator 1 also has such a circuit configuration.

According to the first embodiment of the present invention, when the clocked inverter 2 is provided inside the comparator 1, the configuration of the latch circuit 3 inserted for the timing adjustment and the amplifying operation after the comparator 1 is changed. Since the circuit configuration is based on the configuration of the clocked inverter 2 inside 1, the input / output characteristics of the inverter can be made the same, and the precision can be improved without deterioration of the amplification effect.

Embodiment 2 FIG. Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 shows the second embodiment.
3 is a circuit diagram showing a configuration of a flash (parallel) A / D converter using a chopper type comparator in FIG.

Referring to FIG. 1, reference numeral 1 denotes a chopper comparator having the configuration in the first embodiment, reference numeral 3 denotes a latch circuit having the same configuration in the first embodiment, and reference numeral 6 denotes an encoding circuit.

According to the second embodiment of the present invention, the configuration of the latch circuit 3 inserted after the comparator 1 for the purpose of timing adjustment and amplification is changed to the circuit configuration following the configuration of the clocked inverter 2 inside the comparator 1. And the encoding circuit 6 receiving the output of the latch circuit 3, so that the input / output characteristics of the inverter can be made the same, and the flash type (parallel type) can be improved in accuracy without deterioration in amplification. Type) A / D
You can get a converter.

Embodiment 3 Third Embodiment A third embodiment according to the present invention will be described with reference to FIG. FIG. 4 is a circuit diagram of an R using a chopper type comparator according to the third embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of an interpolation type A / D converter.

In the figure, reference numeral 1 denotes a chopper type comparator having the configuration in the first embodiment described above, 3 denotes a latch circuit having the same configuration in the first embodiment, 6 denotes an encoding circuit, and R denotes an R-type interpolation. Resistance element.

According to the third embodiment of the present invention, the configuration of the latch circuit 3 inserted after the comparator 1 for the purpose of timing adjustment and amplifying operation is the same as that of the clocked inverter inside the comparator 1. R-interpolation which has the same comparator 1 and the encoding circuit 6 which receives the output of the latch circuit 3 so that the input / output characteristics of the inverter can be made the same and the precision can be improved without deterioration in amplification. Type A /
A D converter can be obtained.

Embodiment 4 Embodiment 4 of the present invention will be described with reference to FIG. FIG. 5 is a circuit diagram of a fourth embodiment using a chopper type comparator according to the present invention.
FIG. 2 is a circuit diagram showing a configuration of an interpolation type A / D converter.

In the figure, reference numeral 1 denotes a chopper comparator having the configuration in the first embodiment, 3 denotes a latch circuit having the same configuration in the first embodiment, 6 denotes an encoding circuit, and C, 2C, 3C and 4C denote Cs. This is a capacitance element that constitutes the interpolation.

According to the fourth embodiment of the present invention, the configuration of the latch circuit 3 inserted after the comparator 1 for the purpose of adjusting and amplifying the timing is the same as that of the clocked inverter inside the comparator 1. And the encoding circuit 6 receiving the output of the latch circuit 3 and the capacitance elements C, 2C, 3C, and 4C constituting the C-type interpolation, so that the input / output characteristics of the inverters are the same, and the amplification operation is performed. Thus, it is possible to obtain a C-type interpolation type A / D converter capable of achieving high accuracy without the accuracy deterioration in the above.

As described above, the chopper type comparator according to the embodiment of the present invention has the same input / output characteristics of the inverter inside the latch as the clocked inverter as compared with the conventional chopper type comparator using the clocked inverter. This leads to higher accuracy of the comparator itself and the A / D converter using the same.

[0032]

According to the first aspect of the present invention, in the chopper type comparator having the clocked inverter, the input / output characteristics of the inverters are the same because the latch circuit for performing the timing adjustment and the amplifying operation is provided after the chopper type comparator / comparator. Thus, it is possible to eliminate the deterioration in accuracy in the amplification operation and to increase the accuracy.

According to the second aspect of the present invention, in the chopper type comparator having the clocked inverter, a latch circuit for performing timing adjustment and amplifying action at a stage subsequent to the chopper type comparator comparator, and an encoding circuit for receiving an output of the latch circuit are provided. With this arrangement, it is possible to obtain an A / D converter in which the input / output characteristics of the inverters are the same and the accuracy can be improved without deterioration in amplification.

According to the third aspect of the present invention, in a chopper type comparator having a clocked inverter, a latch circuit for performing timing adjustment and amplifying action at a stage subsequent to the chopper type comparator comparator, a resistance element forming an R interpolation, To provide an R interpolation type A / D converter which has an encoding circuit for receiving the output of the latch circuit, so that the input / output characteristics of the inverter are the same, and the accuracy can be improved without deterioration in amplification. Can be.

According to the fourth aspect of the present invention, in a chopper type comparator having a clocked inverter, a latch circuit for performing a timing adjustment and an amplifying action at a stage subsequent to the chopper type comparator comparator, a capacitance element constituting a C interpolation, To provide a C interpolation type A / D converter which has an encoding circuit for receiving the output of the latch circuit, so that the input / output characteristics of the inverters are the same, and the accuracy can be improved without deterioration in amplification. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a chopper type comparator according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing another configuration of the chopper type comparator according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a parallel A / D converter according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an R-type interpolation A / D converter according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a C-type interpolation A / D converter according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a conventional chopper type comparator.

FIG. 7 is a curve diagram showing input / output characteristics of a CMOS inverter.

FIG. 8 is a circuit diagram showing a configuration example of a latch circuit used in a conventional chopper type comparator.

FIG. 9 is a curve diagram for explaining a problem when a shift occurs in the input / output characteristics of the inverter.

[Explanation of symbols]

Reference Signs List 1 chopper type comparator, 2 clocked inverter, 3 latch circuit, 6 encoding circuit, resistance element constituting RR type interpolation, C, 2C, 3
C, 4C Capacitive elements that make up C-type interpolation.

Continued on the front page (72) Inventor Masao Ito 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Toshio Kumamoto 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. In-house F term (reference) 2G035 AD03 AD13 AD23 AD25 AD47 AD65 5J022 AA06 BA01 BA08 CB01 CE08 5J039 DD01 KK04 KK28 KK31 MM16

Claims (4)

[Claims] 1. A chopper-type comparator having a clocked inverter, comprising: a latch circuit that performs a timing adjustment and an amplifying operation at a subsequent stage of the chopper-type comparator. 2. A chopper-type comparator having a clocked inverter, comprising: a latch circuit that performs a timing adjustment and an amplifying action at a stage subsequent to the chopper-type comparator; and an encoding circuit that receives an output of the latch circuit. A / D converter. 3. A chopper type comparator having a clocked inverter, comprising: a latch circuit for performing a timing adjustment and an amplifying action at a stage subsequent to the chopper type comparator; a resistance element forming an R interpolation; and an output of the latch circuit. An A / D converter comprising an encoding circuit for receiving the signal. 4. A chopper type comparator having a clocked inverter, comprising: a latch circuit for performing timing adjustment and amplifying action at a stage subsequent to the chopper type comparator; a capacitance element forming a C interpolation; and an output of the latch circuit. An A / D converter comprising an encoding circuit for receiving the signal.