JP2001195879A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a word driver outputting ternary voltage while relaxing breakdown strength in a MOS transistor and a semiconductor device using this driver. SOLUTION: This device has such a constitution that a breakdown strength relaxing MOS transistor is inserted into a word driver and NMOS transistors Mn3, Mn4 supplying a read-out potential are used. Also, the word driver is controlled by main word lines MWLbp, MWLbn, MWLRtn having different voltage amplitudes and common word lines FXtp, FXtn, FXbn.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, particularly to a semiconductor memory device. In particular, the present invention relates to a semiconductor device including a highly reliable and highly integrated memory using a memory cell having an amplifying function.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) is widely used by using a one-transistor cell including one transistor and one capacitor as a memory cell. However, in recent semiconductor devices, MOS transistors (MOSFET: Metal Oxide Semiconduc
As the tor Field Effect Transistor is highly integrated and miniaturized, the operating voltage is lowered because the withstand voltage is reduced and the power consumption is reduced. Accordingly, 1
In a DRAM using a transistor cell, the amount of a signal read from the memory cell is small because the memory cell itself has no amplifying action, and the operation is likely to be unstable due to various noises.

Therefore, as a memory cell capable of obtaining a large read signal amount by an amplifying function, a memory cell composed of three transistors (hereinafter referred to as a three-transistor cell) used before a one-transistor cell was put to practical use. Cells). Three-transistor cells are available, for example, from IEE, International Solid-State Circuits.
Conference, Digest of Technical Papers, pp. 10-11 (1972) (IEEE
International Solid-State Circuits Conference, D
IGEST OF TECHNICAL PAPERS, pp. 10-11, 1972).

This memory cell includes, for example, as shown in FIG. 2, a read NMOS transistor QR, a write NMOS transistor QW, and a charge holding NMOS transistor QN.
Consists of The gates of the transistors QR and QW are connected to a word line WL, and the sources are connected to a data line DL. The gate of the transistor QN is connected to the drain of the transistor QW, and the source of the transistor QN is grounded. Further, the drains of the transistors QN and QR are respectively connected. Here, the threshold voltage VTW of the transistor QW is
It is assumed that the threshold voltage VTR is higher than the threshold voltage VTR, and the data line voltage amplitude is equal to the power supply voltage amplitude VDL. In such a memory cell configuration, the word line voltage for the write operation must be a write potential VW higher than the threshold voltage VTW, and this value is generally set higher than the power supply voltage VDL. Further, the word line voltage in the read operation must be higher than the threshold voltage VTR and lower than the VTW, and the read potential VR is generally set between the power supply voltage level VDL and the ground potential. Furthermore, the word line voltage in the standby state (non-selected state) must be lower than the VTR, and is set to, for example, the ground potential VSS.

Further, another memory cell having an amplifying function, which is composed of two transistors and one capacitor (hereinafter abbreviated as a capacitively-coupled two-transistor cell), is disclosed in IEE Electronics. Letters (May 13, 1999), Volume 35, Issue 10, 848
−850 pages (IEE ELECTRONICS LETTERS 13th May 1999 Vo)
l.35 No.10, pp.848-850).

As shown in FIG. 3, this memory cell comprises a read NMOS transistor QR, a write transistor
QW and a coupling capacitance Cc for controlling the voltage of the memory cell node N. The feature is that the cell area is small because the transistors QR and QW have a stacked structure. Here, the transistor QW uses a transistor utilizing a tunnel phenomenon to reduce leakage current.
These elements are connected by connecting one end of the capacitor Cc and the gate of the transistor QW to the word line WL, and connecting the transistor QW
Is connected to the bit line BL. The other end of the capacitor Cc and the drain of the transistor QW are connected to the gate of the transistor QR to form a memory cell node N. Further, the source of the transistor QR is grounded, and the drain is the sense line SL. In such a cell, the word line voltage VW for the write operation and the word line voltage VR for the read operation are set as described for the three-transistor cell shown in FIG.

However, in the standby state (non-selected state), the word line voltage must be such that the potential VN (H) of the memory cell node N in which the power supply voltage level VDL is written in the standby state is lower than VTR. For example, ground potential VS
It is set to the standby potential -VB lower than S. As mentioned above,
In a three-transistor cell or a capacitively-coupled two-transistor cell, one word line is connected to a read potential VR or a write potential VW.
To control the read / write operation.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to realize a high-speed, low-power, highly-integrated DRAM while ensuring high reliability. The present invention provides a semiconductor device including a highly reliable and highly integrated memory using a memory cell having an amplifying action.

[0009] More specifically, there are two inventions as described below. A first object is to provide a sub-word driver for driving a sub-word line to a ternary word line voltage and a DRAM using the word driver. Secondly, at that time, a problem relating to the withstand voltage of the MOS transistor in the sub-word driver is solved, and a high-speed, low-power, highly-integrated DRAM while realizing high reliability is realized.

Hereinafter, the background of the present invention will be described in detail with reference to a conventional example. With the high integration and low voltage of DRAM,
The word line delay time is a problem. As means for solving this problem, a word line structure in which word lines are divided in order to reduce the load capacitance of the word lines and driven independently by drivers arranged in each of the word lines, A driver arranged for each WL has been proposed. The sub-word driver used for this configuration is
European Solid-State Circuits Conference Digest of Technical Papers Pages 131-134 (September 1992)
(European Solid-State Circuits Conference Digest
of Technical Papers, pp. 131-134, Sept. 1992).

FIG. 4 shows this circuit configuration. The circuit configuration SWD surrounded by a dotted line in FIG. 4 is an area of the sub-word driver. The main word line MWLb is connected to the gates of the PMOS transistor Mp1 and the NMOS transistor Mn1, and the common word line FXb is connected to the gate of the NMOS transistor Mn2. The common word line FXt is connected to the source of the transistor Mp1, and the sources of the transistors Mn1 and Mn2 are grounded. Transistor
The drains of Mp1, Mn1, and Mn2 are connected to sub-word lines SWL obtained by dividing the main word line into multiple parts.

The operation of the circuit shown in FIG. 4 will be described with reference to FIG. When the main word line MWLb, which is at the high-level power supply voltage VDL, is driven to the low-level ground level VSS, the common word line FXt, which is at the ground potential VSS, is driven to the power supply voltage VDL. The transistor Mp1 in the indicated sub-word driver is turned on, and the ground potential
The VSS sub word line SWL is driven to the power supply voltage VDL to be in a selected state. As described above, the conventional sub-word driver drives the voltage level of the sub-word line SWL to a binary level of a high level or a low level.

As described above, in a memory array using a three-transistor cell operating at a low voltage or a two-transistor cell of a capacitive coupling type, the word line must be ternary. Considering the case of applying, a sub-word driver for driving the sub-word line to a ternary potential is required. Also, even at low voltage operation, MOS
It is desired that the gate oxide film of the MOS transistor in the peripheral circuit be made thinner so that the driving capability of the transistor does not decrease. Therefore, the MOS of the peripheral circuit
The maximum allowable electric field of the gate oxide film of the transistor is reduced.

However, when a MOS transistor having the same oxide thickness tox as the MOS transistor of the peripheral circuit is applied to the sub-word driver, the ternary sub-word line voltage amplitude required in the capacitively coupled two-transistor cell is as described above. Since it is larger than the power supply voltage amplitude, the problem of the withstand voltage of the MOS transistor cannot be avoided.

The present invention solves the above problems.

[0016]

A typical example of the present invention for achieving the above object is a plurality of word lines, a plurality of data lines intersecting the plurality of word lines, and a plurality of word lines. And a plurality of memory cells arranged at desired intersections with the plurality of data lines, and a plurality of word drivers for driving the plurality of word lines, wherein each of the plurality of word drivers has a drain Or a first conductivity type first MOS transistor to which a first voltage is supplied to one of a source and a second conductivity type first MOS transistor to which a second voltage is applied to one of a drain and a source; For a desired period, a second conductivity type second MOS transistor to which the second voltage is applied to either the drain or the source, and a third voltage to either the drain or the source. Second conductivity type third MOS is
A transistor and a second conductivity type fourth MOS transistor in which either the drain or the source is connected to the other drain or source of the second conductivity type third MOS transistor, and each of the plurality of word drivers is And outputting any one of the first voltage, the second voltage, and the third voltage.

In the specification of the present application, "MOS transistor or MOSFET" is used as an abbreviated expression meaning an insulated gate field effect transistor.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outlines of various embodiments of the present invention will be listed, and then specific examples thereof will be described in detail. A plurality of sub-word lines; a plurality of data lines arranged so as to intersect with the plurality of sub-word lines; a main word line arranged substantially in parallel with the plurality of sub-word lines; A plurality of common word lines arranged, and a large number of memory cells arranged at desired intersections of the plurality of sub-word lines and the plurality of data lines and transmitting / receiving signals to / from the data lines by being selected by the word lines. A plurality of sub-word drivers arranged at desired intersections of the plurality of main word lines and the plurality of common word lines, each of which is selected by the main word line and the common word line and drives each of the plurality of sub-word lines; A read circuit provided to correspond to the plurality of data lines and amplifying a signal from a memory cell; and a read circuit provided to correspond to the plurality of data lines. In a semiconductor device using a hierarchical word line configuration including a write circuit for writing a signal from a memory cell, each of the plurality of sub-word drivers generates a first word line voltage in a write operation, and Each of the sub-word drivers generates a second word line voltage in a standby state, each of the plurality of sub-word drivers generates a third word line voltage in a read operation, and a MOS constituting each of the plurality of sub-word drivers. The voltage applied to the gate oxide film of the transistor is configured to be sufficiently small. Specifically, the following method is used.

First, the main word line and the common word line are each made of three pairs, and the first main word line is connected to the gate of a first PMOS transistor in the sub word driver. Connected to the source of the first PMOS transistor,
When the OS transistor is turned on, the first word line voltage is applied to the sub-word line from the first common word line through the drain of the first PMOS transistor.

Second, a second main word line in the main word line is connected to a first NMOS in the sub word driver.
Connected to the gate of the transistor, the source of the first NMOS transistor is connected to a standby potential -VB, the second NMOS transistor
When the S transistor is turned on, the first NMO
The second word line voltage is applied to the sub-word line through the drain of the S transistor.

Third, a second common word line in the common word line is connected to a gate of a second NMOS transistor in the sub word driver, and a source of the second NMOS transistor is set to a standby potential -VB. And when the second NMOS transistor is turned on, the second word line voltage is applied to the sub-word line through the drain of the second NMOS transistor.

Fourth, a third main word line in the main word line is connected to a third NMOS in the sub word driver.
A third NMOS transistor connected to the gate of the transistor, applying the third word line voltage to the source of the third NMOS transistor, and connecting the third common word line in the common word line to a fourth NMOS transistor in the sub-word driver Connected to the drain of the third NMOS transistor and the source of the fourth NMOS transistor, and connected to the third NMOS transistor.
When both the transistor and the fourth NMOS transistor are turned on, the third word line voltage is applied to the sub-word line through the drain of the fourth NMOS transistor, and the gate of the third NMOS transistor is turned on. Reduce the voltage between drains.

Fifth, the first main word line in the main word line is connected to the first PMOS in the sub word driver.
A second main word line in the main word line is connected to a gate of a first NMOS transistor in the sub-word driver, and a gate electrode of the first PMOS transistor is connected to the gate electrode of the first PMOS transistor. The voltage of the gate electrode of the NMOS transistor is divided to reduce the voltage between the gate and the source of the MOS transistor.

Sixth, a first common word line in the common word line is connected to a source of a first PMOS transistor in the sub-word driver, and a third common word line in the common word line is connected to the third common word line. 4th NM in subword driver
Connected to the gate of the OS transistor to divide the voltage of the source electrode of the first PMOS transistor and the gate electrode of the third NMOS transistor; The voltage between the gate and the drain of the NMOS transistor is reduced.

Seventh, a second PMOS transistor having a fixed voltage applied to a gate electrode is inserted between the drain of the first PMOS transistor in the sub-word driver and the sub-word line, and the gate of the PMOS transistor is connected to the gate of the first PMOS transistor. Reduce the voltage between drains.

Eighth, a fifth embodiment in which a fixed voltage is applied to the gate electrode between the drain of the first NMOS transistor in the sub-word driver or the drain of the second NMOS transistor in the sub-word driver and the sub-word line. And the voltage between the gate and the drain of the NMOS transistor is reduced.

By using the above eight methods in combination, the sub-word driver can generate a ternary word line voltage, and furthermore, the voltage applied to the gate oxide film of the MOS transistor constituting the sub-word driver Can be made sufficiently small.

The first embodiment of the present invention is as follows. A specific example of this mode is exemplified in the following first embodiment.

It comprises a plurality of word lines, a plurality of data lines intersecting the plurality of word lines, and a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data lines. , A plurality of word drivers for driving the plurality of word lines, and the plurality of word drivers
(SWD) has a first conductivity type first MOS transistor (Mp1) supplied with a first voltage (VW) to one of a drain and a source, and a second voltage (Mp1) supplied to one of a drain and a source. -VB) is applied to the second conductivity type first MOS transistor (Mn1), and the second voltage (-VB) is applied to either the drain or the source of the second conductivity type second MOS transistor (Mn2). ), A second conductivity type third MOS transistor (Mn3) to which a third voltage (VR) is applied to one of the drain and source, and the second conductivity type third MOS transistor (Mn3).
3) a second conductivity type fourth MOS transistor (Mn4) in which either the drain or the source is connected to the other drain or source of the third type, and each of the plurality of word drivers includes the first voltage and the A semiconductor device that outputs one of a second voltage and the third voltage.

According to a second aspect of the present invention, in the first aspect, each of the plurality of word drivers applies the first voltage to the word line when the first conductivity type first MOS transistor is turned on. And outputs the third voltage to the word line when the second conductivity type third MOS transistor and the fourth MOS transistor conduct, and outputs the second voltage to the word line otherwise. A semiconductor device characterized by the above-mentioned.

The third embodiment of the present invention is as follows. A specific example of this example is illustrated in FIG.

According to the present embodiment, in the first embodiment, the plurality of word drivers are of the first conductivity type between the other drain or source of the first conductivity type first MOS transistor (Mp1) and a word line. A second MOS transistor (Mp2) and a second conductive type between the other drain or source of the second conductive type first MOS transistor (Mn1) and the second conductive type second MOS transistor (Mn2) and the word line. A fifth MOS transistor (Mn5), wherein a fourth voltage (Vss) is applied to the gate of the first conductivity type second MOS transistor (Mp1),
A semiconductor device, wherein a fifth voltage (VDL) is applied to a gate of an OS transistor.

Here, the transistors Mp1 and Mn5 are not necessarily required, and a circuit may be formed.

The fourth embodiment of the present invention is as follows. A specific example of this example is illustrated in Embodiment 2.

In this embodiment, a plurality of word lines, a plurality of data lines intersecting the plurality of word lines, and a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data lines are provided. And a plurality of word drivers for driving the plurality of word lines, wherein each of the plurality of word drivers has a first voltage (VW) at a drain or a source for a desired period. A first conductivity type first MOS transistor (Mp1) to be supplied, a second conductivity type first MOS transistor (Mn1) to which a second voltage (−VB) is applied to one of a drain and a source, and a drain Or the second conductivity type second MOS transistor (Mn2) to which the second voltage (-VB) is applied to one of the sources, and the third voltage (VR) to either the drain or the source for a desired period. ) Applied second conductivity type third MOS Transistor (Mn
3), wherein each of the plurality of word drivers outputs any one of the first voltage, the second voltage, and the third voltage.

According to a fifth aspect of the present invention, in the fourth aspect, each of the plurality of word drivers includes the first voltage (VW) applied to a drain or a source of the first conductivity type first MOS transistor (Mp1). ) Is supplied, the first conductivity type first
When the MOS transistor conducts, the first voltage is output to the word line, and the second conductivity type first MOS transistor (Mn
1) or when the second conductivity type second MOS transistor (Mn2) conducts, outputs a second voltage (−VB) to the word line, and outputs the second voltage to the drain or source of the second conductivity type third MOS transistor. Three voltage (VR) is supplied, the second conductivity type third MO
When the S transistor is turned on, a third voltage is output to the word line; otherwise, the second voltage (-
VB).

The sixth embodiment of the present invention is as follows. A specific example of this example is illustrated in the third embodiment or the fourth embodiment.

In this embodiment, a plurality of word lines, a plurality of data lines intersecting the plurality of word lines, and a plurality of memories arranged at desired intersections of the plurality of word lines and the plurality of data lines are provided. A plurality of word drivers for driving the plurality of word lines, and each of the plurality of word drivers has a first voltage (VW) in either a drain or a source during a first period. The first conductivity type first MOS transistor supplied with the third potential (VR) during the second period, and the second voltage (−V
B) a second conductivity type first MOS transistor to which the second voltage (-VB) is applied to at least one of a drain and a source for at least a desired period.
And a transistor, wherein each of the plurality of word drivers outputs one of the first voltage, the second voltage, and the third voltage.

Here, the configuration in which the second voltage (-VB) is fixedly input to the source or drain of the transistor Mn2 can sufficiently achieve the object.

According to a seventh aspect of the present invention, in the sixth aspect, each of the plurality of word drivers is configured such that, when the first conductivity type first MOS transistor is turned on during the first period, the word driver is activated. Outputting the first voltage (VW) to the word line, and outputting the third voltage (VR) to the word line when the first conductivity type first MOS transistor conducts during the second period. In the case of (1), the semiconductor device outputs the second voltage (-VB) to the word line.

According to an eighth aspect of the present invention, in the sixth aspect, the plurality of word drivers are arranged such that a first conductive type MOS transistor is provided between the other drain or source of the first conductive type first MOS transistor and a word line. Type second MOS transistor (Mp2)
And a second conductive type fifth MOS transistor between the word line and the other drain or source of the second conductive type first MOS transistor and the second conductive type second MOS transistor.
(Mn5), a fourth voltage (VSS) is applied to the gate of the first conductivity type second MOS transistor, and a fifth voltage (VDL) is applied to the gate of the second conductivity type fifth MOS transistor. A semiconductor device.

According to a ninth aspect of the present invention, in the first to eighth aspects, the material for forming the region in contact with the gate oxide film of the first conductivity type first MOS transistor is the same as that of the first conductivity type. A semiconductor device characterized in that a material for forming a region in contact with a gate oxide film of a first conductivity type MOS transistor included in a circuit for driving a gate electrode of one MOS transistor is different from each other.

The tenth embodiment of the present application is the first to eighth embodiments.
In the embodiments, the first voltage (VW) is equal to the third voltage (V
R), the third voltage is equal to the second voltage (-
The semiconductor device is characterized in that the voltage is higher than VB).

According to an eleventh mode of the present invention, in the third or eighth mode, the first voltage (VW) is equal to the third voltage.
(VR), the third voltage (VR) is greater than the second voltage (-VB), and the fourth voltage (VSS) is the difference between the second voltage and the third voltage. The fifth voltage (VDL) is a voltage magnitude between the first voltage and the third voltage.

The twelfth aspect of the present invention is the eighth aspect of the present invention.
In each of the aspects, each of the plurality of memory cells performs a write operation when the word line is at a first voltage,
The semiconductor device is characterized in that when the word line is at a second voltage, a data holding state is established, and when the word line is at a third voltage, a read operation is performed.

The thirteenth embodiment of the present application is the first to eighth embodiments.
In each of the embodiments, each of the plurality of memory cells includes a first MOS transistor having a gate connected to the word line, and one of a source and a drain connected to the data line, and a gate connected to the first transistor. A second MOS transistor connected to one of the other of the source and the drain, and a gate connected to the word line, and the other of the source or the drain connected to the other of the source or the drain of the second MOS transistor Third
A semiconductor device is a dynamic three-transistor cell including a MOS transistor.

The fourteenth embodiment of the present application is the first to eighth embodiments.
In each of the embodiments, each of the plurality of memory cells includes a first MOS transistor having a gate connected to the word line, and one of a source and a drain connected to the data line, and one terminal connected to the word line. Dynamic coupling type 2 including a coupling capacitor connected to a line, and a second MOS transistor having a gate connected to the other of the drain or source of the first MOS transistor and the other terminal of the coupling capacitor. A semiconductor device, which is a transistor cell.

The first conductivity type is a P type, and the second conductivity type is an N type.

First, the present invention will be described in detail according to an embodiment, taking a case where a capacitively coupled two-transistor cell is used as a memory cell as an example.

In the following example, the voltage setting shown in FIG. 6 is assumed. FIG. 6 is a diagram showing an example of voltage setting in a DRAM using a capacitively coupled transistor cell. The level of the potential is shown at the upper and lower positions in the figure. That is, the power supply voltage is set to VDL, the high level of the bit line, the sense line and the peripheral circuit is set to the power supply voltage VDL, the low level of the bit line, the sense line and the peripheral circuit is set to the ground potential VSS, and the first level of the main word line and the common word line. The high level is VW (hereinafter, writing potential), the first low level of the main word line and the common word line is the ground potential VSS, the second high level of the main word line and the common word line is the power supply voltage VDL, the main word line And the second low level of the common word line is -VB (hereinafter, standby potential), and the first high level of the sub word line is the write potential
VW, the low level of the sub-word line is the standby potential -VB, and the second high level of the sub-word line (hereinafter, read potential) is VR.

At present, the reliability of the gate insulating film is
Generally, the standard of the maximum electric field intensity allowed in the oxide film of the S transistor must be Eox max = 4.5 [MV / cm]. At this time, gate oxide film thicknesses allowed for the PMOS transistor and the NMOS transistor in the sub-word driver are represented by toxp and toxn. The description will be made assuming that the absolute values of the threshold voltages of the PMOS transistor and the NMOS transistor are | Vthp | = −0.3 [V] and | Vthn | = 0.3 [V], respectively.

Further, in the present specification, unless otherwise specified, in a normal peripheral circuit, the gate electrode material of the PMOS transistor is made of p-plus silicon (hereinafter referred to as p + Si) doped with an acceptor at a sufficient concentration. The following describes a case where N + silicon (hereinafter, referred to as n + Si) sufficiently doped with a donor is used for an NMOS transistor. This is to reduce the threshold voltage of the MOS transistor without increasing the amount of ion implantation for adjusting the threshold voltage. In addition,
Here, the gate electrode material is a material in a portion of the gate electrode that is in contact with the gate oxide film. And a two-layer structure of p + Si.

In this case, the power supply voltage of the peripheral circuit is VDL = 1.
When 5 [V] is set, the film thickness tox allowed for the gate oxide film of the peripheral circuit is calculated, and tox = VDL ÷ Eox max = 1.5 [V]
÷ 4.5 [MV / cm] ≒ 3.3 [nm]. However, the thickness must be so large that a tunnel current flowing through the gate oxide film does not actually occur, and is estimated to be about 5 [nm].

<Embodiment 1> In describing this example, FIG. 12 is referred to from FIG. 1 and FIG. FIG. 1 is a diagram showing a configuration example of a sub-word driver for driving a sub-word line to a ternary voltage. FIG. 7 shows a typical configuration example of a hierarchical word line configuration of a DRAM according to the present invention. FIG. 8 is an operation explanatory diagram of the sub-word driver of FIG. 1, FIG. 9 is a configuration diagram of a circuit example of a main word driver of the semiconductor memory device, and FIG. 10 is a configuration diagram showing an example of a common word driver. FIG. 11 is a diagram showing an example of a memory cell array using the two capacitively coupled transistors shown in FIG. FIG. 12 is a diagram illustrating an example of the operation timing of a memory cell configured using two transistors and one capacitor.

The hierarchical word line configuration will be described below with reference to FIG. Sub word line SWL (SWL111, SWL11
2,. . . ) Independently control main word lines MWLbp (MWL1bp, MWL2bp,...) And MWLbn (MWL1).
bn, MWL2bn,. . . ), MWLRtn (MWLR1tn, MWLR2t)
n,. . . ) And the common word line FXtp (FX11tp, FX12t
p,. . . ), FXtn (FX11tn, FX12tn, ...), FXbn
(FX11bn, FX12bn,...). A plurality of these sub-word drivers SWD are provided, and the sub-word driver arrays SWDA (SWDA11, SWDA1
2,. . . ).

The sub-word line SWL is connected to the memory cell array MCA (M
CA11, MCA12,. . . ). Next to these memory cell arrays are a plurality of read / write control circuits RWC.
The read / write control circuit array RWCA (RWCA1, RWCA2,...) Composed of (RWC11, RWC12,...) Is arranged. The main word lines MWLbp, MWLbn, MWLRtn are driven by main word drivers MWD (MWD1, MWD2,...)
Subword driver array SWDA and memory cell array MCA
Cross over

Here, the main word line is composed of non-inverted (true) and inverted (bar) complementary signals.
It is distinguished by b. Further, the inverted signal is composed of a signal for a PMOS transistor and a signal for an NMOS transistor, and is distinguished by suffixes p and n of reference symbols, respectively. A set of common word lines
FXtp, FXtn and FXbn use the common word driver FXD (FXD1
1, FXD12,. . . ), And a plurality of these common word drivers FXD
(FXDA1, FXDA2, ...). The main word driver array MWDA and the common word driver array FXDA are
Subword driver array SWDA and memory cell array MCA
And read / write control circuit array RWCA.

The relationship between the sub-word lines and the memory cells is such that in the memory cell array MCA (MC11, MC12,...), The sub-word lines and the memory cells are connected to the intersections of the sub-word lines SWL and the data lines DL at positions indicated by white circles. Have been.

This memory cell, as described above,
Is a three-transistor cell shown in FIG. In the case of the capacitively coupled two-transistor cell shown in FIG. 3, a bit line BL and a sense line SL are arranged instead of the data line DL. Data line DL
(DL11, DL12, ...) are followed by a read / write control circuit RW
C (RWC11, RWC12, ...) are connected.

Although not shown in FIG. 7, the circuit of FIG. 7 includes an address input signal terminal and an address decoder for selectively controlling a memory cell for performing a read / write operation.
The input address signal is decoded by an address decoder to generate a decoded signal. The decode signal activates the main word driver MWD and the common word driver FXD so as to specify the sub-word line SWL including the selected memory cell.

<Example of the configuration of the sub-word driver>
5 shows a configuration example of a sub-word driver SWD for driving a sub-word line to a ternary voltage according to the present invention. In this figure, the P-type MOS transistor is distinguished from an N-type MOS transistor without an arrow by using a transistor symbol with an arrow according to the conductivity type of majority carrier.

The main word line signal is a PMOS transistor Mp
The main word line MWLbp is connected to the gate of the PMOS transistor Mp1 and the main word line MWLbn is connected to the gate of the NMOS transistor Mn1 separately for the NMOS transistor Mn1 and the NMOS transistor Mn1. The main word line MWLRtn is connected to the gate of the NMOS transistor Mn3. The common word line is also different for PMOS transistor Mp1 and NMOS transistor Mn4.
The common word line FXtp is connected to the source of the transistor, and the common word line FXtn is connected to the gate of the NMOS transistor Mn4.
The common word line FX is connected to the gate of the NMOS transistor Mn2.
bn is connected. The sources of the NMOS transistors Mn1 and Mn2 are connected to the standby potential -VB, and the read potential VR is input to the source of the NMOS transistor Mn3. PMOS transistor Mp
2 and the NMOS transistor Mn5 are MOS transistors for alleviating the electric field, and apply a fixed voltage to the gate electrode. FIG. 1 shows an example in which the ground potential VSS and the power supply voltage VDL are respectively applied. Further, the transistor Mn4 also plays a role of an electric field relaxation MOS. The sub-word line SWL is connected to the drains of the transistors Mp2, Mn4, and Mn5.

<Operation of Subword Driver> The operation of the subword driver SWD of FIG. 1 will be described with reference to FIG.

FIG. 9 shows a case where the sub-word line SWL111 is selected, and the read operation and the write operation are continuously performed from the standby state. First, the ground potential VS
When the read control signal φr, which is S, is driven by the power supply voltage VDL and enters the read state, the main word driver
MWD1 is the main word line MWL1b at the power supply voltage VDL
n is driven to the standby potential -VB, and the main word line MWLR1tn at the standby potential -VB is driven to the power supply voltage VDL. Further, the common word driver FXD11 is connected to the common word lines FX11tp, FX11tn at the ground potential VSS and the standby potential −VB.
Are driven to the write potential VW and the power supply voltage VDL, respectively.
Therefore, the main word line MWL1bp is the write potential VW, the main word line MWL1bn is the standby potential -VB, and the main word line MW
LR1tn is driven to the power supply potential VDL, the common word line FX11tp is driven to the write potential VW, the common word line FX11tn is driven to the power supply voltage VDL, and the common word line FX11bn is driven to the standby potential -VB, so that the transistors Mn3 and Mn4 are turned on. Then, the sub-word driver SWD111 is selected,
The sub-word line SWL111 having the standby potential -VB is driven to the read potential VR.

Next, when the read control signal φr at the power supply voltage VDL is driven to the ground potential VSS to enter a write state, the main word driver MWD1 outputs the write potential VW
Is driven to the ground potential VSS, and the main word line MWLR1t at the power supply voltage VDL
n is driven to the standby potential -VB. Therefore, the main word line MW
L1bp is driven to the ground potential VSS, the main word line MWL1bn is driven to the standby potential -VB, the main word line MWLR1tn is driven to the standby potential -VB, and the common word line FX11tp is driven to the write potential VW,
The common word line FX11tn has the power supply voltage VDL and the common word line FX
When the transistors 11bn are driven to the standby potential -VB, respectively, the transistors Mp1 and Mp2 are turned on, the sub-word driver SWD111 is selected, and the sub-word line SWL111 having the read potential VR is driven to the write potential VW.

As described above, the sub-word driver SWD11
In the operation in which 1 is selected, the unselected sub-word driver is in three states. That is, first, the main word line and the common word line are both unselected, second, the main word line is selected and the common word line is not selected, and third, the main word line is unselected. There are three states in which the word line is selected. Hereinafter, these will be described in order.

First, a state where both the main word line and the common word line are not selected will be described. During standby, all sub-word drivers SWD are in such a non-selected state.
When the sub-word driver SWD111 is selected,
For example, the sub-word driver SWD 221 keeps the same state as during standby. Therefore, the sub-word driver SWD during standby will be generalized and described. The main word line MWLbp is the write potential VW, the main word line MWLbn is the power supply voltage VDL,
The main word line MWLRtn is driven to the standby potential -VB, the common word line FXtp is connected to the ground potential VSS, and the common word line FXt
n is the standby potential -VB, and the common word line FXbn is driven by the power supply voltage VDL, so that the sub-word driver SWD
, The transistors Mn1, Mn2 are turned on, the transistors Mp1, Mn3, Mn4 are turned off, and the sub-word line SW
L is kept at the standby potential -VB.

Second, a state where the main word line is selected and the common word line is not selected will be described. Subword driver
When the SWD 111 is selected, for example, the sub-word driver SWD 121 enters this state. Subword driver SWD
The operation of 121 is shown in the middle part of FIG.

First, when the read control signal φr at the ground potential VSS is driven by the power supply voltage VDL to enter the read state, the main word driver MWD1 changes the main word line MWL1bn at the power supply voltage VDL to the ground potential VSS. Main word line MWLR1tn driven and at standby potential -VB
To the power supply voltage VDL. Also, the common word driver F
XD21 holds the non-selected state, and the common word line FX21tp,
FX21tn and FX21bn are held at ground potential VSS, standby potential -VB and power supply voltage VDL. Therefore, the main word line M
WL1bp is driven to write potential VW, main word line MWL1bn is driven to standby potential -VB, main word line MWLR1tn is driven to power supply potential VDL, and common word line FX21tp is driven to ground potential VS.
S, common word line FX21tn is standby potential -VB, common word line
When the FX21bn is driven to the power supply voltage VDL, the transistors Mn2 and Mn3 in the sub-word driver SWD121 are turned on, and the transistors Mp1, Mn1, and Mn4 are turned on.
Is turned off, and the sub-word line SWL121 is set to the standby potential −
Hold in VB.

Next, the read control signal φr changes to the power supply voltage VDL.
, The main word driver MWD1 drives the main word line MWL1bp at the write potential VW to the ground potential VSS, and the main word line MWLR1tn at the power supply voltage VDL.
Is driven to the standby potential -VB. Therefore, the main word line MWL
1bp is ground potential VSS, main word line MWL1bn is standby potential
-VB, the main word line MWLR1tn is driven to the ground potential VSS, the common word line FX21tp is the ground potential VSS, the common word line FX21tn is the standby potential -VB, and the common word line FX21b.
When n is driven to the power supply voltage VDL, respectively, the transistor Mn2 in the sub-word driver SWD121 is turned on, the transistors Mp1, Mn1, Mn3, and Mn4 are turned off, and the sub-word line SWL121 is kept at the standby potential-.
Hold in VB.

Third, a state in which the common word line is selected while the main word line is not selected will be described. When the sub-word driver SWD111 is selected, for example, the sub-word driver SWD211 enters this state. The operation of the sub-word driver SWD 211 is shown in the lower part of FIG.

First, when the read control signal φr at the ground potential VSS is driven by the power supply voltage VDL to be in the read state, the main word driver MWD2 holds the non-selected state, and the main word drivers MWL2bp, MWL2bn and MWLR2tn.
At the write potential VW, the power supply voltage VDL, and the standby potential -VB. Further, the common word driver FXD11 is connected to the common word line FX11t having the ground potential VSS and the standby potential -VB.
p and FX11tn are driven to the writing potential VW and the power supply voltage VDL, respectively. Therefore, the main word line MWL2bp is driven to the write potential VW, the main word line MWL2bn is driven to the power supply potential VDL, and the main word line MWLR2tn is driven to the standby potential -VB.
The common word line FX11tp has the write potential VW and the common word line
When the FX11tn is driven to the power supply voltage VDL and the common word line FX11bn is driven to the standby potential -VB, the transistors Mn1 and Mn4 in the sub-word driver SWD211 are turned on, the transistors Mp1, Mn2 and Mn3 are turned off, and the sub-word line SWL211 is turned off. At the standby potential -VB.
Further, the read control signal φr which is the power supply voltage VDL
Is driven to the ground potential VSS and enters the write state,
The states of the main word lines MWL2bp, MWL2bn and MWLR2tn and the common word lines FX11tp, FX11tn and FX11bn are held, and the sub-word driver SWD211 keeps the sub-word line SWL211 at the standby potential -VB.

Based on the above operation, an example of a voltage applied to the gate oxide film of each MOS transistor in the sub-word driver SWD111 having the configuration shown in FIG. As an example, the power supply voltage is VDL = 1.5 [V], the standby potential is -VB =-
2 [V], read potential VR = 0.5 [V], write potential V
An NMOS transistor when W = 3 [V] will be described.

The selected sub-word driver SWD111
Since the second high-level power supply voltage VDL is input to the gate of the MOS transistor Mn5, the voltage applied between the gate and the drain of the MOS transistor Mn5 is VW-VDL = 1. 5 [V]. Further, since the NMOS transistors Mn1 and Mn2 are in the cut-off state, no current constantly flows through the transistor Mn5, and the source potential of the transistor Mn5 becomes (VDL-Vthn). Therefore, the voltage applied to the gate oxide film between the gate and the source of the transistor Mn5 becomes VDL- (VDL-Vthn) = 0.3 [V], and the gate oxide film between the gate and the drain of the NMOS transistors Mn1 and Mn2. Becomes (VDL-Vthn)-(-VB) = 3.2 [V] during the write operation. Therefore, by inserting the transistor Mn5 in which the power supply voltage VDL is input to the gate, the transistor Mn1
Is reduced from the write potential VW to (VDL-Vthn), the voltage applied to the gate oxide film between the gate and drain of the transistors Mn1 and Mn2 is VW- (VDL-Vthn) = 1.8 [ V]. In a write operation, VDL is input from the common word line FXtn to the gate of the MOS transistor Mn4, so that the gates of the transistors Mn3 and Mn4 are
-The same discussion holds for the voltage applied between the drain and the gate source, and the withstand voltage can be reduced.

On the other hand, the main word lines MWLbp and MWLbn are separated from the common word lines FXtp and FXnp in the standby and non-selected sub-word drivers, so that the voltage input to the gates of the transistors Mn1 and Mn2 becomes VW-VDL = 1.5 [V], and the withstand voltage can be reduced. That is, the voltage input to the transistors Mn1 and Mn2 is reduced by this amount, and the voltages applied between the gate and the drain and between the gate and the source are reduced by the transistors Mn1, Mn2 and Mn.
5, and VDL-(-VB) = 3.5 [V]. Therefore, the sub-word driver is configured as shown in FIG.
(VDL + VB) ÷ Eox max = so as not to exceed 5 [MV / cm]
By making the thickness more than 3.5 [V] ÷ 4.5 [MV / cm] ≒ 7.8 [nm], the NMOS in the sub-word driver can be controlled in this range.
By setting the gate oxide film thickness toxn of the transistor, the problem of the withstand voltage in the gate oxide film between the gate and the drain of the transistors Mn1 and Mn2 can be solved. From this result and the above-mentioned numerical value of tox, if the gate oxide film thickness is divided between the sub-word driver and the peripheral circuit, it is possible to realize a high-speed circuit.

On the other hand, if the film thickness of the peripheral circuit is adjusted to the value of the sub-word driver, the processing steps are simplified and the number of masks can be reduced. In some cases, the main word line
The second high level of MWLbn (here, the power supply voltage VDL) and the voltage level input to the gate of the transistor Mn5 can be set to appropriate values within a range not exceeding the maximum electric field of 4.5 [MV / cm]. The voltage level input to the gate of the transistor Mn5 may be a pulse signal having an appropriate amplitude. However,
The driving capability of the transistor Mn5 is changed to the transistors Mn1 and Mn2.
In order to reduce the load on the power supply system in the chip and not increase the number of voltage supply lines,
It is desirable that the power supply voltage VDL be the same as the high level of DL.

Next, the PMOS transistor will be described. In the selected sub-word driver SWD111, on the other hand, the voltage input to the gates of the transistors Mp1 and Mp2 can be increased by VSS-(-VB) = 2 [V] by dividing the main word lines MWLbp and MWLbn. Thus, the withstand voltage can be reduced. That is, the voltage input to the transistors Mp1 and Mp2 is reduced by this amount, and the PMOS transistors Mp1 and Mp2 are reduced.
2, the potential difference between the gate and the source and between the gate and the drain becomes maximum during the write operation, and the write potential VW = 3
[V]. On the other hand, since the ground potential VSS is fixedly input to the gate of the transistor Mp2 in the standby state or the non-selection state, the voltage applied to the gate oxide film between the gate and the drain of the transistor Mp2 is VSS − (− VB) = 2 [V]. Further, since the transistor Mp1 is in the off state, no current constantly flows through the transistor Mp2.
Since the source potential of Mp2 is VSS + | Vthp | = 0.3 [V], the potential difference between the gate and source of the transistor Mp2 is (VSS + | Vthp |) -VSS = 0.3 [V]. Therefore, the voltage applied to the gate oxide film between the gate and the drain of the PMOS transistor Mp1 is VW- | Vthp | = 2.7 [V]. Therefore, by inserting the transistor Mp2 in which the ground potential VSS is input to the gate,
Since the drain potential of Mp1 is raised from the writing potential -VB to the threshold voltage | Vthp |, the withstand voltage can be reduced. That is, the voltage applied to the gate oxide film between the gate and the drain can be reduced by (VW + VB)-(VW- | Vthp |) = 2.3 [V]. From the above, the sub-word driver is configured as shown in FIG. 1, and VW ÷ Eox max = 3 [V so that the gate oxide film thickness toxp of the PMOS transistor does not exceed the maximum electric field of 4.5 [MV / cm]. By making the thickness larger than 4.5 [MV / cm] nm6.7 [nm], the problem of the withstand voltage in the gate oxide film between the gate and the drain of the transistors Mp1 and Mp2 can be solved. From this result and the above-mentioned numerical value of tox, if the gate oxide film thickness is divided between the sub-word driver and the peripheral circuit, it is possible to realize a high-speed circuit.

On the other hand, if the film thickness of the peripheral circuit is adjusted to the value of the sub-word driver, the processing steps are simplified and the number of masks can be reduced. In some cases, the main word line
The first low level of MWLbp (ground potential VSS in this case) and the voltage level input to the gate of the transistor Mn5 can be set to appropriate values within a range not exceeding the maximum electric field of 4.5 [MV / cm]. The voltage level input to the gate of the transistor Mp2 may be a pulse signal having an appropriate amplitude. However,
In order to make the driving capability of the transistor Mp2 comparable to that of the transistor Mp1, to reduce the load on the power supply system in the chip, and not to increase the number of voltage supply lines, the same ground potential VSS as the low level of the data line DL is used. desirable.

Further, by combining the method in which the gate electrode material of the transistors Mp1 and Mp2 is n + Si, the voltage applied to the gate oxide film between the gate and the drain of the transistor Mp2 is The work function difference ΔW can be reduced by about 1V which is equal to the work function difference ΔW, and the gate oxide film thickness can be further reduced.

The features of the sub-word driver shown in FIG. 1 described above will be summarized.

(1) In this circuit configuration, a select / non-select signal of a voltage level corresponding to a read / write operation of a memory cell can be generated using a decode signal in a conventional hierarchical word line structure. That is, by inserting the NMOS transistors Mn3 and Mn4, the selected sub-word line can be driven to the read potential VR during the read operation and to the write potential VW during the write operation. When the standby state or the non-selected state is maintained, the corresponding sub-word line can be maintained at the standby potential -VB.

(2) Further, in this circuit configuration, the electric field applied to the gate oxide film of the MOS transistor can be reduced irrespective of selection / non-selection. That is, for electric field relaxation
By inserting the PMOS transistor Mp2 and the NMOS transistor Mn5, the problem of withstand voltage in the gate oxide film between the gate and the drain of the PMOS transistor Mp1 and the NMOS transistors Mn1 and Mn2 can be solved.

(3) The main word line MWL signal is separated into MWLbp and MWLbn having different voltage amplitudes, and the common word line FX signal is separated into FXtp and FXtn having different voltage amplitudes. It is possible to solve the problem of the withstand voltage in the gate oxide film between the gate and the source of the transistor Mp1 in the driver and the problem of the withstand voltage in the gate oxide film between the gate and the source and the gate and the drain of the transistors Mn1 and Mn2 in the unselected sub-word driver. In addition, the problem of withstand voltage in the gate oxide film between the gate and the drain of the transistor Mn3 in the unselected sub-word driver can be solved.

(4) Further, by applying a method of increasing the threshold voltage by setting the gate electrode material of the transistor Mp1 to n + Si whose work function is about 1 V smaller than that of p + Si, the transistor Mp1 in the selected sub-word driver is applied. Can also solve the problem of withstand voltage in the gate oxide film between the gate and the drain. Therefore, a sub-word driver for driving a sub-word line to a ternary voltage can be constituted by seven MOS transistors while solving the problem of withstand voltage of the MOS transistor.

The main word lines MWLbp, MWLbn and MWLRtn connected to the sub-word driver shown in FIG. 1 and the main word drivers MWD and the common word drivers FXD for driving the common word lines FXtp, FXtn and FXbn are shown below.

<Example of Main Word Driver> FIG. 9 shows an example of a circuit configuration of the main word driver MWD. By using the sub-word driver shown in FIG. 1, the voltage amplitude of the main word line is VS, which is the power supply voltage amplitude of the peripheral circuit.
Since the voltage must be from -VB to VW which is larger than S to VDL, the voltage amplitude of the peripheral circuit is level-shifted by the main word driver. Further, in order to solve the withstand voltage problem in the gate oxide film between the gate and the source and between the gate and the drain of the transistors Mp1, Mn1 and Mn2 of the sub-word driver, to generate a selection signal of a voltage level according to the read / write operation of the memory cell. And three kinds of main word lines
MWLbp, MWLbn and MWLRtn are used. Therefore,
The main word driver MWD is composed of the level shift circuits LSCH, LSCL1, and LSCL2 that independently drive the main word lines MWLbp, MWLbn, and MWLRtn, and the read / write control circuit RWCC1.

First, the read / write control circuit RWCC1 will be described. The decode signal axj is input to the first input terminal of the NOR circuit NR1 via the inverter circuit NV1, and the read control signal φr is input to the second input terminal of NR1. Also,
The decode signal axj is input to the first input terminal of the NAND circuit ND1, and the read control signal φr is input to the second input terminal of ND1. The output of NR1 is used as a decoded signal axjr11 and ND
1 is a decode signal axjr12.

Next, the first level shift circuit LSCH will be described. This circuit converts an input signal having a voltage amplitude of the power supply voltage VDL from the ground potential VSS to the power supply voltage VDL from the ground potential VSS.
This is a circuit that outputs a signal having a voltage amplitude of a higher level (here, the writing potential VW). The decode signal axjr11 is input to the gate of the NMOS transistor Mn1 and the source of the NMOS transistor Mn2.
Ground source. A first main word line MWLbp is connected to the drain of the transistor Mn1 and the drain of the PMOS transistor Mp1 and the gate of Mp2. Also, transistors Mp1, Mp
Write the source of p2, input the voltage VW, and set the transistor M
The drains of n2 and Mp2 are connected to the gate of transistor Mp1 to form a feedback path. Here, the transistor Mn2
When the output of the main word line MWLbp is at the ground potential VSS, the through current through the transistor Mp2 is cut off.

Further, a second level shift circuit LSCL1,
The level shift circuit LSCL1 of the LSCL2 will be described.
The level shift circuits LSCL1 and LSCL2 have the same circuit configuration, and apply an input signal having a voltage amplitude of the power supply voltage VDL from the ground potential VSS to a voltage of the power supply voltage VDL from a level lower than the ground potential VSS (here, the standby potential -VB). This is a circuit that outputs as a signal with amplitude.

The gate of the PMOS transistor Mp1 and the PMOS
The decode signal axj is input to the source of the transistor Mp2, and the power supply voltage VDL is input to the source of the transistor Mp1. The second main word line MWLbn is connected to the drains of the transistor Mp1 and the NMOS transistor Mn1 and the gate of Mn2. The sources of the transistors Mn1 and Mn2 are connected to the standby potential -VB, and the drains of the transistors Mp2 and Mn2 are connected to the gate of the transistor Mn1 to form a feedback path. Here, the ground potential is applied to the gate of the transistor Mp2.
By inputting VSS, the through current via the transistor Mn2 is cut off when the output of the main word line MWLbn becomes the power supply voltage VDL.

<Operation of Main Word Driver> The operation of the main word driver MWD using the above configuration will be described. The main word driver MWD is selected when the decode signal axj becomes the power supply voltage VDL. Then, the three types of main word lines MWLbp, MWLbn and MWLRtn are driven to a voltage level corresponding to the read / write operation of the memory cell.

That is, when the read control signal φr at the ground potential VSS is driven by the power supply voltage VDL to perform a read operation, the decode signal axjr11 of the ground potential VSS is input to the level shift circuit LSCH, and the transistor Mp1 is turned on. Then, the main word line MWLbp is held at the write potential VW. Further, the decode signal axj of the power supply voltage VDL is input to the level shift circuit LSCL1, and the transistor Mn1 is turned on to drive the main word line MWLbn at the power supply voltage VDL to the standby potential -VB. In addition, the ground potential VSS decode signal
axjr12 is input to the level shift circuit LSCL2, and the transistor Mp1 is turned on to drive the main word line MWLRtn, which is at the standby potential -VB, to the power supply voltage VDL.

On the other hand, when the read control signal φr at the power supply voltage VDL is driven to the ground potential VSS to perform a write operation, the decode signal axjr11 of the power supply voltage VDL is input to the level shift circuit LSCH, and the transistor Mn1 is turned on. Then, the main word line MWLbp having the write potential VW is driven to the ground potential VSS. Also, since the decode signal axj remains at the power supply voltage VDL, the transistor Mn1 is turned on in the level shift circuit LSCL1 and the main word line MWLb
n is kept at the standby potential -VB. Further, the decode signal axjr12 of the power supply voltage VDL is input to the level shift circuit LSCL2, and the transistor Mn1 is turned on to drive the main word line MWLRtn at the power supply voltage VDL to the standby potential -VB.

The voltage applied to the gate oxide film of each transistor in the main word driver performing such an operation will be described. In the level shift circuit LSCH, the voltage applied to the gate oxide film between the gate and the source and between the gate and the drain of the transistor Mp1 becomes VW at the maximum in the standby state and in the read operation of the selected main word driver. Further, the voltage applied to the gate oxide film between the gate and the source of the transistor Mp2 is the maximum in the write operation of the selected main word driver, and the voltage applied to the gate oxide film between the gate and the drain of the transistor Mp2 is standby. The maximum is VW in both the state and the read operation of the selected word driver. Therefore, if the same gate oxide film thickness and gate electrode material as those of the PMOS transistor in the sub-word driver shown in FIG.
Withstand voltage problems can be avoided. On the other hand, the level shift circuit LSCL
1. In the LSCL2, the voltage applied to the gate oxide film between the gate and the source and between the gate and the drain of the transistor Mn1 becomes (VDL + VB) at the maximum in the read operation of the selected main word driver. Also, the transistor Mn2
The voltage applied to the gate oxide film between the gate and the source of the transistor Mn2 is the largest in the read operation of the selected main word driver, and the voltage applied to the gate oxide film between the gate and the drain of the transistor Mn2 is the standby state and the selected word. The maximum in the write operation of the driver, both (VDL + V
B). Therefore, if the same gate oxide film thickness as that of the NMOS transistor in the sub-word driver shown in FIG. 1 is used, the withstand voltage problem can be avoided.

<Example of Common Word Driver> FIG. 10 shows a common word driver FXD. By using the sub-word driver shown in FIG. 1, the voltage amplitude of the common word line is from -VB to VW, which is larger than the power supply voltage amplitude of the peripheral circuit, VSS to VDL. To shift the level. The gates of the transistors Mp1, Mn2 and Mn4 of the sub-word driver
In order to solve the problem of withstand voltage in the gate oxide film between the source and the gate-drain, and generate a selection signal of a voltage level according to the read / write operation of the memory cell, three types of common word lines FXtp, FXtn and FXbn are used. Used.

Here, the common word line FXbn is a common word line.
Since it is an inverted signal of FXtn, the level shift circuits LSCH and LSCL that independently drive the common word lines FXtp and FXtn and the inverter circuits NVL and NV1 constitute the common word driver FXD. The level shift circuits LSCH and LSCL have the same configuration as that described in the main word driver. The decode signal aj is input to the level shift circuit LSCH, and the decode circuit aj is used as an inverter circuit.
The decode signal ajb generated via the NV1 is input to the level shift circuit LSCL. The output of the level shift circuit LSCH is a common word line FXtp, and the output of the level shift circuit LSCL is a common word line FXbn. The inverter circuit NVL includes a PMOS transistor Mp1 and an NMOS transistor Mn1,
The difference from the inverter of the peripheral circuit is that the standby potential -VB is input to the source of the NMOS transistor Mn1. Transistor Mp
1, the common word line FXbn is connected to the gate of Mn1, and the drain is the common word line FXtn.

<Operation of Common Word Driver> Next, the operation of the common word driver FXD using the above configuration will be described. The common word driver FXD is selected when the decode signal aj becomes the ground potential VSS, and in the level shift circuit LSCH, the transistor Mp1 is turned on and the ground potential VS is turned on.
The common word line FXtp which is set to S is driven to the write potential VW. The decode signal ajb of the power supply voltage VDL is input to the level shift circuit LSCL, and the transistor Mn1 is turned on to drive the common word line FXbn at the power supply voltage VDL to the standby potential -VB. The common word line FXbn of this standby potential -VB
As a result, the transistor Mp1 is turned on in the inverter NVL, and the common word line FXtn at the standby potential -VB is driven to the power supply voltage VDL.

In the common word driver that performs such an operation, the voltage amplitude of the input / output signal is the same as that of the above-mentioned main word driver, so that the voltage applied to the gate oxide film of each transistor is also equal to that of the main word driver. Therefore, if a transistor having the same gate oxide film thickness as the PMOS transistor and the NMOS transistor in the above-described sub-word driver is used for the common word driver, the withstand voltage problem can be solved.

<Example of Memory Cell Array> FIG.
2 shows a memory cell array MCA1 using the capacitively coupled two-transistor cell shown by. As an example of the voltage setting, a voltage setting example suitable for the capacitively coupled two-transistor cell DRAM shown in FIG. 6 is applied. For simplicity, only four memory cells MC are shown for two bit lines BL1 and BL2, two sense lines SL1 and SL2, and two sub-word lines SWL111 and SWL121. A plurality of lines SL and sub-word lines SWL are arranged, and a large number of memory cells MC are arranged at desired intersections thereof.

FIG. 11 shows an example in which a memory cell MC is arranged at each intersection of a bit line BL, a sense line SL and a sub-word line SWL. Further, specific circuit configurations such as switches for controlling operation timings of a read circuit, a write circuit, and a precharge circuit provided for each bit line and each sense line and input / output switches are omitted. These are conventional ones.

FIG. 12 shows the operation of the memory cell.
First, when a pulse voltage of a writing potential VW higher than the threshold voltage VTW of the transistor QW is applied to the selected sub-word line SWL, the transistor QW conducts, and the potential of the bit line corresponding to the writing data changes to the memory cell node. Given to N, a write operation is performed. This potential is applied from a voltage applied from the outside via a write circuit selected in a column. For example, when information "1" is stored, the power supply voltage VD
L, which is the ground potential VSS when information “0” is stored. Next, the sub word line SWL becomes the standby potential -VB. At this time, the voltage VN (H) of the memory cell node given the power supply voltage VDL
Is the threshold voltage VTR of the transistor QR due to the capacitive coupling Cc.
Therefore, the transistors QR and QW are cut off to retain information. In addition, the sense line is
When a pulse potential of the read potential VR is applied to the selected sub-word line after being precharged to VDL, a signal potential corresponding to the information held in the memory node N is read to the sense line SL.

For example, when the information “1” is stored, the voltage of the memory cell node which has been VN (H) becomes VN ′ (H) higher than the threshold voltage VTR of the transistor QR due to the capacitive coupling Cc. Therefore, the transistor QR conducts, and the sense line SL, which has been precharged to the power supply voltage VDL, is discharged to the ground potential VSS. On the other hand, when the information “0” is stored, the voltage of the memory cell node that has been VN (L) becomes VN ′ (L) lower than the threshold voltage VTR of the transistor QR due to the capacitive coupling Cc. The transistor QR holds the cutoff state, and the precharged sense line SL is held at the power supply voltage VDL. As a result, a desired voltage is taken out from the signal read out to the sense line SL via the readout circuit selected in the column, and a read operation is performed.

In the above description, when the capacitively coupled two-transistor cell shown in FIG. 5 is applied to the hierarchical word line structure shown in FIG. 7, each circuit will be described centering on the sub-word driver. It has been shown that the selected sub-word line can be driven to a ternary potential while the voltage applied to the gate oxide film is sufficiently small.

FIG. 9 shows the read control signal φr
Has shown the example of driving the main word line MWL by
The write control signal φwb and the decode signal ax shown in FIG.
A read control circuit is constructed using j and the main word line M
The WL may be driven. Further, the capacitive coupling type 2 shown in FIG.
In the transistor cell, the transistor QW is a transistor using the tunnel phenomenon. However, since the transistor QW operates as an NMOS transistor, the transistor QW may be a normal NMOS transistor.

Further, a case where a memory cell which controls a read / write operation with a ternary word line voltage, as represented by the three-transistor cell shown in FIG. 4, is applied to the hierarchical word line structure shown in FIG. Also each MOS in each circuit
To drive the selected sub-word line to a ternary potential while sufficiently reducing the voltage applied to the gate oxide film of the transistor, the method shown in FIGS. 1, 9 and 10 can be applied. . Hereinafter, another configuration example of the sub-word driver will be described.

<Embodiment 2> FIG. 13 shows an MO for electric field relaxation.
4 shows a circuit configuration example of a sub-word driver having no S transistor.

The sub-word driver of FIG. 13 is different from the circuit configuration of the sub-word driver shown in FIG. 1 in that the PMOS transistor Mp2 and the NMOS transistor Mn5 are removed.
Further, the difference is that the NMOS transistor Mn4 for selecting the read potential is removed and shared with the NMOS transistor Mn3, and the source of the transistor Mn3 is connected to the common word line FXtn. Therefore, the sub-word line for driving the selected sub-word line to a ternary potential can be constituted by four MOS transistors, and the feature is that an increase in the circuit area of this portion is suppressed.

In such a circuit configuration, the gate oxide film of each MOS transistor constituting the sub-word driver is sufficiently thick, and the electric field in the gate oxide film between the gate and source and between the gate and drain of each MOS transistor is the maximum electric field Eox. Applicable if max is not exceeded. Also, in the voltage setting example suitable for the capacitively coupled two-transistor cell DRAM shown in FIG. Is applicable even when the electric field at does not exceed the maximum electric field Eox max.

The circuit configuration shown in FIG. 9 is used for the main word driver MWD driving the main word lines MWLbp, MWLbn and MWLRtn connected to the sub-word driver shown in FIG.

On the other hand, common word lines FXtp, FXtn and FXbn
Are shown in FIG. Compared with the common word driver FXD shown in FIG. 10, the inverter circuit NVL1 for driving the common word line FXtn
Potential at the source of the PMOS transistor Mp1
The difference is that VR is input. Therefore, the voltage amplitude of the common word line FXtn signal changes from the standby potential -VB to the read potential VR.

The operation of the sub-word driver shown in FIG.
It is shown in FIG. FIG. 15 is a diagram showing operation timings of the sub-word driver for generating ternary voltage levels, and shows the operation timings as in FIG. FIG. 1 shown in FIG.
Compared to the operation of the sub word driver, the common word line FX
The operation when tn is selected is different.

First, the case where both the main word line and the common word line are selected will be described. The selected main word driver MWD1 connects the main word line MWLR1tn, which has been at the standby potential -VB in the read operation, to the power supply voltage Vd.
Drive to DL. In addition, the common word driver
Read the common word line FX11tn that is -VB
Drive to R. Therefore, the transistor Mn3 conducts,
The sub-word line SWL111 is selected, and the sub-word line SWL111 at the standby potential -VB is driven to the read potential VR.

Next, the case where the main word line is not selected and the common word line is selected will be described. Sub word line
When the SWL 111 is selected, for example, the sub word line SWL2
11 is in this state. The main word driver MWD2 holds the non-selected state, and the main word lines MWL2bn, MWLR2t
n is held at the power supply voltage VDL and the standby potential -VB, respectively. On the other hand, the common word driver drives the common word line FX11tn at the standby potential -VB to the read potential VR. Therefore, the transistor Mn3 is cut off, the transistor Mn1 is turned on, and the sub-word line SWL211 is set at the standby potential −
VB is not selected.

Although the main word line MWLRtn is connected to the gate of the transistor Mn3 and the common word line FXtn is connected to the source of the transistor Mn3 in the circuit configuration example shown in FIG. 13, it is common to the gate of the transistor Mn3. A configuration is also possible in which the word line FXtn is connected and the main word line MWLRtn is connected to the source of the transistor Mn3. In this case, in the main word driver shown in FIG. 9, the read potential VR is input to the source of the transistor Mp1 in the level shift circuit LSCL2, and the main word line MWLRtn signal amplitude is changed from the standby potential -VB to the read potential VR. Driver configuration. Also, the common word driver is
In the circuit configuration shown as 0, the amplitude of the common word line FXtn signal is changed from the standby potential -VB to the power supply voltage VDL.

<Embodiment 3> FIG. 16 shows a configuration example of still another sub-word driver.

Unlike the sub-word driver shown in FIG. 1, the NMOS transistors Mn3 and Mn4 and the main word line MWLR
The feature is that the circuit configuration is simplified by removing tn and the common word line FXtn. Furthermore, in order to generate a ternary word line voltage using such a circuit configuration, the potential of the common word line Fxtp connected to the source of the PMOS transistor Mp1 is controlled according to the read operation and the write operation. is there.

Referring to FIG. 17, the operation of sub-word driver SWD of FIG. 16 will be described. In the figure, the sub word line SWL1
11 shows a case in which the reading operation and the writing operation are continuously performed from the standby state. The main word driver MWD1 drives the main word line MWL1bp, which is at the write potential VW, to the ground potential VSS, and
VDL main word line MWL1bn is set to standby potential -VB
Drive. In this state, first, when the read control signal φr at the ground potential VSS is driven by the power supply voltage VDL to enter the read state, the common word driver FXD11
Common word line FX with ground potential VSS and power supply voltage VDL
11tp, FX11bn read potential VR, standby potential respectively
-Drive to VB. Therefore, main word line MWL1bp, MWL
1bn are driven to the ground potential VSS and the standby potential -VB, respectively.
When the common word lines FX11tp and FX11bn are driven to the read potential VR and the standby potential -VB, respectively, the transistor Mp1 is turned on, the sub-word driver SWD111 is selected, and the sub-word line SWL11 having the standby potential -VB is set.
1 is driven to the read potential VR.

Next, when the read control signal φr at the power supply voltage VDL is driven to the ground potential VSS to enter the write state, the common word driver FXD11 outputs the read potential Vd.
Write potential VW to common word line FX11tp that is R
Drive. Therefore, the main word lines MWL1bp and MWL1bn
Are driven at the ground potential VSS and the standby potential -VB, respectively, and the common word lines FX11tp and FX11bn are driven at the write potential VW and the standby potential -VB, respectively, so that the transistor Mp1 is turned on and the sub-word driver SWD is turned on.
111 is selected, and the sub-word line SWL111 which is at the read potential VR is driven to the write potential VW.

The main word driver MWD and the common word lines FXtp, FXb connected to the sub word driver SWD shown in FIG. 16 and driving the main word lines MWLbp, MWLbn, respectively.
The common word driver FXD that drives n is shown below.

First, FIG. 18 shows a main word driver MWD.
Is shown. As described in the operation shown in FIG. 17, in the third embodiment, since the common word driver performs control according to the read operation and the write operation, the read / write control circuit is not required in the main word driver. Therefore, the main word driver MWD is constituted by the level shift circuits LSCH and LSCL which independently drive the main word lines MWLbp and MWLbn. That is, the decode signal axj is transferred to the level shift circuit L
Input to SCH and LSCL, and output each to main word line M
WLbp and MWLbn. Decode signal axj is power supply voltage VD
The main word line MWLbp, which is selected by going to L and has the write potential VW, is connected to the ground potential VSS and the power supply voltage VD
The L main word lines MWLbn are driven to the standby potential -VB.

FIG. 19 shows the common word driver FXD. Level shift circuits LSCHRW and LSCL for independently driving the common word lines FXtp and FXbn and the read / write voltage control circuit VRWCC4
And common word driver for inverter circuits NV1 and NV2
FXD is configured. The read / write voltage control circuit VRWCC4 includes the level shift circuit LSCH and the voltage switching circuits VSW1 and VSW2 described in the first embodiment. Read control signal φr
From the inverter circuit NV1 to the level shift circuit LSCH, and the output of the level shift circuit LSCH is used as the read control signal φR. Therefore, the voltage amplitude is changed from the ground potential VSS to the read control signal φr of the power supply voltage VDL.
Is a read control signal ΦR having a voltage amplitude from the ground potential VSS to the write potential VW. The voltage switching circuit VSW1 includes a PMOS transistor Mp1 and an NMOS transistor Mn1.
The read control signal ΦR is connected to the gates of the transistors Mp1 and Mn1, and the write potential is applied to the source of the transistor Mp1.
VW is input to the source of the transistor Mn1 at the read potential VR. The drains of the transistors Mp1 and Mn1 are set to the read / write voltage VRW.

The voltage switching circuit VSW2 includes a PMOS transistor Mp1 and an NMOS transistor Mn1. The read control signal φr is connected to the gates of the transistors Mp1 and Mn1, and the source of the transistor Mp1 is connected to the power supply voltage VDL.
And the read potential VR is input to the source of the transistor Mn1. The drains of the transistors Mp1 and Mn1 are set to the cut-off voltage VRDL. The level shift circuit LSCHRW is different from the level shift circuit LSCH described in the first embodiment in that the read / write voltage VRW is input to the sources of the PMOS transistors Mp1 and Mp2, and the cutoff voltage VR is applied to the NMOS transistor Mn2.
The difference is that the DL is entered. In the level shift circuit LSCHRW having such a configuration, the decode signal aj is connected to the gate of the transistor Mn1 and the source of the transistor Mn2, and the drains of the transistors Mp1 and Mn1 and the gate of the transistor Mp2 are used as a common word line FXtp. Further, the inverted decode signal ajb from the decode signal via the inverter circuit NV2 is input to the level shift circuit LSCL, and the output is used as the common word line FXbn.

A common word driver FX using the above configuration
D is selected when the decode signal aj becomes the ground potential VSS. First, when the read control signal φr at the ground potential VSS is driven to the power supply voltage level VDL to perform a read operation, this signal is input to the voltage switching circuit VSW2, so that the transistor Mn1 conducts and the power supply voltage VDL Is driven to the read potential VR.
Further, since the read control signal ΦR is at the write potential VW, the read / write voltage VRW at the write potential VW is driven to the read potential VR. Therefore, the level shift circuit LS
In the CHRW, the decode signal aj of the ground potential VSS, the read / write voltage VRW of the read potential VR, and the cut-off voltage VRDL are input, so that the transistors Mn1 and Mp2 are cut off, the transistors Mn2 and Mp1 are turned on, and the ground potential
The common word line FXtp which is VSS is driven to the read potential VR. Further, the power supply voltage VDL is input to the level shift circuit LSCL, and the common word line FXbn, which is at the power supply voltage VDL, is driven to the standby potential -VB. Next, the power supply voltage VDL
When the read control signal φr is driven to the ground potential VSS to perform a write operation, this signal is input to the voltage switching circuit VSW2, so that the transistor Mp1 conducts and the cutoff voltage at the read potential VR Drive VRDL to power supply voltage VDL. Further, since the read control signal ΦR at the write potential VW becomes the ground potential VSS, the read / write voltage VRW at the read potential VR is changed to the write potential VW.
Drive to W. Therefore, in the level shift circuit LSCHRW, the decode signal aj of the ground potential VSS, the read / write voltage VRW of the write potential VW, and the cutoff voltage VRDL of the power supply voltage VDL are input, so that the transistors Mn1 and Mp2 are cut off, and the transistors Mn2, The common word line FXtp, which is the read potential VR when the Mp1 conducts, is set to the write potential
Drive to VW. Also, the level shift circuit LSCL receives the inverted decode signal ajb of the power supply voltage VDL, and holds the common word line FXbn at the standby potential -VB.

On the other hand, the operation of the level shift circuit LSCHRW in the non-selected state is different from that of the level shift circuit LSCH for switching the read / write voltage VRW. That is, in the non-selected state, the decode signal aj of the power supply voltage VDL is input, the transistor Mn1 is turned on, and the common word line FXtp is connected to the ground potential.
Drive to VSS. Here, in the write operation and the standby state, since the read / write voltage VRW of the write potential VW and the cut-off voltage VRDL of the power supply voltage VDL are input, the transistor Mp2 is turned on, and the transistor Mp1 is cut off. Then, since the read / write voltage VRW of the write potential VW is input to the drain of the transistor Mn2, the transistor Mn2 is cut off, and the transistor Mp2
Through current is cut off. Further, in the read operation, since the read / write voltage VRW and the cutoff voltage VRDL of the read potential VR are input, the transistor Mp2 is turned on, and the transistor Mp1 is cut off. Then, since the read / write voltage VRW of the read potential VR is input to the drain of the transistor Mn2, the transistor Mn2 is cut off, and the through current via the transistor Mp2 is cut off.

As described above, the common word driver of this embodiment shown in FIG. 19 is characterized in that the common word line is driven to a ternary potential. Specifically, the voltage is controlled by the read / write voltage control circuit VRWCC4 to a voltage corresponding to the read / write operation. Also, in order to prevent a through current from flowing through the level shift circuit LSCHRW, a feature is that the cutoff voltage VRDL is switched in accordance with the switching of the voltage.

In the voltage setting example suitable for the capacitively coupled two-transistor cell DRAM shown in FIG. 6, if the read potential VR is sufficiently higher than the threshold voltage of the transistor Mn2 and the driving capability of the transistor Mn2 is sufficiently high, the cut-off voltage VR
DL may be fixed to the read potential VR. Further, in the voltage switching circuit VSW1, the read / write voltage VR is set via the transistors Mp1 and Mn1 having different WELL structures.
Since W is driven to two different positive voltages, it is possible to prevent the occurrence of latch-up when the power is turned on, and to reliably generate the writing potential VW higher than the power supply voltage VDL.

The sub-word driver shown in FIG. 16 will be summarized. By using the common word driver FXD shown in FIG. 19, the sub-word driver outputting the ternary voltage shown in FIG. 16 can be constituted by five MOS transistors. In addition, since it can be configured with two main word lines and two common word lines, the circuit configuration of this portion is simplified, and an increase in area can be suppressed. When a voltage setting example suitable for the capacitively coupled two-transistor cell DRAM shown in FIG. 6 is applied, the problem of the withstand voltage in the gate oxide film can be solved by using the circuit shown in this embodiment. Can be easily understood from the description. Alternatively, in the circuit shown in this embodiment, the method of using n + Si gates for the PMOS transistors Mp1 and Mp2 described in the first embodiment, or the main word line signal and the common word line signal to be level-shifted are appropriately applied. It is possible to apply a method of setting a proper voltage amplitude. Also, the electric field relaxation MOS transistor Mp
2. The constant voltage level applied to the gate of Mn5 is not limited to one as in the first embodiment, but may be a pulse having an appropriate voltage amplitude. Further, as described in the second embodiment, between the gate and the source and between the gate and the source of each MOS transistor.
The electric field in the gate oxide film between the drains is the maximum electric field Eox
If the value does not exceed max, a circuit configuration without the electric field relaxation MOS transistor from which the transistors Mp2 and Mn5 are removed can be adopted. When the electric field in the gate oxide film is sufficiently small, the main word lines MWLbp and MWL shown in FIG.
Since bn can be shared, driving the seven-word driver with one main word line can suppress an increase in the circuit area of this part. Further, FIG.
In the common word driver shown in FIG. 9, the method of controlling the common word line using the write control signal φwb instead of the read control signal φr as described in the first embodiment can be applied.

<Fourth Embodiment> FIG. 20 shows a further example of the configuration of a sub-word driver.

The sub-word driver SWD of this example is different from the sub-word driver shown in FIG. 16 in that the source electrode of the NMOS transistor Mn2 is connected to the common word line FXtn without connecting to the standby potential -VB. . The main word line signal is separately provided for the PMOS transistor Mp1 and the NMOS transistor Mn1, and the main word line MWLbp is connected to the gate of the PMOS transistor Mp1 and the main word line MWLbn is connected to the gate of the NMOS transistor Mn1. The main word line MWLtn is connected to the gate of the NMOS transistor Mn2. The common word line is also separated for the PMOS transistor Mp1 and the NMOS transistor Mn2, and the common word line FXtp is connected to the source of the PMOS transistor and the common word line FXtn is connected to the source of the NMOS transistor Mn2. NMOS transistor Mn
1 is connected to the standby potential -VB. The PMOS transistor Mp2 and the NMOS transistor Mn5 are MOS transistors for alleviating the electric field, and apply a fixed voltage to the gate electrode. FIG.
0 indicates an example in which the ground potential VSS and the power supply voltage VDL are respectively applied. Further, the sub-word line SWL is connected to the drains of the transistors Mp2, Mn2, and Mn5. With such a circuit configuration, the problem of withstand voltage of the gate oxide film can be solved, and a sub-word driver can be configured with three main word lines, two common word lines, and five MOS transistors. The feature is that the potential of the common word line Fxtp connected to the source of the PMOS transistor Mp1 is controlled according to the read operation and the write operation in order to generate a ternary word line voltage.

Incidentally, even if a circuit is constructed without using the transponders Mp2 and MN5, the object can be sufficiently achieved.

The operation of sub-word driver SWD of FIG. 20 will be described with reference to FIG. In the figure, the sub word line SWL1
11 shows a case in which the reading operation and the writing operation are continuously performed from the standby state. The operation different from the first embodiment is, for example, a main word driver.
The word driver selected like MWD1 is used for the main word line in both read and write operations.
In this operation, MWLbp, MWLbn, and MWLtn are driven to the ground level VSS, the standby potential -VB, and the power supply voltage VDL, respectively. The main word driver MWD1 connects the main word line MWL1bp having the write potential VW to the ground potential VSS and the power supply voltage VDL.
The main word line MWL1tn is set to the standby potential -VB, and the main word line MWL1tn is set to the standby potential -VB.
Drive to VDL respectively. In this state, first, the ground potential V
When the read control signal φr, which is SS, is driven by the power supply voltage VDL to perform a read operation, the common word driver FX
D11 reads the common word lines FX11tp and FX11tn which are at the ground potential VSS and the standby potential -VB, respectively, and
Drive. Therefore, the main word lines MWL1bp and MWL1bn
And MWL1tn are driven to ground potential VSS, standby potential -VB and power supply voltage VDL, respectively, and common word lines FX11tp, F11tp
When X11tn is driven to the read potential VR, the transistor Mn1 is cut off, the transistors Mp1 and Mp2 are turned on, and the sub-word driver SWD is turned on.
111 is selected, and the sub-word line SWL111 having the standby potential -VB is driven to the read potential VR.

Next, when the read control signal φr at the power supply voltage VDL is driven to the ground potential VSS to enter the write state, the common word driver FXD11 outputs the read potential VR.
Is driven to the write potential VW, and FX11tn is driven to the power supply voltage VDL. Therefore,
The main word lines MWL1bp, MWL1bn, and MWL1tn are maintained while being driven by the ground potential VSS, the standby potential -VB, and the power supply voltage VDL, respectively, and the common word lines FX11tp, FX11
When tn is driven to the write potential VW and the power supply voltage VDL, respectively, the transistors Mn1 and Mn2 are cut off, the transistor Mp1 is turned on, the sub-word driver SWD111 is selected, and the sub-word line SWL111 is at the read potential VR. To the write potential VW.

A main word driver MWD for driving main word lines MWLbp, MWLbn and MWLtn connected to the sub word driver shown in FIG.
About the common word driver FXD that drives Xtp and FXtn
It is shown below.

First, FIG. 22 shows an example of the main word driver. As described in the operation shown in FIG. 21, in the fourth embodiment, since the common word driver performs control according to the read operation and the write operation, the read / write control circuit is not required in the main word driver. Therefore, the main word driver MWD is composed of the level shift circuits LSCH and LSCL for independently driving the main word lines MWLbp and MWLbn, and the inverter circuit NVL for driving the main word lines MWLtn. That is, the decode signal axj is transferred to the level shift circuit L
Input to SCH and LSCL, and output each to main word line M
WLbp and MWLbn. Further, the main word line MWLbn is connected to the inverter circuit NVL, and the output thereof is used as the main word line MWLtn. The decode signal axj is selected by the power supply voltage VDL, and the main word line MWLbp, which is the write potential VW, is set to the ground potential VSS, and the main word line MWLbn, which is the power supply voltage VDL, is set to the standby potential -VB. potential
The main word lines MWLtn which are set to -VB are each driven to the power supply voltage VDL.

FIG. 23 shows the common word driver FXD. Level shift circuits LSCHRW, LSCLR and read / write voltage control circuit VRWCC5 for independently driving the common word lines FXtp, FXtn
And the inverter circuit NV1 constitute a common word driver FXD. The difference from the common word driver of the third embodiment shown in FIG. 19 is that the inverter circuit NVL2 is removed because the common word line FXnt has the opposite polarity to the polarity of the common word line FXnb, and the decode signal aj remains unchanged. That is, it is input to the level shift circuit LSCLR. The level shift circuit LSCLR is different from the level shift circuit LSCL described in the first embodiment in that the transistor Mp1
Are different in that the cut-off potential VRDL is input to the source of the control signal. Therefore, such a common word driver FXD is selected by the decode signal aj being at the ground potential VSS, and drives the common word line FXnt, which is at the standby potential -VB, to the read potential VR in the read operation to perform the write operation. In operation, it is driven to the power supply voltage VDL. Common word line FXtp
Are the same as those of the common word driver according to the third embodiment shown in FIG.

Therefore, the common word driver of the present embodiment shown in FIG. 23 is similar to the common word driver of the third embodiment shown in FIG.
The feature is that the common word line FXtp is driven to a ternary potential while switching the cut-off voltage VRDL according to the switching of the voltage in order to prevent a through current from flowing through the CHRW. In addition, in order to control the transistor Mn2 in the sub-word driver, a feature is that the common word line FXtn is driven to a ternary potential, ie, a standby potential -VB, a read potential VR, and a power supply voltage VDL. In the voltage setting example suitable for the capacitively coupled two-transistor cell DRAM shown in FIG. 6, when the read potential VR is sufficiently higher than the threshold voltage of the transistor Mn2 and the driving capability of the transistor Mn2 is sufficiently high, the level shift circuit LSCHRW Transistor Mn2
May be fixed to the read potential VR. Further, in the voltage switching circuit VSW1, the read / write voltage VRW is driven to two different positive voltages via the transistors Mp1 and Mn1 having different WELL structures. A write potential VW higher than VDL can be reliably generated.

The sub-word driver shown in FIG. 20 will be summarized. By using the common word driver FXD shown in FIG. 23, the sub-word driver that outputs the ternary voltage shown in FIG. 20 can be composed of five MOS transistors. In addition, since it can be configured with three main word lines and two common word lines, the circuit configuration of this portion is simplified, and an increase in area can be suppressed.

When the preferred voltage setting example is applied to the capacitively-coupled two-transistor cell DRAM shown in FIG. 6, the problem of the withstand voltage in the gate oxide film can be solved by using the circuit shown in this embodiment. It can be easily understood from the description of the first embodiment. Alternatively, the circuit shown in the present embodiment also includes the PMOS transistor Mp described in the first embodiment.
1. A method using an n + Si gate for Mp2 or a method of setting a main word line signal and a common word line signal to be level-shifted to appropriate voltage amplitudes can be applied. The constant voltage level applied to the gates of the electric field relaxation MOS transistors Mp2 and Mn5 is not limited to one as in the first embodiment, but may be a pulse having an appropriate voltage amplitude. Further, as described in the second embodiment, when the electric field in the gate oxide film between the gate and the source and between the gate and the drain of each MOS transistor does not exceed the maximum electric field Eox max,
It is also possible to adopt a circuit configuration without the electric field relaxation MOS transistor from which the transistors Mp2 and Mn5 are removed. When the electric field in the gate oxide film is sufficiently small, the main word lines MWLbp and MWLbn shown in FIG. 20 can be shared, so that the sub-word driver is driven by two main word lines and two common word lines. Accordingly, an increase in the circuit area of this portion can be suppressed. Further, FIG.
In the common word driver described in (1), the method of controlling the common word line using the write control signal φwb instead of the read control signal φr as described in the first embodiment can be applied.

Although the present invention has been described with reference to various embodiments, the configuration according to the present invention is not limited to these, and similar effects can be obtained in various modifications and applications. For example, although the case where the present invention is applied to a hierarchical word line structure has been described, the present invention can also be applied to a normal word line structure in which a word driver is directly controlled by a row decoder. In addition, the present invention has been described in connection with the case where the capacitively coupled two-transistor cell shown in FIG. 5 is applied to the hierarchical word line structure shown in FIG. 7, but as represented by the three-transistor cell shown in FIG. Also, when a memory cell that controls read / write operations with a ternary word line voltage is applied to a hierarchical word line structure, the voltage applied to the gate oxide film of each MOS transistor in each circuit is sufficiently reduced. Variations and applications of the present invention are possible to drive the selected sub-word line to a ternary potential.

In addition, the reading transistor QR
Although the case where the threshold voltage VTR is lower than the threshold voltage VTW of the write transistor QW has been described, even when the relationship between the threshold voltage VTR of the read transistor QR and the threshold voltage VTW of the write transistor QW is interchanged. It is clear that a similar argument holds. In this case, the read / write operation of the memory cell can be performed by appropriately controlling the data line separately for read and write, and setting the read potential to VW and the write potential to VR. At this time, a sub-word driver, a main word driver, and a common word driver for driving a sub-word line to a read potential and a write potential while appropriately controlling the read / write control circuits described in the various embodiments may be formed.

Further, the case where the memory cell is formed by using the NMOS transistor has been described so far. However, it is apparent that the same discussion is valid when the memory cell is formed by using the PMOS transistor. In such a case, the PMOS and NMOS are replaced by a sub-word driver, etc., and the power supply relationship between the power supply, main word line and common word line is reversed so that the voltage of the unselected sub-word line is higher than that of the high-level data line. What is necessary is just to set the voltage of the sub-word line lower than the low level of the data line.

[0142]

The present invention alleviates the problem of withstand voltage in the MOS transistor, and realizes a DRAM in which the read / write operation is controlled by a ternary word line voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a sub-word driver that generates a ternary voltage level.

FIG. 2 is a diagram illustrating an example of a memory cell including three transistors.

FIG. 3 is a diagram illustrating an example of a memory cell including two transistors and one capacitor.

FIG. 4 is a diagram showing a circuit configuration of a conventional sub-word driver.

FIG. 5 is a diagram showing operation timing of a conventional sub-word driver.

FIG. 6 is a diagram showing a voltage setting example suitable for a capacitively coupled two-transistor cell DRAM.

FIG. 7 is a diagram schematically showing a hierarchical word line configuration according to the first embodiment;

FIG. 8 is a diagram showing operation timings of a sub-word driver that generates a ternary voltage level.

FIG. 9 is a diagram illustrating a configuration example of a circuit of a main word driver according to the first embodiment;

FIG. 10 is a diagram illustrating a configuration example of a circuit of a common word driver.

FIG. 11 is a diagram showing an example of a configuration of a memory cell array.

FIG. 12 is an operation timing chart of a memory cell including two transistors and one capacitor.

FIG. 13 is a diagram showing a configuration example of a sub-word driver for generating a ternary voltage level according to the second embodiment;

FIG. 14 is a diagram showing a configuration example of a circuit of a common word driver according to a second embodiment.

FIG. 15 is a diagram showing operation timings of a sub-word driver for generating a ternary voltage level according to the second embodiment.

FIG. 16 is a diagram illustrating a configuration example of a sub-word driver that generates a ternary voltage level according to the third embodiment;

FIG. 17 is a diagram showing operation timings of a sub-word driver for generating ternary voltage levels according to the third embodiment.

FIG. 18 is a diagram illustrating a configuration example of a circuit of a main word driver according to a third embodiment;

FIG. 19 is a diagram illustrating a configuration example of a circuit of a common word driver according to the third embodiment;

FIG. 20 is a diagram showing a configuration example of a sub-word driver for generating a ternary voltage level according to the fourth embodiment.

FIG. 21 is a diagram showing operation timings of a sub-word driver for generating ternary voltage levels according to the fourth embodiment.

FIG. 22 is a diagram illustrating a configuration example of a circuit of a main word driver according to a fourth embodiment;

FIG. 23 is a diagram illustrating a configuration example of a circuit of a common word driver according to a fourth embodiment;

[Explanation of symbols]

MWLbp, MWLbn, MWLRtn, MWLb, MWLtn: Main word line, FXtp, FXtn, FXbn, FXRtn: Common word line, VW: Write potential, VR: Read potential, -VB: Standby potential, VDL ...
Power supply voltage, VSS: ground potential, Mp1, Mp2: MOS transistor, Mn1, Mn2, Mn3, Mn4, Mn5: MOS transistor, SWL, SWL111, SWL112: sub word line, WL ...
Word line, DL, DL1, DL2: Data line, QW: For writing
NMOS transistor, QR: NMOS transistor for reading,
QN: NMOS transistor for holding charge, MC: memory cell, SW
D, SWD111, SWD112 ... sub word driver, MWD,
MWD1, MWD2: Main word driver, FXD, FXD11,
FXD12: Common word driver, RWC11, RWC12: Read / write circuit, FXDA1, FXDA2: Common word driver array, SWDA11, SWDA12: Subword driver array,
NCA11, MCA12: Memory cell array, RWCA1, RWCA2
... Read / write circuit array, NV1, NV2, NVL, NVL1 ... Inverter circuit, NR1 ... NOR circuit, ND1 ... AND circuit, aj, aj
b, axj, axjr11, axjr12... decode signal, φr, φR
... Read control signal, φw ... Write control signal, LSCH, L
SCL, LSCL1, LSCL2, LSCHRW, LSCLR: Level shift circuit, RWCC1, RWCC2: Read / write control circuit, VRWCC, VRWCC
4, VRWCC5 ... Read / write voltage control circuit, VSW1, VSW2 ...
Voltage switching circuit, VRW: read / write voltage, VRDL: cutoff voltage.

Claims (16)

[Claims] A plurality of word lines; a plurality of data lines intersecting the plurality of word lines; and a plurality of memory cells arranged at desired intersections between the plurality of word lines and the plurality of data lines. A plurality of word drivers provided corresponding to each of the plurality of word lines, wherein each of the plurality of word drivers has a first voltage supplied to one of a drain and a source. A first conductivity type MOSFET, a second conductivity type first MOSFET to which a second voltage is applied to one of a drain and a source, and a second conductivity type first MOSFET to which the second voltage is applied to one of a drain or a source. A second MOSFET, a second MOSFET of a second conductivity type to which a third voltage is applied to one of a drain and a source, and a drain or a source of the third MOSFET of the second conductivity type. And a one second conductivity type second 4MOSFET which one is connected to each of said plurality of word drivers, corresponding said word line first
A semiconductor device driven to one selected from a voltage, the second voltage, and the third voltage; 2. The device according to claim 1, wherein each of the plurality of word drivers outputs the first voltage to the corresponding word line when the first MOSFET of the first conductivity type is turned on, and outputs the first voltage to the corresponding word line. A semiconductor device that outputs the third voltage to the corresponding word line when the third MOSFET is turned on, and outputs the second voltage to the corresponding word line when the second conductivity type first MOSFET is turned on. 3. The first electric field buffer according to claim 1, wherein each of the plurality of word drivers is inserted between a remaining one of a drain or a source of the first conductivity type first MOSFET and the corresponding word line. MOSFET
And a second MOSFET for alleviating electric field inserted between the remaining one of the drain or source of the first MOSFET of the second conductivity type and the corresponding word line. 4. The third conductive type third MO according to claim 1, wherein
A semiconductor device to which the third voltage is supplied to one of a source and a drain of an SFET during both a period in which the plurality of word drivers select the corresponding word line and a non-selection period. 5. The semiconductor device according to claim 1, further comprising a selection circuit for selecting one of the plurality of word drivers, wherein one of a source and a drain of the second conductivity type third MOSFET is provided. A semiconductor device to which the third voltage is supplied from the selection circuit. 6. A plurality of word lines, a plurality of data lines intersecting with the plurality of word lines, a plurality of memory cells arranged at desired intersections with the plurality of word lines and the plurality of data lines, A plurality of word drivers for driving the plurality of word lines, wherein each of the plurality of word drivers has a drain or a source in a first period during a first period.
A first conductivity type first MOSFET to which a voltage is supplied and a third voltage to be supplied during a second period; a second conductivity type first MOSFET to which a second voltage is applied to one of a drain and a source; A second conductivity type second MOSFET having a period in which the second voltage is supplied to one of the sources, wherein each of the plurality of word drivers sets a corresponding word line to the first voltage and the second voltage. A semiconductor device driven to one selected from a voltage and the third voltage. 7. The word driver according to claim 6, wherein each of the plurality of word drivers outputs the first voltage to a corresponding word line when the first conductivity type first MOSFET conducts during the first period. , During the second period,
When the first MOSFET of the first conductivity type is turned on, the third voltage is output to a corresponding word line, and the first MOSFET of the second conductivity type is output.
A semiconductor device that outputs the second voltage to a corresponding word line when the ET conducts. 8. The first electric field relaxation device according to claim 6, wherein each of the plurality of word drivers is inserted between a remaining one of a drain and a source of the first conductivity type first MOSFET and the corresponding word line. MOSFET
And a second electric field relaxation MOSFET inserted between the remaining one of the drain and the source of the second conductivity type first MOSFET and the corresponding word line. 9. The semiconductor device according to claim 1, wherein the first voltage is higher than the third voltage, and the third voltage is higher than the second voltage. 10. The method according to claim 3, wherein the first voltage is higher than the third voltage, and the third voltage is higher than the second voltage.
The first electric field relaxation MOSFET has a first conductivity type, and a voltage between the second voltage and the third voltage is applied to a gate of the first electric field relaxation MOSFET. A semiconductor device in which a MOSFET has a second conductivity type, and a voltage between the first voltage and the third voltage is applied to a gate of the MOSFET. 11. The method according to claim 6, wherein said first voltage is higher than said third voltage, and said third voltage is higher than said second voltage.
A semiconductor device whose voltage is higher than the voltage. 12. The memory cell according to claim 1, wherein when the corresponding word line is at a first voltage, a write operation is performed on the corresponding memory cell, and when the corresponding word line is at a second voltage, the write operation of the corresponding memory cell is performed. A semiconductor device which is in a data holding state and performs a read operation on a corresponding memory cell when the corresponding word line is at a third voltage. 13. The memory cell according to claim 1, wherein each of the plurality of memory cells has an eleventh MOSFET having a gate connected to a corresponding word line and one of a source and a drain connected to a corresponding data line, and a gate connected to an eleventh MOSFET. A twelfth MO connected to the other of the source and the drain of the eleventh MOSFET
An SFET and a thirteenth MOS transistor having a gate connected to the corresponding word line and one of a source and a drain connected to one of a source and a drain of the twelfth MOSFET.
A semiconductor device which is a dynamic memory cell including an SFET. 14. An eleventh MOSFET according to claim 1, wherein each of said plurality of memory cells has an eleventh MOSFET having a gate connected to a corresponding word line and one of a source and a drain connected to a corresponding data line. An electrode has a coupling capacitance connected to the corresponding word line, and a gate has the eleventh MO.
A semiconductor device which is a dynamic memory cell including a drain or a source of an SFET and a twelfth MOSFET connected to the other electrode of the coupling capacitor. 15. The semiconductor device according to claim 1, wherein the first conductivity type is P
And the second conductivity type is an N-type. 16. The semiconductor device according to claim 6, wherein said first conductivity type is P
And the second conductivity type is an N-type.