JP2001195301A - Updating circuit for pipeline cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the contention of the updating processing of data and an access processing from a succeeding thread at the time of a cache mishit and to prevent the disturbance of a pipeline operation. SOLUTION: This circuit is provided with a first pipeline latch (20) to be the interface of a processor (1) and a cache memory (2), a second pipeline latch (21) arranged in an intermediate stage for constituting a pipeline and an external block buffer (110) to be the interface of a main memory and the cache memory. The first pipeline latch is provided with fields (50) and (54) for displaying a thread identifier and the field for displaying a thread state and the external block buffer is provided with the field for displaying the thread identifier, a block address and an intra-set block number. Then, a comparator circuit (18) for judging by comparing the thread identifier displayed by the first pipeline latch with the thread identifier displayed by the external block buffer is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an updating circuit for a data block when a cache memory has a mishit, and more particularly to an updating circuit in a cache having a pipeline structure.

[0002]

2. Description of the Related Art Since a memory system of a computer needs to satisfy three requirements of a large capacity, a high speed and a low price, it is impossible to realize all of the memory system with one kind of memory. For this reason, a memory system in which a plurality of memories having different capacities and speeds are hierarchically combined is employed.

[0003] The cache memory is a high-speed, small-capacity memory arranged between the processor and the main memory to bridge the speed difference between the processor and the main memory. By utilizing the locality of the program, recently used instructions or data are stored to improve the memory access performance.

[0004] For this reason, the first problem is that an ordinary cache memory has a short access time, and the adoption of a pipeline structure is not actively performed. At most, a two-stage pipeline configuration of an address decode and a memory array body is employed.

[0005] However, in the case of a cache memory targeting a special architecture such as a multi-thread processor, not the access time but the throughput may become a problem. That is, although the latency (time delay) may be large, it is important to read out data in a cycle time as short as possible. In such a processor, a pipeline structure is essentially suitable.

For example, in a multi-thread processor, an access request to a cache memory is a request from a different thread every cycle, and there is a margin in the access time of the request. can do.

However, in a cache having a pipeline configuration, there is no problem when a cache access is a hit. However, when a cache hit occurs, an update (update) process of a cache entry and an access process from a subsequent thread are performed in parallel. Therefore, there is a problem in that access to the main memory array competes to disrupt the pipeline operation, thereby lowering the throughput.

[0008]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems that occur when a pipeline structure is applied to a cache memory, and includes a cache entry update process at the time of a cache mishit;
Avoid conflicts with access processing from subsequent threads,
It is an object of the present invention to prevent disturbance of pipeline operation and prevent a decrease in throughput.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for executing pipeline processing in a plurality of stages with respect to a plurality of threads required between a processor and a main memory. A pipelined cache memory, a first pipeline latch serving as an interface between the processor and the cache memory, a second pipeline latch disposed in an intermediate stage forming the pipeline, and the main memory And an external block buffer serving as an interface with the cache memory, wherein the first pipeline latch includes a thread identifier for identifying a thread to be processed and a field indicating a status of the thread, Pipeline latches are processed in this stage. A field indicating a thread identifier, the external block buffer includes fields indicating a thread identifier, a block address, and a block number in a set corresponding to the block, and a thread indicating the first pipeline latch. A cache memory update circuit comprising a comparison circuit for comparing and determining whether an identifier matches a thread identifier displayed by the external block buffer.

According to the present invention, the cache memory can be a set associative cache memory, and the field indicating the state of the thread is inactive when the cache memory has a mishit with respect to the corresponding thread. Is displayed, and when the comparison circuit determines that they match, it is possible to execute a data update process for a corresponding thread under the control of the processor.

Further, according to the present invention, it is possible to provide a random generator for selecting a block number in a set at the time of updating data, and the first pipeline latch and the second pipeline latch can read data. It is possible to connect to the next stage via each decoder for decoding the address of the requested data.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In the present invention, the pipeline latches (registers for holding the information of the pipeline stages) 20, 21, 22, and 23 of the cache memory 2 include:
A field 50 for storing a thread identifier together with the address fields 15 to 17 and the data field 13.
And a field 54 for displaying the state of the thread (active or inactive).

By providing the field 54 for displaying the state of such a thread, it is displayed whether the thread is a hit thread or a miss-hit thread, and it is known that the thread is a miss-hit. And, even in the case of a mishit, each processing of the thread having a mishit is aborted at each stage of the pipeline. Line processing continues.

On the other hand, for a thread having a mishit, the data for updating is read from the main memory 3 and the external block buffer 11 is read out together with the identifier of the thread.
Store to 0. The mishit update processing is performed on data read from the main memory 3 for data update and stored in the external block buffer 110 by comparison by a comparator, that is, a comparison circuit 18 disposed at the entrance of the cache unit. The thread identifier 29 is compared with the thread identifier 14 that is continuously processed in the pipeline. Only when the two thread identifiers match as a result of the comparison, the process is continuously performed without disturbing the process of another thread by using the pipeline cycle (called an empty cycle) for the suspended thread. Update processing is performed.

That is, the external block buffer 11
Since the corresponding address is stored in 0, the address is accessed by this address, and the contents of the tag memory arrays 31 to 34 and the corresponding data memory arrays 41 to 44 which have previously missed by the data stored in the data field 49 are stored. The data of the data block is updated.

The pipeline cache 2 shown in FIG.
Address decoders 11 and 12 configured in multiple stages and pipeline latches 20 inserted in each stage of the pipeline,
21, 22, and 23. The pipeline latch 20 serves as an interface between the processor 1 and the cache memory 2, and the pipeline latches 21, 22, and 23 are arranged in each intermediate stage forming the pipeline.

The pipeline cache further includes a plurality of tag memory arrays 31, 32, 33, and 34, and a plurality of data memory arrays 41, 42, 43, and 44.
And a plurality of comparators 35 and 36 for performing tag comparison, and a plurality of internal read block buffer data fields 6
1 and 62, and a processor bus 7 of one word width.
, A main memory bus 8 having a block size width, a random generator 9 for selecting a block, and an external read block buffer 100, 110 and a comparator 18 which is a circuit for judging a match between thread identifiers.

The pipeline latches 20, 21, 2
2, 23, the internal block buffer 24 and the external block buffers 100 and 110 have data fields 1
3, 46, 49 and the address field (15, 1
6, 17), (26, 27, 28), 48, and 51 are provided. At the same time, a thread number for identifying each thread, that is, a thread identifier (eg, 211, 2 in FIG. 1)
21, 231, 241, 251, 101 and 111 are indicated by thread numbers. ) To store field 5
0, 51, 52, and 53 are provided, and a field 54 is provided to indicate an empty cycle in the case of a mishit.

When the capacity of the data memory arrays 41 to 44 increases, it is naturally conceivable to increase the number of decoding stages and the number of pipeline stages. Thread numbers 211, 221, 231, 241, and 251 in FIG. 1 indicate that the processes related to the displayed threads are being performed in parallel at a certain stage of the pipeline at a certain point in time. Although FIG. 1 shows an example of the set associative cache memory, the present invention is not limited to the set associative cache memory.

In the embodiment shown in FIG. 1, the external block buffer 110 is also provided with an address field for storing a block address. For this reason, there is no need to provide a place in the cache memory 2 for storing the address of the block requested to be input (read) as in a normal cache memory. That is, along with the read request, the main memory 3
, And the address is returned to the cache memory 2 together with the update data. Therefore, the cache memory is kept in a wait state until the response to the main memory is returned, and the address is held. No need. Therefore, pipeline processing for each thread can be continuously executed. Further, the address field is provided with a field for storing a block number in a set, corresponding to the adoption of the set associative system.

NAND circuit 3 which is a hit / mis determination circuit
7, and this circuit 37 includes tag memory arrays 31 to 34.
Of the outputs of the two comparators 35 and 36 at the output side of
AND. Therefore, if both comparators output a mismatch, the entry does not exist (miss). The field 38 of the latch connected to the NAND circuit 37 stores this hit / mis determination result, and the field 39 stores the comparison result of both comparators 35 and 36.

The result of the hit / mis determination is returned to the processor via a path connected to the processor 1 (not shown). The processor 1 stores the determination result in its own memory (not shown) in association with each thread identifier in, for example, a table format. For a thread for which a mistake has been determined, the thread identifier is displayed together with an indication that it is a free cycle. To the cache memory 2, which are stored in the pipeline latch 20.

As shown in FIG. 2A, the processor 1 and the cache memory 2 are connected by a one-word-width processor bus. The cache memory 2 and the main memory 3 are connected by a main memory bus of one block width.
FIG. 2B shows the structure of data passing through the processor bus 7.
FIG. 2C shows a configuration of data passing through the main memory bus 8.

In the embodiment shown in FIG. 1, the total number of pipeline stages is five, the number of pipeline stages for address decoding is two, and the degree of associativity of set associative is two.
Although the number of the comparators 35 and 36 of the tag is 2, it is generally possible to increase the number of pipeline stages or increase the degree of association. The term "set" means a set of tags and data blocks, each of which corresponds to the number of associations.

Hereinafter, (a) a read operation at the time of a hit, (b) a read operation at the time of a mishit,
(C) Write operation (when hit) and (d)
The operation of this embodiment will be described separately for a write operation (at the time of a mishit).

(A) Read Operation at Hit First, a normal read operation will be described. Upon receiving a read request from the processor 1, the pipeline latch 20
, Along with the thread identifier 211, passes through the address decoder 11, the pipeline latch 21, the address decoder 12, and the pipeline latch 22, and reaches the tag memory arrays 31 to 34.

The lower address (16,
17 is decoded by the address decoders 11 and 12, respectively. That is, in the present embodiment, as shown in FIG. 1, the decoder is divided into a serially connected decoder 11 and a decoder 12 for performing hierarchical decoding and for the following reason. The logic of each decoder is the same as that of a normal decoder, and is to decompose ⁿ signals into 2 ⁿ (2 n) signals. That is, a decoder for decoding a lower address is formed by a plurality of decoders 11 and 12, while a lower field is distributed to a plurality of memory small arrays 16 and 17, where decoding is performed by respective decoders.

By dividing the fields of the lower address and decoding them hierarchically as described above, 1) the field length is shortened, the decoding time is shortened, and 2) the decoders are distributed and arranged in small arrays. By
Wiring delay can be reduced.

The lower addresses decoded by the decoders 11 and 12 determine the tag memory arrays 31-34.
The tag corresponding to the lower address is read from. The read tag is compared with the bit of the upper address and the comparator 35,
Compared at 36. If any one of these comparators determines “equal”, that is, a hit, the address latched in the pipeline latch 23
The data memory arrays 41 to 44 are accessed. When the access is completed, the data memory arrays 41 to 44 latch the read data in the data fields 61 and 62 of the internal block buffer 24 and transmit the data to the processor 1 through the processor bus 7.

The above operation is performed as shown in FIG.
(1) Address decoding 1 by decoder 11, (2)
Address decoding by the decoder 12, (3) tag reading, comparison of the tag with the upper address, (4) data reading by accessing the data memory arrays 41 to 44, and (5) access to the processor via the processor bus 7. Data transmission is performed by a total of five stages of pipeline processing. With such a configuration and operation, a new address is accepted every clock cycle, and cache data can be obtained continuously after each five clocks.

(B) Read operation at the time of a mishit The read operation at the time of a mishit is divided into detection of a mishit, selection of an updated block, write-back of a dirty block, reading of an updated block, and updating of a tag and a block. This will be described below.

B-1 Detection of Mishit First, the case where a mishit occurs during a read operation will be described. In this case, the process is the same up to the stage of the tag access and the comparison between the tag and the upper address in the pipeline processing (3).

When it is determined that the outputs of the comparators 35 and 36 are not equal to each other, that is, in the case of a mishit, in this case also, memory access is performed in the same manner as at the time of hit, and the read data is read together with the tag into the internal block buffer. 24
Are latched in the data fields 61 to 62 of. The data in this case is a pair of a tag and data read by the cache address (lower address).

The reading of the data memory arrays 41 to 44 is performed in exactly the same manner irrespective of a miss or a hit simply by determining a miss because the tags do not match. The read data is also sent to the processor 1 as it is, but the processor 1 discards the sent data because it has received the determination result of a mishit along with the thread identifier. The difference from the hit is that the processor 1 is notified of the mishit by a thread identifier.

The processor 1 determines the thread that has issued the mis-hit access request based on the thread identifier, and sets the corresponding thread to an idle cycle. That is, the thread that has become an empty cycle sends a thread identifier to the cache memory 2 together with an instruction that the cycle is an empty cycle. Upon receiving this instruction, for the corresponding thread, the field 54 of the pipeline latch 20 indicating the state of the thread (active or inactive) indicates that the thread is inactive.

When there is a pause indication indicating an empty cycle in the field 54, the cache memory 2 performs an actual access operation (address decoding by a decoder, tag access, and the access between the tag and the upper address) in each stage corresponding to this thread. Comparison, memory array access, and data transmission) are not performed. Processor 1
, An access request is issued to the cache memory 2 every cycle from a thread other than a thread in an empty cycle (particularly in the case of an instruction cache).

B-2 Selection of Update Block An entry that has become a miss hit needs to be updated. The update is performed using the idle cycle of the sleeping thread.

First, the data of the block to be updated is flushed to the main memory 3. In this case, it is necessary to select the block to be updated (block number in the set). In this selection, it is difficult to use a so-called LRU (least recently used) method for replacing a block that has been unused for the longest time, as in a selection in a normal cache memory.

The reason is that in the pipeline cache memory, there are operations in all stages every cycle. Further, each cycle, the tag memory arrays 31 to 34 and the data memory arrays 41 to 44 are accessed. Therefore, it is difficult to take time for updating the LRU stack, and a high-speed cycle time cannot be realized by the LRU method. For this reason, it is necessary to adopt an alternative to the LRU method.

In the present embodiment, a random algorithm is employed. Random algorithms perform relatively well. That is, selection of a block (block number within a set) is determined by the output of the random generator 9. The block number in the set is a number in which a pair of a tag and a data block constituting a set is numbered for a block selected to be evicted in the case of a cache miss. For example, in a cache memory having an associativity of 2 including n sets, the block number in the set is defined as 0 or 1.

In general, if the selected block (block number in the set) is A, the determination of A may be made in advance. That is, a value generated by the random generator 9 in advance may be obtained. Random generator 9
Operates to generate the next random number in preparation for the next request.

The block address indicating this block number is usually specified by the upper bits of the lower address, and the lower bits of the lower address select a word in the block.

B-3 Write Back of Dirty Block After the flush block is determined, it is necessary to actually write back the data in the selected flush block to the main memory. In other words, if the block is dirty (dirty; the contents of the cache where the writing has been performed do not match the contents of the main memory), the contents of the internal block buffer 24 storing the data of the eviction block are passed through the main memory bus 8. Is sent to the main memory 3 in one clock cycle.

The write address to the main memory 3 is stored in the address storage field 26 of the internal block buffer 24,
It can be generated from tags and lower addresses stored in 27 and 28. After several cycles of write time, the write operation to main memory 3 is completed.

B-4 Reading of updated block To update the data of the cache memory, the main memory is written by the triple of the request address, the thread identifier, and the block number in the set without ending the completion of the write operation to the main memory. A read access request is made. After several cycles after the request, the access to the main memory 3 is completed.

The blocks read from the main memory are sent through the main memory bus 8 as a quadruple obtained by adding a data block to a triplet of an address at the time of a read access request, a thread identifier, and a block number in a set. , Are stored in the external block buffer 110. Then, FIG.
Is sent to the multiplexer 4 at the entrance of the cache unit through the left line 10 (indicated by a bold line), and finally is written into the data memory arrays 41 to 44 through the pipeline processing step shown in FIG.

B-5 Update of Tags and Blocks In response to the movement of the corresponding thread identifier, FIG.
As shown in (1), each processing step (decode 1 and decode 2) is performed by the decoder 11 and the decoder 12. Thereafter, first, the tag memory arrays 31 to 34 are accessed, and the tags are updated with the addresses and the block numbers in the set.
Next, the contents of the data block are written into the corresponding blocks of the data memory arrays 41 to 44 by the address and the block number in the set, and the entry is updated.

The write timing for this update is as follows:
Similarly, this is when the thread number (111) stored in the external block buffer 110 matches the thread number of the thread identifier flowing in the memory array stage of the pipeline. At this time, the dirty bit in the corresponding block is cleared at the same time. At this point where the update is completed, the processor 1 returns the sleeping state of the missed thread to the active state.

In the case of updating, the operation of the fifth stage (not shown) is usually "empty" and only the clock is advanced. If any data is sent to processor 1, processor 1 discards the data without receiving it. As described above, writing to the corresponding blocks of the data memory arrays 41 to 44 is performed in the idle cycle of the sleeping thread, so that there is no conflict with the memory array access of another active thread.

By giving a thread identifier to a write request to the main memory 3, a write request from the cache memory 2 to the main memory 3 is made asynchronously,
Even when the access is completed after a large latency, the synchronization with the pipeline processing can be accurately obtained.

The reason for assigning the block number in the set is that the method of simply storing the data of the missed block in the cache memory 2 via the external block buffer 110 cannot cope with the occurrence of a plurality of mishits. It is.

Whether a block is dirty or clean depends on the write operation described below.

(C) Write Operation (When Hit) Finally, the write operation will be described. In this embodiment, a so-called write-back method is employed, but the present invention is not limited to the write-back method, and can be applied to a write-through method.

The write request is sent to the address decoders 11 and 12 together with the address, write data and thread identifier.
Then, the data is sent to the tag memory arrays 31 to 34 through the pipeline latches 20, 21, and 22, respectively. After the tag access, the operation is exactly the same as the read operation up to the point where the tag comparison is performed by the comparators 35 and 36.

Data memory array 4 of cache memory
Normally, 1 to 44 are provided with a dirty bit field of 1 bit for each block (not shown). When the output of one of the comparators 35 and 36 is "equal", that is, at the time of a hit, the write data and the address are sent to the data memory arrays 41 to 44 to perform writing, and the dirty bit of the corresponding block is turned on.

(D) Write operation (at the time of a mishit) When the outputs of the comparators 35 and 36 are not equal, that is, when there is no corresponding block in the cache memory 2 and there is a mishit, the corresponding block exists. A write request is issued only to the main memory 3 to be written, and writing is performed.

This method is known as a so-called right-no-allocate method. Since writing to the main memory 3 is performed in parallel with the operation of the processor 1, it is not necessary to stop the thread in which a write error has occurred in the event of a write error. Since a block having a write miss does not exist in the cache, it always becomes a mishit in a subsequent read access, and is read into the cache memory 2 by the above-described read operation.

[0058]

As described above, according to the present invention,
For example, in a cache memory having a pipeline structure suitable for a multi-thread processor or the like, even if a cache access is a mishit, it is possible to perform a cache entry update process and an access process from a subsequent thread at the same time. Become. Then, there is no problem such that the access to the memory array competes, the pipeline operation is disturbed, and the throughput of the cache memory is reduced.

The embodiment of the present invention described here is merely an example, and the embodiment of the cache memory updating circuit can be variously modified without changing the gist of the present invention.

[Brief description of the drawings]

FIG. 1 is a diagram showing an update circuit of a pipeline cache of the present invention.

FIG. 2 is a diagram showing a configuration of a signal transmitted between a pipeline cache and a processor and a main memory. (A) Configuration of memory system, (b) Between pipeline cache and processor, (c) Between pipeline cache and main memory

FIG. 3 is a diagram showing processing contents in each stage of the pipeline. (A) read (hit), (b) read (miss hit), (c) write or update

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Cache memory 3 ... Main memory 4, 40, 45 ... Multiplexer 6, 7, 8, 10 ... Bus 9 ... Random generator 11, 12 ... Decoder 13, 46, 49 ... Data field 14, 25, 29 , 47 ... thread identifier (indicated by thread number) 15, 26 ... upper address field 16, 17, 27, 28 ... lower address field 18, 35, 36 ... comparator 20, 21, 22, 23 ... pipeline latch 24 ... Internal block buffers 31, 32, 33, 34 Tag memory array 37 NAND circuit 38 Hit / miss field 39 Comparison field 41, 42, 43, 44 Data memory array 48, 58 Address field 50, 51 52, 53 ... thread identifier case Field 54 ... free cycle display field 61, 62 ... data fields 100, 110 ... external block buffer 211,221,231,241,251,101,1
11… thread number

Claims (6)

[Claims] 1. A method according to claim 1, wherein the processor is arranged between a processor and main memory.
In a cache memory configured to execute pipeline processing in a plurality of stages for a plurality of threads requested by a processor, a first pipeline latch serving as an interface between the processor and the cache memory; A second pipeline latch disposed at an intermediate stage forming a line, and an external block buffer serving as an interface between the main memory and the cache memory, wherein the first pipeline latch is a thread to be processed. The second pipeline latch includes a field indicating a thread identifier processed at this stage, and the external block buffer corresponds to the block. Thread A field for displaying an identifier, a block address, and a block number in a set, and comparing and determining whether the thread identifier displayed by the first pipeline latch matches the thread identifier displayed by the external block buffer. A cache memory updating circuit, comprising: 2. The cache memory updating circuit according to claim 1, wherein said cache memory is a set associative cache memory. 3. The cache memory updating circuit according to claim 1, wherein the field for displaying the state of the thread indicates that the cache memory is inactive if the cache memory has a mishit with respect to the thread. 4. When the comparison circuit determines that they match,
2. The cache memory update circuit according to claim 1, wherein a data update process for a corresponding thread is executed under the control of the processor. 5. The cache memory updating circuit according to claim 2, further comprising a random generator for selecting a block number in a set when updating data. 6. The first pipeline latch and the second pipeline latch are connected to the next stage via respective decoders for decoding addresses of data requested to be read. 3. The cache memory updating circuit according to claim 1 or 2.