JP2001189675A - Radio equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide radio equipment adaptive to plural radio communication systems with minimum hardware devices. SOLUTION: The radio equipment is composed of an A/D and D/A converter 1, memory 2 for temporarily storing the data of the A/D and D/A converter 1, DSP 4 for processing the prescribed operation of the radio equipment on the basis of a program described by software, FPGA 5 for processing the prescribed operation of the radio equipment in the manner of hardware on the basis of a program described in a hardware description language, reloadable storage device 3 for holding the software of these DSP and FPGA, input/output controller 10, I/O interface 9, CPU 7 for executing software of controlling its own entire equipment, ROM 8 for storing the software of the CPU and memory 6 for temporarily storing data processed by the CPU and these elements are connected by the FPGA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio apparatus that performs signal processing by software.

[0002]

2. Description of the Related Art Some radios perform all or a part of signal processing by software. FIG. 9 shows the configuration of a conventional radio of this type. In FIG. 9, 101 is an A / D and D / A converter, 102 is a dedicated IC, and 103 is a D / A converter.
SP (Digital Signal Process)
or; a digital signal processing device), 104 is a memory, 10
5 is a control IC, 106 is a CPU, 107 is a ROM, 1
08 is an I / O interface, 109 is RAM, 11
0 is an A / D and D / A converter, and 111 is an analog I / O.

Hereinafter, the operation of the conventional radio will be described with reference to FIG.

In the case of reception, an A / D and D / A converter 101 receives an analog signal received by a radio unit (not shown), converts the signal into a digital signal, and converts the signal into a dedicated I / O signal.
An operation of transferring the information to C102 is performed. On the other hand, in the case of transmission,
The digital signal input from the dedicated IC 102 is received, the signal is converted into an analog signal, and the signal is delivered to a wireless unit (not shown) and transmitted.

When receiving, the dedicated IC 102 and the DSP 103 demodulate the signal input from the A / D and D / A converter 101, perform waveform shaping using a root roll-off filter, etc., a channel codec, a voice codec, and the like. Is decrypted. On the other hand, in the case of transmission, operations such as encoding (mapping) of the original signal, waveform shaping and modulation using a root roll-off filter and the like are performed by digital signal processing, and the signal is converted into an A / D, D / A converter 101 Perform the operation of passing to. In these processes, the dedicated IC 102
Performs relatively high-speed processing.
And performs relatively low-speed signal processing and the like in accordance with the program recorded in Step 4. These processes may differ depending on the wireless communication system used, the dedicated IC used, and the performance of the DSP.

The control IC 105 controls the input / output timing of signals among the A / D / D / A converter 101, the dedicated IC 102, and the DSP 103, channel control, and modulation / demodulation switching. Also, it controls a wireless unit (not shown).

The CPU 106 loads the program recorded in the ROM 107 into the RAM 109,
Control IC 1 according to the program loaded in M109
05 and the input / output of data with the keyboard and the display via the I / O 108.

The A / D and D / A converters 110 and the analog I / Os 111 receive A / D,
The D / A converter 110 converts the digital signal decoded from the DSP 103 into an analog audio signal and transfers the analog audio signal to the analog I / O 111. The analog I / O 111 reproduces the received analog signal into sound using a speaker. On the other hand, in the case of transmission, the analog I / O 111 transfers the analog audio signal input from the microphone to the A / D, D / A converter 110. The A / D and D / A converter 110 converts the received analog signal into a digital signal,
Hand over to 103.

Most of such conventional radios are made of dedicated hardware such as an ASIC and a gate array, and some of the radio functions are realized by software. This makes it possible to take measures against some of the functions performed by the DSP in response to changes in specifications after design prototyping and bugs.

However, the conventional radio has the following problems. That is, in such a wireless device architecture, in order to support a plurality of wireless communication systems, such as an analog mobile phone and a digital mobile phone, with a single wireless device, only a small part of software is required. Therefore, it is necessary to physically provide a plurality of hardware parts and take measures such as switching between them as necessary, and there is a problem that the hardware scale becomes large. In addition, one wireless device cannot be used in both wireless communication systems such as PDC and PHS. In addition, when bugs occur in radios, most of them are hardware bugs, so even if it is small, we will collect all products depending on the type of bug,
There is a need to replace parts and the like, resulting in a significant cost loss.

[0011]

SUMMARY OF THE INVENTION In a conventional wireless device,
In order to cope with a plurality of wireless communication systems, it is necessary to take measures such as mounting a plurality of hardware and switching between them as necessary, and there is a problem that the hardware scale becomes large. In addition, a wireless device manufactured to support a certain wireless communication system cannot be changed to support another wireless communication system.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a wireless device capable of easily coping with a plurality of wireless communication systems.

[0013]

Means for Solving the Problems The present invention (claim 1) provides:
A wireless device capable of supporting a plurality of wireless communication systems, wherein an element commonly used by the plurality of wireless communication systems, a plurality of types of elements used according to the wireless communication system, Depending on the wireless communication system to be
Wiring means for changing the connection between the elements.

[0014] Preferably, the wiring means may change the connection between the elements so that the elements not used in the wireless communication system to be set are not connected to other elements.

Preferably, the wiring means comprises an FPGA, and the connection between the elements may be changed by rewriting the wiring of the FPGA.

Preferably, the plurality of types of elements used in accordance with the wireless communication system include a DSP for realizing a predetermined function necessary for supporting the wireless communication system, In order to include at least one of an FPGA for realizing a predetermined function necessary for corresponding and a dedicated IC for realizing a predetermined function required for supporting the wireless communication system, Is also good.

Preferably, the information processing apparatus may further include means for storing information indicating a connection state between the elements according to the wireless communication system.

The present invention (Claim 6) provides A / D and D /
An A converter, a first memory for temporarily storing data of the A / D and D / A converters, a DSP for processing a predetermined operation of the radio device based on a program described by software, and a An FPGA that processes a predetermined operation in hardware based on a program described in a hardware description language, a rewritable first storage device that holds the DSP and software of the FPGA, an input / output control device, and an I / O A wireless device including an interface, a CPU for executing software for controlling the entire device, a second storage device for storing software of the CPU, and a second memory for temporarily storing data processed by the CPU. The A / D and D / A converters, the first memory, the DSP, the FPGA, the first storage device, the input / output Controller, the I / O interface, the CPU, the second storage device, and the connections between at least some of the elements of said second memory F
It is characterized by performing by PGA.

For example, a plurality of wireless communication systems can be supported by rewriting the DSP program and the FPGA wiring for connecting (wiring) the elements.

Preferably, a dedicated IC for processing the operation of the radio device by hardware is further provided, and the connection between the dedicated IC and another element may be performed by the FPGA.

[0021] Preferably, the input / output control device may control a radio means comprising an analog circuit.

Preferably, a D / A converter to which a speaker is connected is connected to an output of the I / O interface,
An A / D converter having a microphone connected to the input of the I / O interface may be connected to enable voice communication.

Preferably, a network I / O device may be connected to the I / O interface to enable data communication.

The present invention relating to the apparatus is also realized as an invention relating to a method, and the present invention relating to a method is also realized as an invention relating to an apparatus.

According to the present invention, a wireless device that performs wireless signal processing by software is provided with only a minimum amount of hardware and is provided with means for adaptively changing wiring. It is possible to correspond to a communication system, and a system change for processing used in each wireless communication system can be easily and quickly realized. In addition, when making a hardware change for various wireless communication systems, the wiring between devices can be easily changed by rewriting a changeable wiring program.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

Hereinafter, a radio having a function of realizing at least a part of the radio function by software is referred to as a “software radio”.

FIG. 1 shows a configuration example of a radio signal processing device applied to a software defined radio according to the present embodiment.

As shown in FIG. 1, the present radio signal processing apparatus performs A / D and D / A conversion for performing A / D conversion and D / A conversion.
A converter 1, A / D, D / A converter 1 or A / D
A memory 2 for temporarily storing data to a D / D / A converter 1, a rewritable storage device 3 for holding software of a DSP or an FPGA, and an operation of a radio device in a program described by software. DSP (Digital Signal Procedures)
sor; digital signal processing device) 4, an FPGA (Field Pr) that processes the operation of the radio device in hardware based on a program described in a hardware description language
It comprises an programmable gate array 5, a memory 6, a CPU 7, a ROM 8, an I / O interface 9, an input / output control unit 10, and a changeable wiring 11.

In the rewritable storage device 3, software for operating the DSP 4 is recorded. The DSP 4 performs a desired operation by loading a necessary program from the rewritable storage device 3 and executing it. The rewritable storage device 3 is an EEPROM (Electrically).
Erasable and Programmable
e Read Only Memory), RAM (R
Any memory that can be read and written, such as an Random Access Memory, may be used. The rewritable storage device 3 may include the memory 2 in some cases.

The "changeable wiring" (11) is used to make a data bus, a control line and the like optimal wiring for each wireless communication system when various wireless communication systems (for example, PDC or PHS) are used. Things. In addition, when there is a portion that is not used in the wireless communication system currently used, there is also an effect that the power consumption of the entire device is suppressed by preventing connection and unnecessary current from flowing. The changeable wiring 11 is formed of, for example, an FPGA.

FIG. 2 shows a configuration example of a software defined radio to which the present radio signal processing device is applied.

As shown in FIG. 2, the software defined radio is configured using a radio unit 12 and a radio signal processing device 20. The radio unit 12 performs RF processing such as analog signal filtering and power amplification, and IF processing such as band limitation, mixing with a local oscillation signal, and modulation / demodulation. The wireless unit 12 includes a wireless signal processing device 20.
A control line from the input / output control unit 10 is connected, and for example, switching control of a duplexer, control of the oscillation frequency of a synthesizer, and the like are performed.

Next, the operation of the software defined radio will be described.

First, when the power is turned on, the CPU 7
8 and performs an initial operation such as a check of a wireless communication system that is currently operable. During the operation of the wireless function, the DSP 4, the FPGA 5, and the I / O
The control of the O interface 9 is performed. Also, the memory 6
Stores a program and temporary data for the operation of the CPU 7. In this software defined radio, software for realizing a radio function is recorded in a rewritable storage device 3.

The DSP 4 and the FPGA 5 load and execute a program necessary for an operation recorded in the rewritable storage device 3 according to a control signal of the CPU 7. The application program executed by the DSP 4 is part or all of digital processing, and includes, for example, a modulation function, a demodulation function, a filtering function, a frequency conversion function, a signal generation (synthesizer) function, a channel codec (TDMA).
Control) function, voice codec function, spreading /
A despreading function and the like. Also, A / D,
Functions for controlling the D / A converter 1, for example, A / D, D / A
Control of converter clock frequency, and input / output control unit 1
A function of controlling the wireless unit 12 through the control unit 0, for example, switching of gain may be included. If the DSP 4 includes a function whose processing speed is too late or a function that is more efficient to execute with the FPGA 5, the FPGA 5 executes this function. Of course, the CPU 7 may perform these controls.

The communication I / O interface 9 is used to communicate data transmitted / received by the wireless function with an external device. For example, the data is an audio signal,
If the signal is for data communication, an interface with an external device corresponding to the signal is provided.

The rewritable storage device 3 has a DS
It includes wiring information of “changeable wiring” (11) for connecting devices such as P4 and FPGA5,
The connection of the CPU 5, the FPGA 5, the CPU 7, and the like is performed according to a program in the rewritable storage device 3. Further, the CPU 7,
Since there is no need to change the connection of the ROM 8, the wiring may be fixed.

When the software defined radio performs communication,
First, at the time of reception, the A / D and D / A converters 1
An analog signal such as an IF signal and a baseband signal is received from the wireless unit, and A / D conversion processing is performed under the control of the DSP 4 and the CPU 7. The A / D converted digital signal is transmitted to the DSP 4 or the FPGA 5. If the signal transmitted here exceeds the processing speed of the DSP 4 or the FPGA 5, a method of temporarily storing the signal in the memory 2 is conceivable. For the converted digital signal,
The DSP 4 or the FPGA 5 performs demodulation processing, filtering processing, channel codec processing, audio codec processing, and in the case of CDMA, despreading processing and the like.
The data is transmitted directly to the O interface 9 or after performing processing such as packetization into a protocol to be transmitted by the CPU 7 in the case of data communication, for example.

At the time of transmission, data such as an audio signal and packet data is transmitted directly from the I / O interface 9 or after the CPU 7 processes the packet data.
4 or the FPGA 5. DSP4 or FP
The GA 5 performs a speech codec process, a channel codec process, a filtering process, a modulation process, and, in the case of CDMA, a spreading process on the received signal. When the processing is completed, the data is transmitted to the A / D and D / A converter 1. When a process for communicating data between the DSP 4 and the FPGA 5 is included, the data is stored in the memory 2 and the data is stored in the memory 4.
The processing is performed by accessing the A / D / D / A converter 1 from the memory 2.

By configuring the wireless device in this way, when supporting various wireless communication systems, since the modulation / demodulation function differs depending on the wireless communication system, the storage device 3 capable of rewriting the program of the modulation / demodulation function, for example, EEPRO
M, and this program is switched as necessary and executed by the DSP 4 or the FPGA 5, so that it is possible to adaptively cope with various modulation schemes.

In a wireless communication system requiring high-speed signal processing, the rewritable storage device 3 is rewritten, and a program necessary for the high-speed signal processing is added to the FPGA 5 for processing. At this time, the changeable wiring 11 is rewritten so that only necessary parts are connected.

In the case of the FPGA 5, the size of a program for a new wireless communication system or an updated program for adding a new function to an existing wireless communication system is expanded and a larger memory is required. In addition, a method of operating as a memory by adding a memory function to the memory is also conceivable. In such a case, since the connection wiring is fixed in the case of the conventional wireless device, it is impossible to adopt such a method without being able to connect to the I / O port of the memory. On the other hand, in the case of the software defined radio according to the present embodiment, the changeable wiring 11 is constituted by a rewritable device such as an FPGA, so even in such a case, a new wiring is added to the FPGA 5. It is possible to connect to the I / O of the added memory.

Next, FIG. 3 shows another configuration example of the radio signal processing device 20 applied to the software defined radio according to the present embodiment.

The wireless signal processing device of FIG. 3 is the same as the wireless signal processing device of FIG. 1 except that a dedicated IC 14 is added to the configuration of FIG.

In the configuration example of FIG. 3, the dedicated IC 14
Changeable wiring 1 in parallel with DSP4 and FPGA5
1 connected. The dedicated IC 14 is, for example, F
FT (Fast Fourier Transform)
high-speed processing such as the processing speed of the DSP 4 and the FPGA 5, or processing commonly used in a plurality of wireless communication systems, such as a filter function, a frequency conversion function, and a quadrature modulation / demodulation function. To do. The dedicated IC 14
Since the optimal design is performed for the processing to be executed, the processing can be expected to be faster. In addition, if the processing such as the quadrature modulation / demodulation function is not fast but can be shared by a plurality of wireless communication systems, the power consumption can be reduced by executing the processing using the dedicated IC 14.

The dedicated IC 14 is similar to the DSP 4 in that the dedicated IC 14 loads and executes a program necessary for an operation recorded in the rewritable storage device 3.

Next, a data input / output mode in the present wireless signal processing device (or a software defined radio to which the present wireless signal processing device is applied) will be described.

FIG. 4 shows a configuration in which an A / D and D / A converter 15 is connected to the I / O interface 9 shown in FIG. 1 or 3, and a microphone 16 and a speaker 17 are connected thereto. Here, by inserting a codec function between the A / D / D / A converter 15 and the I / O interface 9, it is possible to cope with digital modulation, and voice communication becomes possible.

FIG. 5 is a diagram in which a network I / O 18 is connected to the I / O interface 9 of FIG. 1 or FIG. The network I / O 18 is, for example, a serial connection I / O (RS-232C, USB, IEEE1
394), a PC card I / O, an Ethernet I / O, an infrared communication, a modem connectable to a telephone line, and the like. This enables data communication with information processing terminals such as personal computers and PDAs, other wireless devices, and public line networks.

Hereinafter, a software defined radio to which the present radio signal processing apparatus is applied will be described using a more specific example.

Here, a case where the ASIC 14 forms a digital quadrature modulator / demodulator and the FPGA 5 forms a filter section will be described as an example.

FIG. 6 shows an example of the configuration of the software defined radio.

In FIG. 6, the radio section 12 receives an RF wave from an antenna and supplies a signal to the A / D and D / A conversion section 1 by performing amplification processing, frequency conversion processing, and the like. The signal from the / D, D / A converter 1 is transmitted from the antenna as an RF wave.

The A / D and D / A conversion unit 1 performs an analog-to-digital conversion process on the signal from the radio unit 12 and supplies it to digital quadrature modems (31, 32). Is subjected to digital-analog conversion processing and supplied to the radio unit 12. The digital quadrature modulator / demodulator includes a multiplier 32 and an oscillator 31, and passes through a filter unit (33) to a demodulation unit 22 and a modulation unit 2.
3 is connected. The modulation / demodulation processing is performed by the digital quadrature modulator / demodulator, the filter unit, the demodulation unit 22, and the modulation unit 23. The TDMA control unit 24 performs digital signal processing and connects to the codec unit 25.

The codec unit 25 encodes and decodes audio, supplies an audio signal to the speaker 17 through the A / D and D / A converter 15, and outputs an A / D signal from the microphone 16.
An audio signal is received through the D / D / A converter 15.

When the configuration of the software defined radio of FIG. 6 is realized by using the radio signal processing apparatus of the present embodiment, for example, a digital quadrature modulator / demodulator is formed by the dedicated IC 14,
The filter unit is formed by the FPGA 5, and the demodulation unit 22, the modulation unit 23, the TDMA control unit 24, and the codec unit 25 are
4 and the wiring 11 that can be changed as necessary is set as appropriate. Note that, for example, the TDMA control unit 24
U7 may be realized, and other functional blocks are not limited to the above-described allocation method.

Next, the case where the functional blocks shown in FIG. 6 are realized in the radio signal processing apparatus of this embodiment will be described focusing on the "changeable wiring" (11).

FIG. 7 shows an example of wiring when the functional blocks of FIG. 6 are realized in the wireless signal processing device of the present embodiment.

In this case, the CPU 7, the ROM 8, the memory 6,
Are connected to a bus 26 having a fixed bit width.
, And a mode of connecting to the changeable wiring 11 is also conceivable. A general-purpose bus such as a PCI bus or an ISA bus may be used as the bus 26. A control line is connected from the bus 26 to the radio unit 12 and the A / D and D / A conversion unit 1.
Signal input / output wiring is connected to the D / D / A converter 15 and the dedicated IC 14, the dedicated IC 14 and the FPGA 5, and the FPGA 5 and the DSP 4 respectively. The DSP 4 is further connected to an I / O interface 9 for controlling input / output with the bus 26 and input / output with the A / D / D / A converter 15 for audio. All or some of these wirings are performed by the changeable wirings 11.

FIG. 8 is a wiring diagram in the software defined radio of the present embodiment for realizing the configuration of FIG.

As shown in FIG. 8, "changeable wiring"
(11) is an A / D, D / A converter 1, a dedicated IC 14,
The FPGA 5, the DSP 4, the bus 26, and the A / D / D / A converter 15 are connected by a plurality of wires. By rewriting the wiring inside the changeable wiring 11 by a program such as an FPGA as shown in FIG.
The connection as shown by the oblique lines in FIG. 7 is performed. That is, in this case, the internal wiring of the changeable wiring 11 is a fixed wiring with the A / D and D / A conversion unit 1 and a dedicated IC 1
4 with fixed wiring, fixed wiring with dedicated IC 14 and FPGA
5, and the fixed wiring with the FPGA 5 and the fixed wiring with the DSP 4 are written so as to be connected to each other.

In this embodiment, the example of the radio signal processing device including the DSP, the FPGA, and the dedicated IC has been described. However, not all of these elements are essential. Good thing. Of course, D
Elements other than the SP, the FPGA, and the dedicated IC may be provided.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope.

[0065]

According to the present invention, one wireless device can be easily adapted to a plurality of wireless communication systems.
In addition, when making a hardware change for various wireless communication systems, the wiring between devices can be easily changed by rewriting a changeable wiring program.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a wireless signal processing device of a software defined radio according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing a configuration example of a software defined radio according to the embodiment.

FIG. 3 is an exemplary view showing another configuration example of the wireless signal processing device of the software defined radio according to the embodiment;

FIG. 4 is an exemplary view showing an example of a data input / output mode of the software defined radio according to the embodiment;

FIG. 5 is an exemplary view showing another example of the data input / output mode of the software defined radio according to the embodiment;

FIG. 6 is an exemplary diagram showing a more detailed internal configuration example of the software defined radio according to the embodiment;

FIG. 7 is a diagram for explaining a changeable wiring;

FIG. 8 is a diagram for explaining a changeable wiring;

FIG. 9 is a diagram illustrating a conventional wireless device.

[Explanation of symbols]

 1, 15 A / D, D / A converter 2 memory 3 rewritable storage device 4 DSP 5 FPGA 6 memory 7 CPU 8 ROM 9 I / O interface 10 input / output control unit DESCRIPTION OF SYMBOLS 11 ... Changeable wiring 12 ... Wireless part 14 ... Dedicated IC 16 ... Microphone 17 ... Speaker 18 ... Network I / O 20 ... Wireless signal processing device 22 ... Demodulation part 23 ... Modulation part 24 ... TDMA control part 25 ... Codec part 26 ... bus 31 ... oscillator 32 ... multiplier 33 ... filter

 ──────────────────────────────────────────────────の Continuing from the front page (71) Applicant 599171154 Hiroshi Harada 3-4-2 Hikarinooka, Yokosuka City, Kanagawa Prefecture Within the Communications Research Laboratory, Ministry of Posts and Telecommunications, Yokosuka Radio Communication Research Center No. 1, Komukai Toshiba, Toshiba R & D Center (72) Inventor Hiroshi Yoshida No. 1, Komukai Toshiba, Kochi, Kawasaki, Kanagawa, Japan Toshiba R & D Center (72) Inventor Shinichi Kanno, Kanagawa (72) Inventor Masayuki Fujise 3-4 Hikarinooka, Yokosuka City, Kanagawa Prefecture, Japan Yokosuka Wireless Communication Research Center (72) Invention Person Hiroshi Harada 3-4 Hikarinooka, Yokosuka City, Kanagawa Prefecture Research Center in the F-term (reference) 5K004 AA05 FG02 FH00 5K011 AA16 DA00 DA26 JA01 KA01

Claims (10)

[Claims] A wireless device compatible with a plurality of wireless communication systems, comprising: an element commonly used by the plurality of wireless communication systems; a plurality of types of elements used according to the wireless communication system; A wireless device comprising wiring means for changing a connection between the elements according to a wireless communication system to be set in the wireless device. 2. The apparatus according to claim 1, wherein said wiring means changes the connection between the elements so that the elements not used in the wireless communication system to be set are not connected to other elements. A wireless device according to claim 1. 3. The wiring means comprises an FPGA.
The wireless device according to claim 1, wherein the connection between the elements is changed by rewriting a wiring of a GA. 4. A plurality of types of elements used according to the wireless communication system include a DSP for realizing a predetermined function required to support the wireless communication system, and a DSP supporting the wireless communication system. And at least one of an FPGA for realizing a predetermined function required to perform the function and a dedicated IC for realizing a predetermined function necessary for supporting the wireless communication system. The wireless device according to claim 1, wherein: 5. The wireless device according to claim 1, further comprising means for storing information indicating a connection state between the elements according to the wireless communication system. 6. An A / D and D / A converter, a first memory for temporarily storing data of the A / D and D / A converter, and a predetermined operation of the radio are described by software. A DSP that processes based on a program, an FPGA that processes a predetermined operation of the radio device in hardware based on a program described in a hardware description language,
A rewritable first storage device that holds the software of the SP and the FPGA, an input / output control device, an I / O interface, a CPU that executes software for controlling the entire device, and a second storage that stores software of the CPU. An A / D and D / A converter, the first memory, the DSP, the FPGA, a wireless device including a device, a second memory for temporarily storing data processed by the CPU, The first storage device, the input / output control device, the I / O interface, the CP
U, a connection between at least a part of the second storage device and at least a part of the second memory is performed by an FPGA. 7. A dedicated IC for processing the operation of the wireless device in a hardware manner, wherein the connection between the dedicated IC and another element is performed by the FPGA.
The wireless device according to claim 6, wherein the wireless communication is performed by: 8. The radio device according to claim 6, wherein said input / output control device controls radio means comprising an analog circuit. 9. An output of the I / O interface is connected to a D / A converter connected to a speaker, and an input of the I / O interface is connected to an A / D converter connected to a microphone. 7. The wireless device according to claim 6, wherein a call can be made. 10. The wireless device according to claim 6, wherein a network I / O device is connected to said I / O interface to enable data communication.