JP2001186197A - Current driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a current driver capable of performing operation over a wide voltage range. SOLUTION: A twisted pair of cables TP/NTP respectively connected to a termination bias voltage via a termination resistance is driven. For that reason, the current driver 3 connected to the twisted pair of cables, a common mode voltage monitor circuit 1 for monitoring the difference between the common mode voltage (intermediate potential) V cm of the twisted pair of cables and the power supply voltage of the driver 3 and a current correction circuit 2 connected to the twisted pair of cables, so as to gradually correct the output current of the driver 3 corresponding to the monitored results are provided, and when the current drive capability of the driver 3 falls due to the decrease of the power supply voltage of the driver 3 and the fluctuation of the common mode voltage V cm of the twisted pair of cables, a constant current operation is made possible by compensating the quantity of the fall of the current drive capability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a current driver circuit for a high-speed interface.

[0002]

2. Description of the Related Art In order to achieve high-speed data transmission,
A differential interface using a transmission line pair (twisted pair cable) coupled to a terminating bias voltage via a terminating resistor is preferred. Data transmission on this interface is performed by transmitting a constant-amplitude current through the twisted-pair cable by the transmitting-side current driver and detecting a small-amplitude and constant-amplitude potential difference generated at both ends of the terminating resistor by the receiving-side receiver circuit. Will be

US Pat. No. 5,592,510 (issue date:
(January 7, 1997) discloses a current driver circuit used in IEEE 1394, which is a high-speed serial interface standard. According to this, the output current to the twisted pair cable is monitored, and according to the monitoring result, the output current is corrected so as to have a constant amplitude.

[0004]

[0007] In order to further advance the miniaturization and low power consumption of semiconductor processes, it is essential to lower the power supply voltage. However, if the power supply voltage (Vdd) decreases when the termination bias voltage (Tpbias) is kept constant, the values of Vdd and Tpbias become closer, so that the drain-source voltage of the PMOS current source transistor in the current driver becomes higher. As a result, the PMOS current source transistor enters the non-saturation region, and the constant current operation cannot be performed. Therefore, in order to keep the output current within the predetermined range, the allowable range of Vdd is limited. On the other hand, when Vdd increases, the PMOS current source transistor operates in the saturation region, but the current amount tends to gradually increase due to the resistance of the drain region.
Therefore, it becomes necessary to provide a dedicated power supply for the PMOS current source transistor. However, providing a dedicated power supply is not realistic because it increases power consumption and manufacturing cost.

On the other hand, when the receiving side determines Tpbias, the value of Tpbias viewed from the current driver on the transmitting side fluctuates due to fluctuations in the ground level of the receiving side. Here, when Tpbias becomes lower, the NMO in the current driver becomes smaller.
The S current source transistor enters the non-saturation region, and the constant current operation cannot be performed. Conversely, when Tpbias increases, PMO
The S current source transistor enters the non-saturation region, and the constant current operation cannot be performed. Therefore, the value of Tpbias must be set within a range in which both current source transistors can operate at a constant current, but the region becomes narrower by lowering Vdd.

In view of the above problems, an object of the present invention is to provide a current driver circuit capable of operating in a wide voltage range.

[0007]

According to the present invention, there is provided a current driver circuit for driving a transmission line pair each coupled to a terminating bias voltage via a terminating resistor. And a common mode voltage (intermediate potential) of the transmission line pair
And a common mode voltage monitor circuit for monitoring a difference between the current driver and at least one power supply voltage level of the current driver, and an output current of the current driver is corrected in accordance with a monitoring result from the common mode voltage monitor circuit. And a current correction circuit coupled to the transmission line pair.

According to this configuration, when the current driving capability of the current driver is reduced due to a decrease in the power supply voltage level of the current driver or a change in the common mode voltage of the transmission line pair, the decrease is compensated for. Since the current correction circuit operates, constant current operation becomes possible. Moreover, since the difference between the common mode voltage and the power supply voltage level is used,
A current correction operation that correctly reflects the drain-source voltage of the current source transistor in the current driver can be realized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a transmitting / receiving circuit provided with a current driver circuit according to the present invention. The transmission / reception circuit 20 of FIG. 1 is coupled to a transmission line pair (twisted pair cable) TP / NTP having a series circuit of two terminating resistors R in the vicinity, and includes a common mode voltage monitor circuit 1, a current correction circuit 2, A current driver 3, a power supply voltage monitor circuit 4, a bias adjustment circuit 5, a pulse generation circuit 6,
It includes two current sources 7, a receiver circuit 8, and a resistor circuit 9.

The current driver 3 outputs the differential data signal Dat
a + / Data- depending on the twisted pair cable TP /
NTP is driven by a PMOS as described later.
It has a current source transistor and an NMOS current source transistor. The receiver circuit 8 outputs the strobe signal Str
This is a circuit for receiving b_Rx.

The resistor circuit 9 is composed of two resistors R1 and R2 provided in the LSI so as to detect the common mode voltage Vcm of the twisted pair cable.
The common mode voltage monitor circuit 1 is configured to detect a difference between a first power supply voltage (Vdd) level coupled to a source of a PMOS current source transistor in the current driver 3 and the common mode voltage Vcm; The difference from a second power supply voltage (Vss = ground) level coupled to the source of the NMOS current source transistor in the current driver 3 is monitored and evaluated. Monitor result Con
t <0: 3> is sent to the current correction circuit 2. The current correction circuit 2 is coupled to the twisted pair cable TP / NTP so as to gradually correct the output current of the current driver 3 according to the monitoring result Cont <0: 3>. The common mode voltage monitor circuit 1 and the current correction circuit 2 are circuits for correcting a shortage of current when any one of the current source transistors in the current driver 3 reaches an unsaturated region. Since stepwise current correction is employed here, current control with oscillation suppressed is facilitated.

The power supply voltage monitor circuit 4 has a reference potential Ref
The Vdd level is monitored and evaluated using <0: 1>. The monitoring result Mod <0: 1> is sent to the bias adjustment circuit 5. The bias adjustment circuit 5 corrects the output current of the current driver 3 according to the monitoring result Mod <0: 1> based on the basic bias Bias and the PMOS current source transistor and NM in the current driver 3.
Gate bias voltage P of each OS current source transistor
Adjust bias and Nbias. The power supply voltage monitor circuit 4 and the bias adjustment circuit 5 are circuits for correcting fluctuations in the amount of current caused by the drain resistance in the saturation region of the PMOS current source transistor in the current driver 3.

The transmission / reception circuit 20 of FIG. 1 can transmit information by forcibly changing the common mode voltage Vcm of the twisted pair cable. The pulse generation circuit 6 and the two current sources 7 have a configuration for that purpose. For example, when the speed signal SS representing transmission rate information is asserted, the pulse generation circuit 6 couples the two to the two signal lines TP / NTP of the twisted pair cable.
The signal SS1 is supplied to turn on the two current sources 7 at the same time. That is, Vcm is set for a certain period (about 100 ns).
By lowering, transmission rate information is transmitted. However, a sudden change in Vcm may occur, and the current correction circuit 2 may malfunction. To avoid this problem, the pulse generation circuit 6 supplies the signal SS2,
The Vcm input of the common mode voltage monitor circuit 1 and the output of the current correction circuit 2 are separated during the transmission period of the speed signal SS.

FIG. 2 shows an example of the configuration of the transmission / reception circuit of the transmission / reception circuit 20 shown in FIG. The transmitting / receiving circuit 21 of FIG.
Is coupled to a twisted pair cable TP / NTP having a series circuit of two terminating resistors R in the vicinity, and includes a current driver 3, a power supply voltage monitor circuit 4, a bias adjustment circuit 5, a receiver circuit 8, a termination circuit And a bias voltage generation circuit 11. The current driver 3 drives the twisted pair cable TP / NTP according to the differential strobe signal Strb + / Strb-. Bias adjustment circuit 5
Adjusts the gate bias voltages Pbias 'and Nbias' of the PMOS current source transistor and the NMOS current source transistor in the current driver 3, respectively. The receiver circuit 8 is a circuit for receiving the data signal Data_Rx. The termination bias voltage generation circuit 11 supplies a termination bias voltage Tpbias' equal to the supplied termination bias voltage Tpbias to an intermediate tap of the two termination resistors R.

The transmission / reception circuit 21 of FIG. 2 can determine the common mode voltage of the twisted pair cable TP / NTP with respect to its own ground level by the termination bias voltage generation circuit 11 by itself, so that the bias of each current source transistor in the current driver 3 can be determined. It is easy to design conditions in the saturation region. Therefore, unlike the transmission / reception circuit 20 of FIG. 1, the common mode voltage monitor circuit 1 and the current correction circuit 2
Need not be provided, and the circuit scale can be kept small.

FIG. 3 shows a detailed configuration example of the common mode voltage monitor circuit 1 in FIG. The common mode voltage monitor circuit 1 of FIG. 3 includes four comparators 31a to 31a.
d, transfer gate 32, current source 33, 4
There are provided resistors R3 to R6 and a capacitor C1.

The four resistors R3 to R6 are connected to Vdd and Vss.
(= 0 V). The current source 33 allows the current I1 to flow through a series circuit of these four resistors R3 to R6. Thereby, the resistance terminal voltages V1 to V4 are obtained. Here, V1 = Vdd-I1 * R3 V2 = Vdd-I1 * (R3 + R4) V3 = I1 * (R5 + R6) V4 = I1 * R6 The four comparators 31a to 31d generate Cont <0: 3> by comparing the common mode voltage Vcm with the resistance terminal voltages V1 to V4, respectively. Specifically, if the value of Vcm is equal to or less than the value of V1, C
ont <0> becomes “H”, and when it exceeds, Cont <0>
Becomes “L”. Similarly, when the value of Vcm is equal to or less than the value of V2, Cont <1> becomes "H", and when it exceeds, Cont <1> becomes Con.
t <1> becomes “L”. When the value of Vcm is equal to or more than V3, Cont <2> becomes “L”, and when the value falls below V3, Cot <2> becomes CoL.
nt <2> becomes “H”. Similarly, when the value of Vcm is V4
Above, Cont <3> becomes “L”, and below this, Cont <3> becomes “H”. In order to prevent malfunction due to the influence of noise or the like, the comparators 31a to 31a-3
It is preferable that the input / output relationship of 1d has hysteresis.

Further, according to FIG. 3, the Vcm input is disconnected from the common mode voltage monitor circuit 1 by turning off the transfer gate 32 by setting the SS2 signal to "H" during the transmission period of the speed signal SS. . In this period, the value of Vcm is held by the capacitor C1. As a result, the transmission period of the speed signal SS ends,
When the transfer gate 32 is turned on again, no potential difference occurs, and malfunction can be prevented.

FIG. 4 shows a detailed configuration example of the current correction circuit 2 in FIG. The current correction circuit 2 shown in FIG.
MOS current source transistors QP1 and QP2 and two P
MOS switching transistors QP3, QP4, 2
NMOS current source transistors QN1 and QN2, and 2
NMOS switching transistors QN3, QN4
, An inverter 41, and two NAND gates 42, 4
3 and two NOR gates 44 and 45.

When SS2 = "L", the differential data signal D
Even if data + / Data- is given, Cont <0>
And Cont <1> are “H” and Cont <2
> And Cont <3> are “L”, QP1, QP
None of P2, QN1, and QN2 perform a current correction operation (normal state). However, when Cont <1> transitions from the normal state to “L” due to a change in Vcm, for example, Q
P2 starts a current correction operation of discharging current to one signal line TP via QP3 and discharging current to another signal line NTP via QP4. Further Cont
When <0> changes to “L”, QP1 and QP2 start the current correction operation. On the other hand, from the normal state, Cont <2
When> changes to “H”, QN1 starts a current correction operation of drawing current from one signal line TP via QN3 or drawing current from another signal line NTP via QN4. Further, when Cont <3> changes to “H”, QN1 and QN2 start the current correction operation.

Further, according to FIG. 4, by setting the SS2 signal to "H" during the transmission period of the speed signal SS, QP3, QP
By turning off P4, QN3 and QN4 all,
QP1, QP2, QN1 and QN2 are all disconnected from the twisted pair cable TP / NTP.

FIG. 5 shows a detailed configuration example of the current driver 3 in FIG. The current driver 3 of FIG.
MOS current source transistor QP10 and two PMOSs
Switching transistors QP11 and QP12, one NMOS current source transistor QN10, and two NMs
OS switching transistors QN11 and QN12 are provided. Vdsp represents the drain-source voltage of QP10, and Vdsn represents the drain-source voltage of QN10.

FIG. 6 shows a detailed configuration example of the power supply voltage monitor circuit 4 in FIG. Power supply voltage monitor circuit 4 of FIG.
Has two comparators 51a and 51b and two high resistances R7 and R8. Two high resistance R7, R8
Are connected in series with each other between Vdd and Vss (= 0 V). The tap voltage V51 of this resistor series circuit
Are compared with reference potentials Ref <0> and Ref <1> by two comparators 51a and 51b, respectively.
Specifically, when the potential of V51 is lower than Ref <0>, Mod <0> becomes “L”, and when it is higher, Mod <0.
> Becomes “H”. Similarly, when the potential of V51 is Ref <1
>, Mod <1> becomes “L”, and when it is higher, Mod <1> becomes “H”.

FIG. 7 shows a detailed configuration example of the bias adjustment circuit 5 in FIG. The bias adjustment circuit 5 in FIG.
6 PMOS transistors QP61 to QP66, 2
NMOS transistors QN61 and QN62. QP61, QP62 and QP65 each represent a current source, QP63 and QP64 each represent a switch, and QN6
1, QN62 and QP66 each constitute a current mirror circuit.

According to FIG. 7, when the power supply voltage Vdd is high, only the current source QP65 receives the reference bias Bias. When Vdd drops to a predetermined potential, Mod <0
> Or Mod <1> attains “L”, so that the corresponding one of the switches QP63 and QP64 is turned on, the corresponding current sources QP61 and QP62 are added, and the current I6 increases. Therefore, Pbias
And Nbias change accordingly, and the current driver 3
Output current increases. The amount of change in the current amount is determined by the current source QP
61 and QP62 can be adjusted by the transistor size. In addition, the gate bias voltage is set to the PMOS side, NM
The adjustment may be made independently on the OS side.

FIG. 8 shows a detailed configuration example of the pulse generation circuit 6 in FIG. The pulse generation circuit 6 of FIG.
And second delay circuits 71 and 74 and a NAND gate 72
, A NOR gate 75, and two inverters 73 and 76
And

FIG. 9 shows the operation of the pulse generation circuit 6 of FIG. Here, the propagation delay time of the first delay circuit 71 is set to td1, and the propagation delay time of the second delay circuit 74 is set to td2. As shown in FIG. 9, a period during which the common mode voltage Vcm is changed (“H” period of SS1)
Means that the current correction circuit 2 is a twisted pair cable TP / NT
This is included in a period (“H” period of SS2) separated from P. Thereby, the current correction circuit 2
Can be further reduced. td1
And td2 may be set to, for example, 5 to 10 ns.

FIG. 10 shows the effects of the common mode voltage monitor circuit 1 and the current correction circuit 2, and FIG. 11 shows the effects of the power supply voltage monitor circuit 4 and the bias adjustment circuit 5, respectively. Ip in the figure is a PMOS current source transistor QP1.
In represents the sum of the drain currents of the activated transistors of 0, QP2 and QP1, and In represents the sum of the drain currents of the activated transistors of the NMOS current source transistors QN10, QN1 and QN2, respectively.

According to FIG. 10, the allowable range of the termination bias voltage Tpbias is limited to the upper limit VU1 and the lower limit in order to keep the currents Ip and In within a predetermined range (upper limit IU, lower limit IL), as indicated by a chain line. VL1. On the other hand, according to the present invention, it is possible to keep the currents Ip and In within a predetermined range between the upper limit IU and the lower limit IL in a wider range of Tpbias.

According to FIG. 11, the current Ip is conventionally set to a predetermined range (upper limit IU, lower limit IU) as indicated by a dashed line.
L), the allowable range of the power supply voltage Vdd is limited between the upper limit VU2 and the lower limit VL2. On the other hand, according to the present invention, in a wider range of Vdd, the current I
p can be within a predetermined range between the upper limit IU and the lower limit IL.

FIG. 12 shows the three PMOs in FIGS. 4 and 5.
An example of a preferred size of the S current source transistors QP10, QP2, QP1 is shown. That is, the current correction circuit 2
Changes the total size of the PMOS current source transistors to be activated non-linearly (for example, exponentially) with respect to the difference between the common mode voltage Vcm and the power supply voltage Vdd level. In the example of FIG. 12, the size of QP2 is set larger than that of QP10, and the size of QP1 is set larger than that of QP2. It should be noted that the three NMOS current source transistors QN10, QN1, QN2 in FIGS.
As for the total size of the NMOS current source transistors to be activated, the common mode voltages Vcm and Vss
What is necessary is just to change nonlinearly with respect to the difference with a level (ground level). By employing such non-linear control, it is possible to reduce the switching frequency of current correction as compared with the case of linear control.

FIG. 13 shows preferable fluctuation characteristics of the current I1 in FIG. The current I1 flowing from the current source 33 is P
It is preferable that the voltage is varied according to the current driving capability of each of the MOS current source transistor QP10 and the NMOS current source transistor QN10. Thereby, the comparators 31a to 31 in the common mode voltage monitor circuit 1
It becomes possible to make the detection level of d follow the threshold value fluctuation of the transistor based on the temperature or process fluctuation.

Although FIGS. 1 and 2 illustrate an example of communication between the two transmission / reception circuits 20 and 21, the present invention is applied to a transmission / reception system having only a transmission function at the master station and only a reception function at the slave station. It goes without saying that the invention is applicable.

[0035]

As described above, according to the present invention, a current driver circuit capable of supplying a constant current over a wide voltage range can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a transmission / reception circuit including a current driver circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a counterpart transmission / reception circuit of the transmission / reception circuit of FIG.

FIG. 3 is a circuit diagram of a common mode voltage monitor circuit in FIG.

FIG. 4 is a circuit diagram of a current correction circuit in FIG. 1;

FIG. 5 is a circuit diagram of the current driver in FIG. 1;

FIG. 6 is a circuit diagram of a power supply voltage monitoring circuit in FIG. 1;

FIG. 7 is a circuit diagram of a bias adjustment circuit in FIG. 1;

FIG. 8 is a circuit diagram of a pulse generation circuit in FIG. 1;

FIG. 9 is a timing chart showing an operation of the pulse generation circuit of FIG. 8;

FIG. 10 is a diagram showing the effects of the common mode voltage monitor circuit and the current correction circuit in FIG.

11 is a diagram showing the effects of the power supply voltage monitor circuit and the bias adjustment circuit in FIG.

FIG. 12 is a diagram for describing a preferred size example of three PMOS current source transistors in FIGS. 4 and 5;

FIG. 13 is a diagram showing preferable fluctuation characteristics of a current flowing from the current source in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Common mode voltage monitor circuit 2 Current correction circuit 3 Current driver 4 Power supply voltage monitor circuit 5 Bias adjustment circuit 6 Pulse generation circuit 7 Current source 8 Receiver circuit 9 Resistance circuit 11 Termination bias voltage generation circuit 20, 21 Transmission / reception circuit 31a-d Comparator 32 Transfer gate 33 Current source 51a, b Comparator C1 Capacitance Ip Total drain current of activated PMOS current source transistor In Total drain current of activated NMOS current source transistor QP1,2,10 PMOS current source transistor QP3,4,11 , 12 PMOS switching transistor QP61-66 PMOS transistor QN1,2,10 NMOS current source transistor QN3,4,11,12 NMOS switching transistor QN61,62 NMO Transistor R Termination resistance R1 to R8 Resistance SS Speed signal (transmission rate information) TP, NTP Transmission line pair (twisted pair cable) Vcm Common mode voltage of transmission line pair Vdd First power supply voltage level Vss Second power supply voltage level (ground Level) Tpbias Termination bias voltage

Continuing from the front page (72) Inventor ▲ Takashi Gashi 1006 Kadoma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Yoshihide Komatsu 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (12)

[Claims] 1. A current driver circuit for driving a transmission line pair each coupled to a termination bias voltage via a termination resistor, comprising: a current driver coupled to the transmission line pair; A common mode voltage monitor circuit for monitoring a difference between a common mode voltage and at least one power supply voltage level of the current driver; and correcting an output current of the current driver according to a monitoring result from the common mode voltage monitor circuit. And a current correction circuit coupled to the transmission line pair. 2. The current driver circuit according to claim 1, wherein the current correction circuit corrects an output current of the current driver in a stepwise manner. 3. The current driver circuit according to claim 1, wherein the current correction circuit changes a total size of the current source transistors to be activated non-linearly with respect to a difference between the common mode voltage and the power supply voltage level. A current driver circuit, comprising: 4. The current driver circuit according to claim 1, wherein said current driver comprises a PMOS current source transistor and an N.
A MOS current source transistor, the common mode voltage monitor circuit comprising: a difference between a first power supply voltage level coupled to a source of the PMOS current source transistor and the common mode voltage; A current driver circuit for evaluating a difference from a second power supply voltage level coupled to a source of an NMOS current source transistor. 5. The current driver circuit according to claim 4, wherein the common mode voltage monitor circuit includes a plurality of serially connected between the first power supply voltage level and the second power supply voltage level. A resistor, a current source for causing a current to flow through a series circuit of the plurality of resistors, and a plurality of comparators for comparing the common mode voltage and terminal voltages of the plurality of resistors, respectively. Current driver circuit. 6. The current driver circuit according to claim 5, wherein each of the plurality of comparators has a hysteresis in an input / output relationship. 7. The current driver circuit according to claim 5, wherein the current flowing through said current source varies according to the current driving capability of each of said PMOS current source transistor and said NMOS current source transistor. Current driver circuit. 8. The current driver circuit according to claim 4, wherein a power supply voltage monitoring circuit for monitoring the first power supply voltage level, and an output of the current driver according to a monitoring result from the power supply voltage monitoring circuit. In order to correct the current, the PMO
A current driver circuit, further comprising: a bias adjustment circuit for adjusting a gate bias voltage of each of the S current source transistor and the NMOS current source transistor. 9. The current driver circuit according to claim 1, further comprising: means for disconnecting the current correction circuit from the transmission line pair when transmitting / receiving a signal by changing the common mode voltage. A current driver circuit, characterized in that: 10. The current driver circuit according to claim 9, wherein the period in which the common mode voltage is changed is included in a period in which the current correction circuit is disconnected from the transmission line pair. . 11. A current driver circuit for driving a transmission line pair each coupled to a termination bias voltage via a termination resistor, the current driver circuit comprising a PMOS current source transistor and an NMOS current source respectively coupled to the transmission line pair. A current driver having a transistor; a power supply voltage monitor circuit for monitoring a power supply voltage level coupled to a source of the PMOS current source transistor; and an output current of the current driver according to a monitoring result from the power supply voltage monitor circuit. So that the PMO
A current driver circuit, comprising: a bias adjustment circuit for adjusting a gate bias voltage of each of the S current source transistor and the NMOS current source transistor. 12. A signal transmission method for transmitting a signal by flowing a current having a constant amplitude through a transmission line pair coupled to a terminal bias voltage via a terminal resistor, wherein the common mode voltage of the transmission line pair is And monitoring a difference between a power supply voltage level of a current driver for driving the transmission line pair and a current flowing through the transmission line pair within a predetermined range based on a result of the monitoring. A step of correcting the output current of the current driver in a stepwise manner.