JP2001186146A - Data transfer controller and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer controller having reduced time required for reset processing and the relieved processing load, and to provide an electronic device. SOLUTION: The data transfer controller, which is in compliance with the IEEE 1394 standards analyzes a received packet, stores the packet into a queue without processing it immediately and starts processing of the received packet, when a received packet on a data buffer is not in existence. The controller aborts the received packet which is not needed by resetting, when the received packet is a reset packet. When a plurality of queues is in existence, the queue of the received packet which is not needed by reset is cleared. The queue for a management agent MNG is processed with priority and in the case of resetting an MNG, and not only the MNG queue but also fetching agent FCH queue is cleared. The queue for command control fetching agent FCH1 is processed with priority. When bus reset occurs, by clearing the queue of the received packet, the received packet prior to the occurrence of the bus reset is aborted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device and an electronic apparatus, and more particularly, to a data transfer control device and a data transfer control device for performing data transfer in accordance with a standard such as IEEE1394 between a plurality of nodes connected to a bus. Related to electronic equipment.

[0002]

BACKGROUND OF THE INVENTION In recent years, I
An interface standard called EEE1394 has been spotlighted. This IEEE 1394 standardizes a high-speed serial bus interface that can support next-generation multimedia. This IEEE 1394
According to this, data requiring real-time properties such as moving images can be handled. In addition, not only computer peripherals such as printers, scanners, CD-RW drives, and hard disk drives, but also home appliances such as video cameras, VTRs, and TVs can be connected to the IEEE 1394 bus. For this reason, it is expected that digitalization of electronic devices can be drastically promoted.

[0003] SBP-2 (Serial Bus Protocol) standardized as an upper protocol of IEEE 1394 is now known.
In l-2), resets such as agent reset, target reset, and reset start are defined. That is, the target (printer, scanner, CD-R
W, etc.), when it is determined that the data transfer process cannot be continued, the initiator (such as a personal computer) requests the above reset. When such a reset is requested, it is necessary to discard a received packet that becomes unnecessary due to the reset.

In addition, in IEEE1394, when an electronic device is newly connected to a bus or an electronic device is removed from the bus, and the number of nodes connected to the bus increases or decreases, a so-called bus reset occurs. Then, when a bus reset occurs, the topology information of the node is cleared, and all incomplete transactions are canceled, so that all packets received before the occurrence of the bus reset become invalid.

[0005] However, firmware for processing packets generally operates on a CPU having a low processing speed in many cases. Therefore, processing on a received packet is performed after a given time has elapsed after the reception of the packet. For this reason, a large number of unprocessed packets always exist on the target data buffer. Therefore, it takes a lot of time to search for a received packet that becomes unnecessary due to a reset (agent reset, bus reset, etc.) from a large number of received packets existing in the data buffer. For this reason,
The resetting process takes a long time, causing problems such as stall of the entire system process and an excessive processing load of the firmware.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a data transfer control device capable of shortening the time required for reset processing and reducing the processing load. And electronic equipment.

[0007]

According to the present invention, there is provided a data transfer control device for transferring data between a plurality of nodes connected to a bus. Packet analysis means for analyzing the written received packet, storing the analyzed received packet in a queue, and repeatedly analyzing the received packet and storing it in the queue until there are no more received packets in the data buffer; and a received packet in the data buffer. When there is no packet, packet processing means for processing the received packet stored in the queue, and when the processed received packet is a packet instructing a reset, the packet is unnecessary due to the reset among the received packets stored in the queue. And a packet discarding means for discarding the received packet.

According to the present invention, the analyzed received packet is stored in the queue without being processed immediately. And
When there are no more received packets in the data buffer, processing of the received packets stored in the queue is started. Then, if the received packet is a packet instructing reset, the received packet that becomes unnecessary due to the reset is discarded. By doing so, it is possible to prevent unnecessary packet processing from being performed on received packets that become unnecessary due to the reset (received packets affected by the reset), and it is possible to greatly reduce the time required for the reset processing.

Although it is desirable to provide a plurality of queues, one queue may be provided. Further, as the processing of the received packet performed by the packet processing means, for example, processing of passing the received packet to a subsequent processing means (request execution means or the like) can be considered. As a process of discarding unnecessary received packets, a process of clearing a queue or the like can be considered, but the received packets may be discarded individually.

Further, according to the present invention, a plurality of queues are prepared as the queue, the packet analyzing means stores the analyzed received packet in any one of the plurality of queues, and the packet discarding means comprises If the processed received packet is a packet instructing reset,
It is characterized by clearing a queue in which received packets that become unnecessary by resetting are stored.

[0011] In this manner, since the received packets that become unnecessary due to the reset can be collectively discarded, the process of discarding the received packets can be made much more efficient.

It is desirable that each of the plurality of queues be provided with a queue corresponding to a processing unit (request execution unit or the like) at a subsequent stage for passing the received packet.

Also, the present invention provides a first request executing means for receiving a received packet from the packet processing means and executing a request from another node, and receiving a received packet from the packet processing means and receiving a received packet from the other node. A second request execution unit that executes a request and resets itself when the first request execution unit is reset, wherein the packet analysis unit transmits the request to the first request execution unit. The received packet to be passed is stored in a first queue, the received packet to be passed to the second request execution means is stored in a second queue, and the packet processing means is stored in the first queue. The received packets stored in the second queue are processed with higher priority than the received packets stored in the second queue.

With this configuration, the received packet to be passed to the first request execution means is processed with priority. Therefore, it is possible to prevent a situation in which the received packet of the second request execution unit, which is reset when the first request execution unit is reset, is unnecessarily processed, and the time required for the reset process can be reduced. .

As the first and second request execution means, for example, a management agent or a fetch agent in SBP-2 can be considered, but the present invention is not limited to this.

Further, according to the present invention, the packet discarding means includes:
If the processed received packet is a packet instructing reset of the first request execution means, the first,
It is characterized in that both of the second queues are cleared.

In this way, the received packets of the second request execution means which do not need to be processed are collectively discarded, so that the processing can be made more efficient.

Further, according to the present invention, the second request execution means executes a command control request of an upper layer device.
And a fourth request execution unit for executing a data transfer request, wherein the packet analysis unit stores a received packet to be passed to the third request execution unit in a third queue, The received packet to be passed to the fourth request execution unit is stored in a fourth queue, and the packet processing unit stores the received packet stored in the third queue in the fourth queue. It is characterized in that processing is performed prior to received packets.

According to this configuration, the received packet to be passed to the third request execution means can be processed preferentially, and the command control request of the device can be interrupted during the data transfer processing.

The present invention also relates to a data transfer control device for transferring data between a plurality of nodes connected to a bus, which analyzes a received packet written in a data buffer of its own node, and analyzes the received packet. Packet analysis means for storing packets in a queue, and repeating analysis of received packets and storing them in the queue until there are no more received packets in the data buffer; and receiving packet stored in the queue when there are no more received packets in the data buffer. It is characterized by including a packet processing means for processing and a packet discarding means for discarding a received packet before the occurrence of the reset when a reset for clearing the topology information of the node occurs.

According to the present invention, the analyzed received packet is stored in the queue without being processed immediately. And
When there are no more received packets in the data buffer, processing of the received packets stored in the queue is started. When a reset for clearing the topology information of the node occurs, the received packet before the occurrence of the reset is discarded. Therefore, it is possible to prevent unnecessary packet processing from being performed on the packet received before the occurrence of the reset, and it is possible to greatly reduce the time required for the reset processing.

Further, according to the present invention, the packet discarding means includes:
When a reset for clearing the topology information of the node occurs, the queue storing the received packet is cleared.

In this way, the received packets before the occurrence of the reset can be collectively discarded, so that the processing efficiency can be improved.

The determination as to whether or not to clear the queue may be made each time a received packet is stored in the queue, or may be made after all received packets have been stored in the queue.

It is preferable that the reset for clearing the topology information of the node is a bus reset defined in the IEEE 1394 standard.

In the present invention, it is desirable to perform data transfer conforming to the IEEE 1394 standard.

An electronic apparatus according to the present invention includes any one of the above data transfer control devices, an apparatus for performing a given process on data received from a partner node via the data transfer control device and a bus, And a device for outputting or storing the data on which data has been applied. Further, the electronic device according to the present invention, any one of the data transfer control device described above, a device that performs a given process on data to be transmitted to the partner node via the data transfer control device and a bus,
And a device for taking in data to be processed.

According to the present invention, the processing load on firmware or the like for controlling data transfer can be reduced, so that it is possible to reduce the cost of electronic equipment and speed up processing.
In addition, since a situation in which the processing of the entire system is stalled due to the occurrence of the reset can be prevented, the reliability of the electronic device can be improved.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. IEEE 1394 First, IEEE 1394 will be briefly described.

1.1 Overview IEEE 1394 (IEEE 1394-1995, P1
394. In (a), high-speed data transfer of 100 to 400 Mbps is possible (800 in P1394.b).
３3200 Mbps). It is also allowed to connect nodes having different transfer speeds to the bus.

Each node is connected in a tree shape.
A maximum of 63 nodes can be connected to one bus. If a bus bridge is used, about 64000 nodes can be connected.

In IEEE 1394, asynchronous transfer and isochronous transfer are prepared as packet transfer methods. Here, the asynchronous transfer is a transfer method suitable for transfer of data requiring reliability, and the isochronous transfer is a transfer method suitable for transfer of data such as moving images and audio which require real-time properties.

1.2 Layer Structure FIG. 1 shows the layer structure (protocol configuration) of IEEE1394.

The IEEE 1394 protocol includes a transaction layer, a link layer, and a physical layer. The serial bus management monitors and controls the transaction layer, link layer, and physical layer, and provides various functions for controlling nodes and managing bus resources.

The transaction layer provides an interface (service) in transaction units to the upper layer, and executes transactions such as a read transaction, a write transaction, and a lock transaction through the interface provided by the lower link layer.

Here, in the read transaction, data is transferred from the response node to the request node. on the other hand,
In a write transaction, data is transferred from a request node to a response node. In a lock transaction, data is transferred from the requesting node to the responding node,
The responding node processes the data and returns it to the requesting node.

The link layer provides addressing, data check, data framing for packet transmission / reception, cycle control for isochronous transfer, and the like.

The physical layer provides conversion of logical symbols used by the link layer into electric signals, arbitration of the bus, and provides a physical interface of the bus.

1.3 SBP-2 As shown in FIG. 2, a protocol called SBP-2 (Serial Bus Protocol-2) has been proposed as an upper protocol including some functions of the transaction layer of IEEE1394. ing.

Here, SBP-2 has been proposed to make the SCSI command set usable on the IEEE 1394 protocol. If this SBP-2 is used, the SBP used in the existing SCSI standard electronic equipment can be used.
With minimal changes to the CSI command set, IE
It can be used for EE1394 standard electronic equipment.
Therefore, the design and development of the electronic device can be facilitated. Also,
Since not only SCSI commands but also device-specific commands can be encapsulated and used, the versatility is very high.

As shown in FIG. 3, in SBP-2, first, a login ORB (Operation Request Block) created by an initiator (for example, a personal computer)
Is used to perform a login process (step T1). Next, the fetch agent is initialized using the dummy ORB (step T2). Then, command processing is performed using the command block ORB (normal command ORB) (step T3), and finally, logout processing is performed using the logout ORB (step T3).
4).

Here, in the command processing of step T3, as shown at A1 in FIG. 4, the initiator transfers a write request packet (issues a write request transaction) and rings the doorbell register of the target. Then, as indicated by A2, the target transfers the read request packet, and the initiator returns a corresponding read response packet. As a result, the ORB (command block ORB) created by the initiator is fetched into the target data buffer. Then, the target analyzes the command included in the fetched ORB.

The command included in the ORB is SC
If the write command is an SI write command, the target transfers a read request packet to the initiator, and the initiator returns a corresponding read response packet, as indicated by A3. Thereby, the data stored in the data buffer of the initiator is transferred to the target. Then, for example, when the target is a printer, the transferred data is printed by the printer engine.

On the other hand, the command included in the ORB is SCS
If the command is an I read command, the target transfers a series of write request packets to the initiator as shown in B1 of FIG. Thus, for example, when the target is a scanner, the scan data acquired by the scanner engine is transferred to the data buffer of the initiator.

According to SBP-2, the target can transfer a request packet (issue a transaction) and transmit / receive data when it is convenient. Therefore, since the initiator and the target do not need to move in synchronization, the data transfer efficiency can be improved.

As an upper layer protocol of IEEE1394, in addition to SBP-2, FCP (Function Control Protocol)
ol Protocol) has also been proposed.

1.4 Bus Reset In IEEE 1394, a bus reset occurs when power is turned on or when a device is inserted or removed in the middle. That is, each node monitors a voltage change of the port. When a change occurs in the port voltage due to a connection of a new node to the bus or the like, the node that has detected this change notifies other nodes on the bus that a bus reset has occurred. The physical layer of each node is
Inform the link layer that a bus reset has occurred.

When such a bus reset occurs, topology information such as a node ID is cleared.
After that, the topology information is automatically reset. That is, after the bus reset, tree identification and self identification are performed. Then the isochronous resource manager,
Management nodes such as a cycle master and a bus manager are determined. Then, the normal packet transfer is restarted.

As described above, in the IEEE 1394, the topology information is automatically reset after the bus reset.
A cable of an electronic device can be freely connected and disconnected, and a so-called hot plug can be realized.

If a bus reset occurs during a transaction, the transaction is canceled. Then, the request node that has issued the canceled transaction transfers the request packet again after the topology information is reset. The response node must not return a response packet of the transaction canceled by the bus reset to the request node.

2. Next, an overall configuration example of the data transfer control device of the present embodiment will be described with reference to FIG. In the following, a case where a target (own node) that performs data transfer with an initiator (a partner node) is a printer will be described as an example, but the present invention is not limited to this.

The data transfer control device 10 according to the present embodiment
It includes a PHY device 12 (physical layer device), a link device 14 (link layer device), a CPU 16 (processor), a data buffer 18 (storage means), and firmware 20 (processing means). PHY device 1
2. The link device 14, the CPU 16, and the data buffer 18 are optional components, and the data transfer control device 10 of the present embodiment does not need to include all of these components.

The PHY device 12 is a circuit for realizing the physical layer protocol of FIG. 1 by hardware, and has a function of converting a logical symbol used by the link device 14 into an electric signal.

The link device 14 is a circuit for realizing a part of the protocol of the link layer and the protocol of the transaction layer in FIG. 1 by hardware, and provides various services for packet transfer between nodes.

The CPU 16 controls the entire apparatus and controls data transfer.

The data buffer 18 is a buffer for temporarily storing transfer data (packets).
It is composed of hardware such as SDRAM or DRAM. In the present embodiment, the data buffer 1
Reference numeral 8 functions as a packet storage unit which is not particularly limited but can be accessed randomly.

The firmware 20 is a program including various processing routines (processing modules) operating on the CPU 16. The protocol of the transaction layer is as follows.
The firmware 20 and a hardware CPU
16 or the like.

The device driver 102 included in the personal computer 100 serving as the initiator is a program including various processing routines for managing and controlling peripheral devices. This program is stored in the information storage medium 11
0 (FD, CD-ROM, DVD, ROM).

Here, the program of the device driver 102 may be downloaded from an information storage medium (hard disk, magnetic tape, or the like) of the host system via a network such as the Internet, and installed in the personal computer 100.

The firmware 20 (F / W) includes a communication unit 30 (COM), a management agent 40 (MNG), and a fetch agent 50 (F / W).
CH1), a fetch agent 60 (FCH2), and a print task unit 70 (PRT).

Here, the communication unit 30 is a processing module that functions as an interface with hardware such as the link device 14.

The management agent 40 (first request execution means) is a processing module for managing login, reconnect, logout, reset, and the like. For example, when the initiator requests the target to log in, first, the management agent 40
Will accept this login request.

The fetch agents 50 and 60 (command block agents; second request execution means) are processing modules for executing a request from the initiator, and more specifically execute commands included in the command block ORB. I do. Fetch agent 50, 6
0 is different from the management agent 40, which can handle only a single request, and can also handle the link list of the ORB fetched by itself in response to a request from the initiator.

The printer disk unit 70 communicates with a printer engine or a scanner engine (upper layer device) by DMA.
This is a processing module for performing transfer.

The fetch agent 50 (third agent)
The (second) request execution unit) is a processing module for command control of a subsequent printer engine or scanner engine (upper layer device), and the fetch agent 60 (the fourth (second) request execution unit) , A processing module for transferring data between the subsequent printer engine and scanner engine.

For example, when it is desired to check the remaining ink amount during data transfer with the printer engine, if there is only one fetch agent, the remaining ink amount cannot be checked until all data transfer by the ORB link list is completed.

In this embodiment, two independent fetch agents are provided (three or more fetch agents may be provided). Then, the priority of the process of the fetch agent 50 for command control is determined by the fetch agent 6 for data transfer.
0 is higher than the priority of the process. More specifically, as described later, a received packet passed to the fetch agent 50 for command control is processed with priority over a received packet passed to the fetch agent 60 for data transfer.

By doing so, it is possible to interrupt printer command control processing such as ink remaining amount check during data transfer processing using the ORB link list. Therefore, it is possible to check the remaining ink amount without waiting for a long time for the data transfer process to end,
The command of the device can be controlled without affecting the data transfer.

The communication unit 30 includes a packet analysis unit 32, a packet processing unit 34, and a packet discarding unit 36.

Here, the packet analysis unit 32 transmits the data from the personal computer 100 to the IEEE 1394 bus and the PH.
The received packet written to the data buffer 18 via the Y device 12 and the link device 14 is analyzed. Then, the analyzed received packet is stored in the queue.

This queue can be secured on a local memory of the CPU 16, for example. When there are a plurality of queues as described later, the packet analysis unit 32 stores the received packet in a queue according to the analysis result.

After storing the received packet in the queue, the packet analyzing unit 32 analyzes the next received packet. The analysis of the received packet and the storing of the received packet in the queue are repeated until there is no more received packet in the data buffer 18.

The packet processing unit 34 includes a data buffer 1
When there are no more received packets on the queue 8, the received packets stored in the queue are processed. More specifically, the received packets stored in the queue are received by the management agent 40 (MNG) and the fetch agent 50 (F
CH1) or fetch agent 60 (FCH
Hand over to 2). For example, when there are a plurality of queues such as a queue for MNG, a queue for FCH1, and a queue for FCH2, a received packet stored in the queue for MNG is passed to the management agent 40. The received packets stored in the FCH1 and FCH2 queues are passed to the fetch agents 50 and 60, respectively.

The packet discarding unit 36 includes the packet processing unit 3
If the received packet processed by step 4 is a packet instructing a reset such as an agent reset, a target reset, a reset start, etc., among the received packets stored in the queue, the received packet that becomes unnecessary due to the reset (reset packet) Perform processing to discard the affected received packets). For example, when there are a plurality of queues, the received packets are collectively discarded by clearing the queue of the agent to be reset.

When a bus reset (a reset for clearing topology information of a node in a broad sense) occurs, the packet discarding unit 36 discards a packet received before the bus reset.

3. Features of the present embodiment 3.1 Discarding Unnecessary Packet at Reset Now, in SBP-2, when an error occurs in the target, the initiator instructs the target to reset (hereinafter referred to as a reset packet). ) Can be transferred. In this case, various resets having different levels are prepared in the SBP-2. For example, reset start is the strongest level of reset, and all node states are reset. In an abort task or an abort task set, a task or a set of tasks is reset, and in a target reset, a target is reset. In the agent reset, only the fetch agent is reset.

The reset start and the agent reset are transmitted to the target by the initiator writing predetermined information in a predetermined register. The abort task, abort task set, and target reset are performed by the management ORB transferred from the initiator.
Is transmitted to the target using.

As described above, when the reset packet is transferred from the initiator, it is necessary to discard a packet which becomes unnecessary due to the reset. Then, in this case, in the comparative example of FIG. 7, immediately after analyzing the received packet, packet processing (such as processing of passing the received packet to the agent) is performed (steps T1 and T2). Next, it is determined whether or not the received packet is a reset packet. If the received packet is a reset packet, a process of discarding the received packet is performed (steps T3 and T4). Then, the above processing is repeated until there are no more received packets (step T5).

However, in this comparative example, even for a received packet destined to be discarded by a reset,
Packet processing is performed. Therefore, the reset process becomes very inefficient.

In particular, when the data transfer control device according to the present embodiment is incorporated in a peripheral device such as a printer, a scanner, or a CD-RW, an inexpensive CPU with a low processing capacity is often used due to restrictions on product costs. , And therefore its CP
The firmware running on U is also affected by the restriction, and the processing speed is reduced. For this reason, the processing of the received packet cannot be made in time, and a large number of unprocessed received packets exist on the data buffer of the own node (target). Therefore, the problem of an increase in the reset processing time becomes more serious.

Therefore, in the present embodiment, as indicated by C1 and C2 in FIG. 8, after analyzing the received packet written in the target data buffer, the analyzed received packet is stored in the queue without being processed immediately. Then, as indicated by C3, when there are no more received packets in the data buffer, the received packets stored in the queue are processed. Then, as shown in C4, when the processed received packet is a reset packet such as an agent reset, a received packet that becomes unnecessary due to the reset (a received packet affected by the reset) is discarded.

In this way, for a received packet that becomes unnecessary without performing the packet processing due to the reset, the packet processing does not need to be performed. Therefore, the time required for the reset process can be significantly reduced as compared with the comparative example of FIG. 7 in which packet processing is performed on all received packets. As a result, it is possible to prevent a situation in which the processing of the entire system is stalled by the reset processing, and it is also possible to reduce the processing load on the firmware.

Further, in this embodiment, a plurality of queues for storing received packets are prepared, and the analyzed received packets are
Sort and store in any of the multiple queues. When a reset occurs, the queue storing the received packets that become unnecessary due to the reset is cleared.

More specifically, as shown in FIG. 9A, an MNG queue for storing received packets to be passed to the management agent and an FCH queue for storing received packets to be passed to the fetch agent are prepared. . Then, as shown in FIGS. 9A and 9B, the received packet is stored in a queue corresponding to the analysis result of the received packet. That is, packets to be passed to the management agent are stored in the MNG queue, and packets to be passed to the fetch agent are stored in the FCH queue.

Then, as shown in FIG. 9C, for example, when the received packet is determined to be an agent reset (when it is determined that the received packet is a write packet to the agent reset register), the FCH queue is cleared. . That is, the received packet stored in the FCH queue is a packet to be passed to the fetch agent and becomes unnecessary after the agent reset.
Therefore, by clearing the agent queue itself,
These unnecessary packets can be collectively discarded.

As described above, if the received packets are discarded by clearing the queue, unnecessary received packets can be discarded collectively, and the process of discarding the received packets can be made much more efficient. This makes it possible to further speed up the reset process.

In the present embodiment, when the first agent is reset and the second agent is reset, the received packet stored in the queue for the first agent is Processing is performed with priority over received packets stored in the queue for the second agent.

More specifically, as shown in FIG. 10A, an MNG queue for a management agent (first request executing means) and a fetch agent (second
If there is an FCH queue for request execution means), M
The received packet stored in the NG queue is processed preferentially (the fetch agent is also reset when the management agent is reset). That is, after packet processing (processing such as passing a packet to a management agent) for all received packets stored in the MNG queue is completed,
As shown in FIG. 10B, the packet processing of the received packet stored in the FCH queue is started.

In this way, as shown in FIG. 10C, for example, when a packet instructing a reset start is included in the received packets stored in the MNG queue, both the MNG queue and the FCH queue are used. Can be cleared. As a result, the received packets stored in the FCH queue are discarded, and it becomes unnecessary to perform useless packet processing on these received packets. As a result, the efficiency of the reset process can be further improved, and the reset process can be completed at high speed.

In this embodiment, as shown in FIG. 11A, the fetch agent (second request execution means)
Fetch agent FCH for command control
1 (third request execution means) and a fetch agent FCH2 (fourth request execution means) for data transfer. The received packet to be passed to the fetch agent FCH1 for command control is stored in the FHC1 queue, and the fetch agent F for data transfer is stored.
The received packet to be passed to CH2 is stored in the FHC2 queue. Then, as shown in FIG.
After the received packets for command control stored in the CH1 queue are processed with priority, and after the packet processing for all the received packets in the FCH1 queue is completed, FIG.
As shown in FIG. 1 (B), the packet processing of the received packet stored in the FCH2 queue is started.

In this way, the processing by the fetch agent FCH1 is prioritized, and the command control processing by the fetch agent FCH1 can be easily interrupted during the data transfer processing by the fetch agent FCH2. Therefore, it is possible to check the remaining ink amount without waiting for the completion of printing.

3.2 Processing of Unwanted Packet at Bus Reset In IEEE 1394, when an electronic device is newly connected to the bus or when the electronic device is removed from the bus, a bus reset occurs. When a bus reset occurs, the topology information of the node is cleared, and all transactions that have not been completed when the bus reset occurs are canceled. Therefore, all packets received before the occurrence of the bus reset are invalidated.

However, as described above, the CPU operating on the peripheral device in which the data transfer control device is incorporated has a low processing capability. For this reason, the firmware operating on this CPU cannot process received packets at high speed, and a large number of unprocessed received packets exist in the data buffer. Therefore, when a bus reset occurs, it is necessary to perform a process of discriminating and discarding a packet before the occurrence of the bus reset from among these many unprocessed received packets. Therefore, the processing load of the firmware becomes excessive.

Therefore, in this embodiment, as shown in FIG. 12A, after analyzing the received packet written in the target data buffer, the analyzed received packet is stored in the queue without being processed immediately. Then, when there are no more received packets on the data buffer, the received packets stored in the queue are processed. When a bus reset occurs, a packet received before the bus reset occurs is discarded.

More specifically, as shown in FIG. 12B, while the received packet is being stored in the queue, the IEEE139
When a bus reset occurs on the bus No. 4, the queue of the received packet is cleared, and the received packet before the occurrence of the bus reset is discarded (in this case, the received packet on the data buffer may also be discarded). desirable). Also,
As shown in FIG. 12C, after all received packets are stored in the queue, even if a bus reset occurs during processing of the received packet, the queue of the received packet is cleared and the received packet is discarded. I do.

[0097] In this way, for the received packet that becomes unnecessary without performing the packet processing due to the bus reset, the packet processing does not need to be performed. Therefore, the time required for the bus reset process can be significantly reduced as compared with the comparative example of FIG. 7 in which packet processing is performed on all received packets. As a result, it is possible to prevent a situation in which the processing of the entire system is stalled by the bus reset processing, and to reduce the processing load on the firmware.

Further, if the received packets are discarded by clearing the queue, a large number of received packets before the occurrence of the bus reset can be discarded at once, so that the process of discarding received packets can be made more efficient. In particular, in the case where a large number of unprocessed received packets exist in the data buffer due to the low processing capacity of the CPU, the method of the present embodiment for discarding received packets by clearing the queue is a method of the present invention. It is very effective in improving efficiency.

4. Next, a detailed processing example of the present embodiment will be described with reference to FIGS.
This will be described with reference to the flowchart of FIG.

When an interrupt from the CPU (or link device) occurs, the cause of the interrupt is analyzed, and the analyzed interrupt cause is cleared (step S1).
Here, the interrupt factors include a packet reception interrupt, a bus reset occurrence interrupt, and a DMA to the printer.
There are a transfer end interrupt, a CPU timer interrupt, and the like.

Next, it is determined whether or not the analyzed interrupt factor is a packet reception interrupt (step S2). If it is not a packet reception interrupt, it is determined whether or not a bus reset generation interrupt is performed (step S2). Step S3).
If the interrupt is due to a bus reset, all of the agent queue and the transmission queue are cleared (step S4; see FIGS. 12B and 12C), and the received packet before the occurrence of the bus reset is discarded. .

Next, it is determined whether or not an interrupt factor from the CPU exists (step S5). If so, the interrupt factor is analyzed and the analyzed interrupt factor is cleared (step S6). ). Next, it is determined whether or not an unprocessed interrupt factor that has not been analyzed still exists (step S7). If it exists, the process returns to step S2. If not, the interrupt process ends.

If it is determined in step S2 that a packet reception interrupt has occurred, it is determined whether the received packet is a response packet of the initiator to the request packet transferred by itself (step S8 in FIG. 14). If the received packet is a response packet, processing relating to the response packet (pointer control of the storage location of the response packet in the data buffer, etc.) is performed (step S9).

Next, it is determined whether the received packet is a packet to be passed to the agent based on the analysis result of the packet (step S10). If the packet is to be passed to the agent, the received packet is stored in the queue of the corresponding agent as described with reference to FIGS. 9A and 9B (step S11). For example, received packets to be passed to the management agent are stored in the MNG queue, and received packets to be passed to the fetch agent are stored in the FCH queue.

Next, it is determined whether or not a bus reset has occurred (step S12). If a bus reset has occurred, all the agent queues and the transmission queue are cleared as described with reference to FIG. 12B (step S22). On the other hand, if not, it is determined whether or not the received packet to be stored in the queue still exists in the data buffer (step S1).
3) If it exists, return to step S11. Then, the processing of steps S11, S12, and S13 is repeated until there are no more received packets in the data buffer.

Next, after storing the received packet in the queue,
It is determined whether a bus reset has occurred (step S14). Then, if it occurs, FIG.
As described in (C), all the agent queues and the transmission queue are cleared (step S22). On the other hand, if not, as shown at C3 in FIG. 8, it is determined whether or not there is a process for the received packet stored in the queue (a process to be passed to the agent) (step S15). Then, when there is a process, FIG.
As described in (1), processing is performed from an agent queue having a higher priority (for example, an MNG queue) (step S1).
6).

Next, it is determined whether or not the received packet is a reset packet (a packet instructing a reset) (step S17). For example, in the case of a target reset, the agent analyzes the contents of the ORB to determine whether or not the packet is a reset packet. In the case of an agent reset or reset start, the agent can determine whether or not the packet is a reset packet by analyzing the write address of the packet.

If the received packet is a reset packet, the agent queue affected by the reset is cleared as described with reference to FIGS. 9C and 10C (step S18). For example, when the management agent is reset, both the MNG queue and the FCH queue are cleared. On the other hand, when the fetch agent is reset, only the FCH queue is cleared.

Next, it is determined whether there is a free space in the transmission buffer on the data buffer and there is a transmission request (step S19), and if there is, a packet is transmitted (step S20). Next, it is determined whether or not a bus reset has occurred (step S21). If it has occurred, all the agent queues and the transmission queue are cleared (step S22). On the other hand, if no error has occurred, the process returns to step S3 in FIG.

Then, steps S3 to S7, S2, S8
Steps S21 to S21 are repeated, and the received packets stored in the queue are sequentially processed one by one. That is, first, the queue having the highest priority (for example, the MNG queue)
Are sequentially processed one by one, and when the processing for all the received packets is completed, the queue having the second highest priority (for example, FCH1)
Process the received packets stored in the queue. When the processing of all the received packets in the queue is completed, the queue having the third highest priority (for example, FCH2)
Process the received packets stored in the queue. As described above, the processing is performed on all the received packets stored in the queue.

5. Electronic Device Next, an example of an electronic device including the data transfer control device of the present embodiment will be described.

For example, FIG. 15A shows an internal block diagram of a printer which is one of the electronic devices, and FIG. 16A shows an external view thereof. CPU (microcomputer) 51
0 controls the entire system. The operation unit 511 is for the user to operate the printer. ROM5
16 stores a control program, fonts, and the like.
The RAM 518 functions as a work area for the CPU 510. The display panel 519 is for notifying the user of the operation state of the printer.

Print data sent from a partner node such as a personal computer via the PHY device 502 and the data transfer control device 500 is sent directly to the print processing unit (printer engine) 512 via the bus 504. The print data is subjected to given processing in a print processing unit 512, and is printed and output on paper by a print unit (device for outputting data) 514 including a print header and the like.

FIG. 15B shows an internal block diagram of a scanner which is one of the electronic devices, and FIG. 16B shows an external view thereof. The CPU 520 controls the entire system. The operation unit 521 is for the user to operate the scanner. The ROM 526 stores a control program and the like, and the RAM 528 functions as a work area of the CPU 520.

An image of a document is read by an image reading unit (device for taking in data) 522 including a light source, a photoelectric converter, and the like, and the data of the read image is processed by an image processing unit (scanner engine) 524. .
Then, the processed image data is directly sent to the data transfer control device 500 via the bus 505. The data transfer control device 500 generates a packet by adding a header or the like to the image data, and transmits the packet to a partner node such as a personal computer via the PHY device 502.

FIG. 15C shows a CD which is one of the electronic devices.
FIG. 16C shows an internal block diagram of the RW drive, and FIG.
Fig. 2 shows its external view. The CPU 530 controls the entire system. The operation unit 531 is for the user to operate the CD-RW. The ROM 536 stores a control program and the like, and the RAM 538 functions as a work area of the CPU 530.

The reading / writing unit (device for taking in data or device for storing data) 533 comprising a laser, a motor, an optical system, etc.
The data read from 32 is input to a signal processing unit 534 and subjected to given signal processing such as error correction processing. Then, the signal-processed data is transferred to the bus 506.
Is sent directly to the data transfer control device 500 via the. The data transfer control device 500 generates a packet by adding a header or the like to this data, and the PHY device 50
2 to a partner node such as a personal computer.

On the other hand, data sent from the partner node via the PHY device 502 and the data transfer control device 500 is sent directly to the signal processing unit 534 via the bus 506. Then, given signal processing is performed on this data by the signal processing unit 534, and the reading and writing unit 53
3 is stored in the CD-RW 532.

In FIGS. 15A, 15B and 15C, in addition to the CPUs 510, 520 and 530, a CPU for data transfer control in the data transfer control device 500 may be provided separately. Good.

In FIGS. 15A, 15B and 15C, the RAM 501 (corresponding to a data buffer) is provided outside the data transfer control device 500.
May be incorporated in the data transfer control device 500.

If the data transfer control device according to the present embodiment is used in an electronic device, even if an error occurs in the data transfer control device or the electronic device and the data transfer control device is reset, the data transfer control device can be returned to a normal state in a short time. Will be able to return to Further, even when a new electronic device is connected to the bus and a bus reset occurs, the bus can be returned from the bus reset state in a short time, and a situation in which the entire system is stalled can be prevented.

If the data transfer control device of this embodiment is used in an electronic device, high-speed data transfer can be performed. Therefore, when the user gives a printout instruction using a personal computer or the like, printing is completed with a small time lag. Further, after the instruction to take in the image to the scanner, the user can view the read image with a small time lag. Also, CD-
It is possible to read data from the RW and write data to the CD-RW at high speed.

Further, by using the data transfer control device of the present embodiment in an electronic device, the processing load of the firmware operating on the CPU can be reduced, and an inexpensive CPU and a low-speed bus can be used. Further, since the cost and the size of the data transfer control device can be reduced, the cost and the size of the electronic device can be reduced.

The electronic apparatus to which the data transfer control device of the present embodiment can be applied is, for example, various optical disk drives (CD-ROM, DVD), magneto-optical disk drive (MO), hard disk drive, TV, etc. , VTR, video camera, audio equipment, telephone, projector, personal computer, electronic organizer, word processor and the like.

Note that the present invention is not limited to this embodiment,
Various modifications can be made within the scope of the present invention.

For example, the configuration of the data transfer control device of the present invention is particularly preferably the configuration shown in FIG. 6, but is not limited thereto.

The method for discarding the received packet is also preferably, but not limited to, the method described in the present embodiment.

In the present embodiment, the case where two or three queues are provided has been described. However, four or more queues may be provided.

It is particularly preferable that the present invention is applied to data transfer in the IEEE 1394 standard, but the present invention is not limited to this. For example, the present invention can be applied to data transfer based on a standard based on the same concept as IEEE 1394 or a standard developed from IEEE 1394.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layer structure of IEEE1394.

FIG. 2 is a diagram for explaining SBP-2.

FIG. 3 is a diagram for explaining an outline of a data transfer process of SBP-2;

FIG. 4 is a diagram for explaining command processing when data is transferred from an initiator to a target.

FIG. 5 is a diagram for explaining command processing when data is transferred from a target to an initiator.

FIG. 6 is a diagram illustrating a configuration example of a data transfer control device according to the present embodiment.

FIG. 7 is a flowchart illustrating a process according to a comparative example.

FIG. 8 is a diagram for describing a method of the present embodiment at the time of reset.

FIGS. 9A, 9B, and 9C are diagrams for explaining a method of preparing a plurality of queues and discarding unnecessary packets by clearing the queues.

FIGS. 10A, 10B, and 10C are diagrams for explaining a method of processing a queue with a higher priority with priority;

FIGS. 11A and 11B are diagrams for explaining a method of processing a queue of a fetch agent for command control with priority;

FIGS. 12A, 12B, and 12C are diagrams for explaining a method according to the present embodiment at the time of bus reset;

FIG. 13 is a flowchart illustrating a detailed processing example of the present embodiment.

FIG. 14 is a flowchart illustrating a detailed processing example of the embodiment;

FIGS. 15A, 15B, and 15C are examples of internal block diagrams of various electronic devices.

FIGS. 16A, 16B, and 16C are examples of external views of various electronic devices.

[Explanation of symbols]

Reference Signs List 10 data transfer control device 12 PHY device 14 link device 16 CPU 18 data buffer 20 firmware (F / W) 30 communication unit (COM) 32 packet analysis unit 34 packet processing unit 36 packet discarding unit 40 management agent (MNG; first) Request execution means) 50 fetch agent (FCH1; third (second) request execution means) 60 fetch agent (FCH2; fourth (second) request execution means) 70 print task unit (PRT) 100 personal computer 102 device Driver 104 data buffer 110 information storage medium

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shinichiro Fujita 3-5-5 Yamato, Suwa City, Nagano Prefecture Inside Seiko Epson Corporation (72) Inventor Akemi Toumi 3-3-5 Yamato Suwa City, Nagano Prefecture Seiko Epson F term in reference (reference) 5B077 DD02 NN02 NN08 5K030 HA08 KA03 LA03 LC18 LE05 MB15 5K033 CB17 CC01 DB13

Claims (11)

[Claims] 1. A data transfer control device for transferring data between a plurality of nodes connected to a bus, comprising: analyzing a received packet written in a data buffer of the own node; And a packet analyzing means for repeating the analysis of the received packet and storing it in the queue until there are no more received packets in the data buffer, and processing the received packets stored in the queue when the received packets in the data buffer are gone. Packet processing means; and packet discarding means for, when the processed received packet is a packet instructing reset, discarding a received packet that becomes unnecessary due to the reset among the received packets stored in the queue. A data transfer control device, characterized in that: 2. The packet discarding unit according to claim 1, wherein a plurality of queues are prepared as the queue, and the packet analysis unit stores the analyzed received packet in one of the plurality of queues. However, if the processed received packet is a packet instructing reset, the data transfer control device clears a queue in which the received packet which becomes unnecessary by reset is stored. 3. The method according to claim 1, wherein the first request execution unit receives a received packet from the packet processing unit and executes a request from another node, and receives the received packet from the packet processing unit. And a second request execution unit that executes a request from the node of the first request execution unit and resets itself when the first request execution unit is reset. The received packet to be passed to the request execution means is stored in a first queue, the received packet to be passed to the second request execution means is stored in a second queue, and the packet processing means A data transfer control device, wherein a received packet stored in a queue is processed with priority over a received packet stored in the second queue. 4. The packet processing device according to claim 3, wherein the packet discarding unit is configured to execute the first,
A data transfer control device for clearing both of the second queues. 5. The request execution device according to claim 3, wherein the second request execution device executes a command control request of an upper layer device, and the fourth request execution process executes a data transfer request. The packet analysis means stores the received packet to be passed to the third request execution means in a third queue, and stores the received packet to be passed to the fourth request execution means in a fourth queue. Data stored in a queue, wherein the packet processing means processes received packets stored in the third queue with higher priority than received packets stored in the fourth queue. Transfer control device. 6. A data transfer control device for transferring data between a plurality of nodes connected to a bus, comprising: analyzing a received packet written in a data buffer of the own node; Packet analysis means for repeatedly analyzing received packets and storing them in a queue until there are no more received packets in the data buffer, and a packet for processing the received packets stored in the queue when there are no more received packets in the data buffer A data transfer control device, comprising: a processing unit; and a packet discarding unit that, when a reset for clearing topology information of a node occurs, discards a received packet before the occurrence of the reset. 7. The data transfer control according to claim 6, wherein the packet discarding unit clears a queue storing received packets when a reset for clearing topology information of the node occurs. apparatus. 8. The method according to claim 6, wherein the reset for clearing the topology information of the node comprises the step of:
A data transfer control device, which is a bus reset defined in the EEE1394 standard. 9. A data transfer control device according to claim 1, wherein data transfer is performed in accordance with the IEEE 1394 standard. 10. A data transfer control device according to claim 1, wherein the data transfer control device performs a given process on data received from a partner node via the data transfer control device and a bus. And a device for outputting or storing the data. 11. The data transfer control device according to claim 1, wherein the data transfer control device and a device for performing a given process on data to be transferred to a partner node via a bus. And an apparatus for capturing data.