JP2001186111A - Bit-synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a bit-synchronization circuit which is compact and low cost, operated at a high speed region of Gb/s or higher, capable of synchroniza tion within 10-bit, with a jitter suppression effect that prevents synchronization error even from a signal, whose SNR is deteriorated. SOLUTION: The bit synchronization circuit 1 consists of a polyphase clock generating circuit 2, phase comparator 3, identification circuit 4, majority phase decision circuit 5, data selection circuit 6, clock frequency divider circuit 7, storage circuit 8, and delay circuit 9. The majority phase decision circuit 5 applies time series majority decision to phase comparison outputs, to decide a clock having a level transition timing in the middle of a level transition timings adjacent to each other in input data from the data identified by clocks with different phases. The data identified by the decided clock at the identification circuit 4 are selected by a selection circuit 6, which provides the output of the selected data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a large-scale optical switching network in a large-sized computer, a large-capacity ATM switch and an IP router, and more particularly to a bit synchronization circuit of an optical receiver.

[0002]

2. Description of the Related Art In a large-capacity optical interconnection network using an optical space switch, a signal from each node is switched by the optical space switch. Since the transmission rate per port of this large-capacity optical interconnection network is several Gb / s or more and the scale is 100 × 100 or more, it is difficult to make the distances between the nodes equal in mm order and to synchronize them.

Therefore, in an optical receiver, it is necessary to reestablish bit synchronization when an optical switch is switched by a bit synchronization circuit. It is desired that the synchronization time be within 10 bits so as not to lower the throughput.

In a large-capacity optical interconnection network using an optical space switch, a signal / noise ratio (SNR) of a signal light is determined by spontaneous emission (ASE) of an optical switch element or an optical amplifier used for compensating a loss of a path. Deteriorates. Since the deterioration of the SNR increases the jitter with respect to the time component, it is necessary to consider the influence of the jitter in the receiver.

Further, since the scale is as large as 100 × 100 or more and 100 or more optical receivers are used, it is required to be small in size, low in cost and low in power consumption. As a conventional bit synchronization method, a method using a phase locked loop (PLL), a method using a timing tank, a method using a gated oscillator (Gated VCO), and a method using a multi-phase clock are known.

In the PLL method, the phase of a received signal is compared with that of a voltage controlled oscillator (VCO) output clock, and the voltage of the VCO is controlled so that the phase difference is eliminated. The synchronization time depends on the response time of the loop and is generally
For an order of 10 Gb / s, it is about 10,000 bits.

In the method using a timing tank, the received signal is differentially folded, and the output is passed through a band-pass filter (BPF) to perform bit synchronization. It is known that the synchronization time takes approximately Q0 bits when the Q value of the BPF is Q0. Generally, a Q value of 100 or more is used in order to obtain a clock with little jitter, so that a synchronization time also takes 100 bits or more.

The gated VCO uses an open loop in which rising and falling signals of received data are used as gate inputs of the gated VCO, and can be synchronized with one bit, but has no jitter suppression effect.

On the other hand, in a bit synchronization circuit using a multi-phase clock, synchronization at several bits and suppression of jitter are possible. For example, Japanese Patent Application Laid-Open No. 7-193562 discloses a "bit synchronization circuit" in which a clock multiphase circuit that outputs a plurality of N-phase clock signals from a reference clock, a received data, and a multiphase clock output from the clock multiphase circuit are input. A clock selection circuit for selecting a clock used for identification, an elastic store (memory) for reading received data with a clock output from the clock selection circuit and reading with a reference clock, and using a clock selected by the clock selection circuit. Bit synchronization is performed by identifying received data by using the reference clock in the elastic store and always obtaining the same phase output.

As another example of a circuit for selecting an identification clock from other multi-phase clocks, there is Japanese Patent Application Laid-Open No. 4-347793, "Phase Synchronized Clock Extraction Circuit". This circuit is configured to select a clock to be used for discrimination from multi-phase clocks as in Japanese Patent Application Laid-Open No. 7-193562. In this circuit, however, as a countermeasure when a selection error occurs due to noise or the like during clock selection. Once a clock is selected, a majority decision circuit or an averaging circuit determines whether or not the clock pulse is correctly selected from the time series selection result for the same pulse train, and determines a clock to be actually used. I have.

The logic circuit for selecting a clock and the circuit for performing a majority decision in this circuit detect a change point (rising or falling) of the input data and use a pulse corresponding to the change point as a clock. If the signal speed is A (b / s), the speed is twice as high as 2 (H / H).
It operates with the clock of z).

As an example of a circuit for selecting an identification clock from other multi-phase clocks, there is Japanese Patent Application Laid-Open No. H11-215110 entitled "Bit Synchronization Circuit". In this circuit, a plurality of clocks having different phases synchronized with an input reference clock are generated by a multi-phase clock generation circuit, and an identification circuit identifies input data using the plurality of clocks, while each of the plurality of clocks is identified. A phase comparison circuit determines the phase relationship between the input data to be identified and the clock having the optimal phase, and selects and outputs the input data identified by the optimal phase clock from the identification circuit. ing.

[0013]

The conventional bit synchronization circuit of the type which selects a clock from a multi-phase clock requires an elastic store. However, an elastic store which operates in a high-speed region of several Gb / s or more is required. Is difficult to realize.

When serial / parallel conversion (S / P conversion) is performed up to the speed at which the elastic store operates and bit synchronization is performed using the elastic store, the number of elastic stores required for parallel development is required. There is a problem that the size of the circuit cannot be reduced due to an increase in circuit size.

In the case of using a pulse corresponding to a change point of input data as a clock of a logic circuit, if the signal speed is A (b / s), the speed is twice as high as 2 A (Hz).
Clock. In a large-capacity optical interconnection network using an optical space switch, it is necessary to increase the capacity per port as much as possible in order to increase the capacity.

Therefore, the transmission speed per port is almost equal to the upper limit of the operation speed of the circuit, and is often 70% or more of the upper limit. Therefore, there is a problem that it is difficult to operate the circuit with a clock having twice the speed. Further, when the transmission speed per port is reduced, there is a problem that the capacity of the entire network is reduced.

Further, the phase synchronization circuit which determines a clock having an optimum phase relationship from the multi-phase clocks and selects and outputs identification data based on the determined clock from the identification circuit is provided in the high-speed domain. Although operation is possible and sensitivity degradation due to phase shift does not occur, when the phase comparison circuit determines the phase relationship between each of the plurality of clocks and the input data to be identified, jitter occurs in the input data, If the SNR is degraded, the optimum phase clock may not be determined, and a synchronization error may occur.

It is an object of the present invention to provide a compact and low-cost Gb /
It is an object of the present invention to realize a bit synchronization circuit that operates in a high-speed region of s or more, can perform synchronization within 10 bits, has a jitter suppression effect, and can prevent a synchronization error even for a signal with degraded SNR.

[0019]

A bit synchronization circuit according to the present invention comprises: a multi-phase clock generation circuit for generating a plurality of clocks having different phases synchronized with an input reference clock;
A plurality of identification circuits for identifying input data using clocks of different phases output from the multi-phase clock generation circuit as data identification clocks; and each of the input data and different phases output from the multi-phase clock generation circuit. A phase comparison circuit that performs a phase comparison with a clock, and for each of the phase comparison outputs of the plurality of phase comparison circuits, a majority logic of a predetermined number of time-series values that are continuous is adopted, whereby the plurality of phase comparison circuits are compared. A majority phase determining circuit for determining each output value, and levels of the input data adjacent to each other from among the plurality of phase clocks based on output values of the plurality of phase comparison circuits determined by the majority phase determining circuit. A clock at which a level transition timing occurs at the center of the transition timing is selected as the data identification clock, and the selected clock is selected. Characterized in that it is composed of a data selection circuit for outputting the input data identified by the data identification clocks.

In the above-mentioned bit synchronization circuit, the majority decision phase determination circuit is operated by a frequency-divided clock of the reference clock.

Further, the bit synchronization circuit includes holding means for holding a decision result of the majority decision phase circuit in response to an external control signal, and controls the selection means in accordance with a holding output of the holding means. Features.

Further, the bit circuit includes delay means for adjusting output timings from the identification means.

In the above-mentioned bit synchronization circuit, the plurality of identification circuits receive the input data as a data input and the plurality of D-type F / Fs each receiving the clock as a clock input.
F.

In the above-mentioned bit synchronization circuit, the phase comparator is constituted by a plurality of D-type F / Fs each of which receives the clock as a data input and receives the input data as a clock input. .

[0025]

FIG. 1 is a block diagram showing a first embodiment of the present invention. In this embodiment, the number of clock phases is 4, and the data transmission speed is 10 Gb / s. The bit synchronization circuit 1 of the present embodiment comprises a multi-phase clock generation circuit 2, a phase comparator 3, an identification circuit 4, a majority decision phase determination circuit 5, a data selection circuit 6, a 1/2 clock frequency division circuit 7, and a holding circuit 8. , And a delay circuit 9.

FIGS. 2 to 8 show the multi-phase clock generation circuit 2, the phase comparator 3, the identification circuit 4, the majority decision phase determination circuit 5, the data selection circuit 6, the holding circuit 8,
FIG. 3 is a block diagram illustrating a configuration example of a delay circuit 9; 9 to 10 are timing charts according to the present embodiment.

The multi-phase clock generation circuit 2 includes a ring oscillator 201, a phase detector 202,
The input 1 is constituted by a low-pass filter 203.
Synchronized with the 0 GHz reference clock (Ref.CLK) and the phase is 9
Four-phase clocks PH1, PH2, PH shifted by 0 degrees
3, a phase locked loop (PLL) circuit that outputs PH4.

Since the phase difference between PH1 and PH3 is 180 degrees, PH3 is the inverse of PH1. The same applies to PH2 and PH4. Therefore, since it is sufficient to perform a phase comparison between PH1 and DATA and a phase comparison between PH2 and DATA, the phase comparator 3 outputs DATA and PH1 and DATA and PH1.
This is a configuration for performing a phase comparison of 2. That is, when the multi-phase clock generation circuit 2 outputs a 2N-phase (N is a positive integer) clock, an optimum data discrimination phase can be obtained by comparing a predetermined N phase of the 2N phases with data. Can be determined.

As shown by reference numeral 300 in FIG. 3, the phase comparator 3 includes D-type flip-flops (F / F) 301 and 302.
, The phase 1 (PH1) and phase 2 (PH2) clocks of the output of the multiphase clock generation circuit 2 are input to the data input, and DATA is input to the clock input. The clocks PH1 and DATA are compared with each other, and the clocks PH2 and DATA are compared with each other in phase. If the respective clocks are advanced with respect to the rise of DATA, "1" is output to the PDs 1 and 2 if they are delayed.

As shown in FIG. 4 at 400, the identification circuit 4
DATA is input to the data inputs of the D-type F / Fs 401 to 404, and four types of clocks (PH1 to PH4), which are the outputs of the clock generation circuit 2, are input to the clock inputs, and DATA is input by the respective clocks. And outputs the identification data to Q1 to Q4. Since the phase margin of the D-type F / F used here is 180 degrees or more, DATA can be accurately identified by any of the four-phase clocks.

As shown at 500 in FIG. 5, the majority phase decision circuit 5 performs a majority decision on the time series of the output of the PD1 and outputs a selection output S'1, and a majority decision of the time series of the output of the PD2. Block 5 that outputs S'2
20 and the result S ′ of block 510 and block 520
The EX-OR 508 outputs an exclusive OR of S'1 and S'2 and outputs a selection output S'3. Since block 510 and block 520 have the same configuration, block 5
Only the configuration 10 will be described.

In this example, the configuration is such that a 3-bit majority decision is taken. The block 510 includes a three-stage shift register composed of three F / Fs 511, 512, and 513 that operate at ク ロ ッ ク clock, and a 3-bit majority logic circuit 501. The 3-bit majority circuit 501 has an F / F 511
A gate 514 for ANDing the output SR11 and the F / F513 output SR13, the F / F512 output SR12 and the F / F5
Gate 515, F / F for ANDing 13 output SR13
AN of 511 output SR11 and F / F512 output SR12
D taking gate 516 and AND gates 514 and 51
It comprises a gate 517 that takes the OR of 5,516.

Next, the operation of the present embodiment will be described with reference to the time charts of FIGS. As shown in FIG. 9, when the input data (DATA) rises at a near timing, the optimum clock position for identifying the input data is almost in the middle of the time slot of the input data (about the level transition timing of the input data adjacent to each other). The clock PH3 rises at the center. At this time, in the phase comparator 3, the clocks PH1 and PH2 are compared in phase with the input data at the following timing, so that the output PD1 is "1" and the PD2 is "0".

When the outputs PD1 and PD2 are input to the majority decision phase determination circuit 5 (FIG. 5), each of the blocks 51
0, 520, the outputs of SR11 to SR13 are all “1”, and SR21 to SR23
Are all "0", so that S'1 obtained by majority decision of the output of each stage of each 3-bit shift register becomes "1" and S'2 becomes "0". Therefore, S'1 and S '
The EX-OR output S'3 of "2" becomes "1".

These S'1, S'2 and S'3 are held when the control signal BSEN becomes "1" in the holding circuit 8 (FIG. 7), and the selection signals S1, S2 and S3 are output. . The data selection circuit 6 (FIG. 6) selects one of the outputs Q1 to Q4 of the identification circuit 4 according to the selection signals S1, S2, S3. In this example, S1 is "1", S2 is "0",
Since S3 is "1", Q3 identified by the clock PH3 rising almost in the middle of the DATA time slot is selected.

Similarly, in FIG. 9, when the input data rises at each of the following timings, the outputs (PD1, PD2) of the phase comparator 3 are ("1",
“1”), (“0”, “1”), (“0”, “0”). Therefore, the selection signals (S1, S2, S3) are (“1”, “1”, “0”), (“0”, “1”,
"1"), ("0", "0", "0"), and Q4, Q1, and Q2 are selected from the identification circuit, respectively.

Further, the transition timing of the output data is made constant by the delay circuit 9 (FIG. 8) regardless of which output of Q1 to Q4 is selected.

Next, the operation of the present invention when an erroneous signal is output from the phase comparator due to the influence of jitter will be described with reference to the timing chart of FIG. Note that FIG.
Then, the optimal clock phase for identifying DATA is DATA
This shows a case where PH3 that rises almost in the middle of a time slot is selected.

The output PD1 of the phase comparator 3 (FIG. 3) comparing the phases of DATA and PH1 is normally "1" as shown in FIG. 10, but the rise of DATA and PH1 is so close that the output PD1 is affected by the jitter of DATA. There is a moment when it becomes “0”.

The output of PD1 is determined by majority decision phase decision circuit 5.
(FIG. 5), it is passed to the shift register of block 510, and the waveform of each stage becomes as shown in SR11 to SR13, and S'1 which is the majority decision of the output of each stage of this 3-bit shift register Becomes "1".

The edges of DATA and PH2 are not close to each other, and the output PD2 of the phase comparator 3 which compares the phases of DATA and PH2 is "0" in this example, and the output S'2 of the majority circuit is also "0". , S′1 and S′2 have an EX-OR output S′3 of “1”. Therefore, the selection signals (S1, S1
(2, S3) becomes ("1", "0", "1"), and a normal selection signal is output.

As described above, by providing the majority decision phase determining circuit, it is possible to absorb an instantaneous error determination of the phase comparator due to jitter or the like, and to prevent a synchronization error due to jitter or SNR degradation. .

When a packet (DATA) of a new phase is received by switching of an optical switch or the like, the external control signal BSEN is set to "0" once so that the majority decision of 3 bits becomes effective in the new phase. Bit synchronization can be established by setting BSEN to "1" after receiving three or more rising edges of DATA and holding it during packet reception.

FIG. 11 is a block diagram showing a second embodiment of the present invention. In this embodiment, the number of clock phases is 4, and the data transmission speed is 10 Gb / s. The bit synchronization circuit 11 of the present embodiment includes a multi-phase clock generation circuit 12,
Phase comparator 13, identification circuit 14, majority phase determination circuit 1
5, a data selection circuit 16 and a delay circuit 19.

FIGS. 12 to 14 are block diagrams each showing a configuration example of the multiphase clock generation circuit 12, the identification circuit 14, and the delay circuit 19 in FIG. FIG.
FIG. 3 is a diagram illustrating a timing chart of the present embodiment.

The multi-phase clock generation circuit 12 corresponds to 21 in FIG.
0, buffers 211, 212 and 25 ps
This is a circuit constituted by a delay circuit 213 (corresponding to 90 degrees at 10 GHz) and outputting four-phase clocks whose phases are shifted by 90 degrees. The phase comparator 13, the majority decision phase decision circuit 15, and the data selection circuit 16 have the same configuration as in the first embodiment.

As shown in FIG. 13, the discriminating circuit 14 has three-stage latch Master-Slave-Master type F / Fs 411 and 413, and a normal two-stage latch Master-Slave type F / F 412 and 414.
And the output timing of the F / F 411 and the F / F
The output timing of 412 is the same. Similarly, F / F
The output timing of 413 and the output timing of F / F 414 are the same.

In the delay circuit 19, as shown at 910 in FIG. 14, 90-degree delays 911 and 912 are connected to the Q1 and Q3 outputs. Therefore, Q′1 to Q′4 have the same output timing due to the combination of the identification circuit and the delay circuit. The majority phase determination circuit operates by an external control signal BSEN, but the internal operation is the first operation.
This is the same as the embodiment.

As shown in FIG. 15, when a signal is input to BSEN such that a pulse of 5 bits corresponding to 1/2 clock and "1" follows, Q3 identified by clock PH3 rising almost in the middle of the DATA time slot is generated. It can be seen that Q3 is selectively output and continues to output Q3 while BSEN is "1".

When a packet (DATA) of a new phase is received by switching of an optical switch or the like, the external signal BSEN is set to "0" once, and BSEN is set so that a 3-bit majority decision becomes valid in the new phase. In this case, a signal in which "1" continues during the packet reception after a pulse of 3 bits or more may be input.

In the above description, the number of clock phases is four, but this can be an arbitrary number of two or more phases. Although the data rate was set to 10 Gb / s, it was 5 G at 1 Gb / s.
There is no problem with Gb / s. The number of bits for performing the majority decision may be 5 bits. Even if the divided clock is not 1/2,
4 is acceptable. As long as the above function is satisfied in the above configuration, the number of phases and the speed used are free, and the above description does not limit the present invention.

[0052]

According to the present invention, Gb is small in size and low in price.
/ S, which operates in a high-speed region of not less than / s, can achieve synchronization within 10 bits, has a jitter suppressing effect, and can realize a bit synchronization circuit that prevents a synchronization error even for a signal with degraded SNR. A large-capacity optical interconnection network using switches can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a multi-phase clock generation circuit in FIG.

FIG. 3 is a block diagram illustrating a configuration of a phase comparator in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of an identification circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a majority decision phase determination circuit in FIG. 1;

FIG. 6 is a block diagram showing a configuration of a data selection circuit in FIG. 1;

FIG. 7 is a block diagram illustrating a configuration of a holding circuit in FIG. 1;

FIG. 8 is a block diagram illustrating a configuration of a delay circuit in FIG. 1;

FIG. 9 is a time chart for explaining the operation of the first embodiment.

FIG. 10 is a time chart for explaining the operation of the first embodiment.

FIG. 11 is a block diagram showing a second embodiment of the present invention.

12 is a block diagram showing a configuration of a multi-phase clock generation circuit in FIG.

FIG. 13 is a block diagram illustrating a configuration of an identification circuit in FIG. 11;

FIG. 14 is a block diagram showing a configuration of a delay circuit in FIG. 11;

FIG. 15 is a time chart for explaining the operation of the second embodiment.

[Explanation of symbols]

1, 11 bit synchronization circuit 2, 12, 200, 210 polyphase clock generation circuit 201 ring oscillator 202 phase detector 203 low-pass filter 211, 212 buffer 213 delay circuit 3, 13, 300 phase comparator 301, 302 D type F / F 4, 14, 400, 410 Identification circuit 401, 402, 403, 404 D-type F / F 411, 413 Master-Slave-Master D-type F / F 412, 414 Master-Slave D-type F / F 5, 15, 500 majority decision phase decision circuit 501, 502 majority decision logic circuit 510, 520 circuit block 511, 512, 513, 521, 522, 523 shift register F / F 514, 515, 516, 524, 525, 526 A
ND gate 517, 527 3-input OR gate 508 EX-OR gate 6, 16, 600 Data selection circuit 601, 602, 603 2: 1 selector 7 1/2 clock divider 8 Holding circuit 9, 19, 900, 910 Delay circuit

Claims (7)

[Claims] 1. A multi-phase clock generating means for generating a plurality of clocks having different phases synchronized with an input reference clock, and a data identification clock for generating a plurality of clocks having different phases output from the multi-phase clock generating means. A plurality of data identification means for respectively identifying input data; a plurality of phase comparison means for performing a phase comparison between the input data and a plurality of mutually different phase clocks output from the multi-phase clock generation means; A majority decision phase decision means for determining each output value of the plurality of phase comparison means by adopting majority logic of a predetermined number of successive time-series values for each phase comparison output of the phase comparison means; Based on the output values of the plurality of phase comparison means determined by the phase determination means, Data selection means for selecting, as the data identification clock, a clock in which a level transition timing occurs at the center of adjacent level transition timings of the input data, and outputting the input data identified by the selected data identification clock And a bit synchronization circuit comprising: 2. The multi-phase clock generation means is 2N (N is a positive integer) phase multi-phase clock generation means, and the plurality of phase comparison means and the majority decision phase determination means are the 2N-phase clock generation means.
2. The bit synchronization circuit according to claim 1, further comprising means for outputting a phase comparison value of predetermined N phases of the phases. 3. The bit synchronization circuit according to claim 1, wherein said majority phase determining means operates by a frequency-divided clock of said reference clock. 4. A storage device for storing a determination result of the majority phase determination unit in response to an external control signal,
4. The bit synchronization circuit according to claim 1, wherein the selection unit controls the selection of the data identification clock in accordance with a holding output of the holding unit. 5. The bit synchronization circuit according to claim 1, further comprising a delay unit for adjusting output timings from said identification unit. 6. A plurality of DF / Fs wherein said plurality of identification circuits receive said input data as a data input and each of said clocks as a clock input.
The bit synchronization circuit according to any one of claims 1 to 5, 7. The phase comparator according to claim 1, wherein each of said clocks is a plurality of DF / Fs each having a data input and said input data being a clock input.
The bit synchronization circuit according to any one of the above.