JP2001186050A - Reception terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception terminal that can reduce power consumption by a path search circuit and a timing generating circuit in a timing control circuit. SOLUTION: The reception terminal consists of a wireless circuit 2 that receives a signal via an antenna 1 and outputs the received signal, a finger circuit 3 that receives this received signal, a timing control circuit 5, and a rake circuit 4 that synthesizes only valid paths. The finger circuit 3 includes a plurality of inverse spread circuits 6 and a plurality of level measurement circuit 7. The timing control circuit 5 includes a delay profile circuit 15, a path search circuit 16 and a timing generating circuit 17. Finger valid/invalid information from the level measurement circuit 7 stops the operation clock to the timing generating circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a receiving terminal device, and more particularly to a receiving terminal device for receiving signals from a plurality of propagation paths such as a portable radio receiver.

[0002]

2. Description of the Related Art The spread of receiving terminal devices such as mobile phones has been remarkable. Therefore, technical development of such a receiving terminal device or wireless communication device is extremely active, and competition among a plurality of manufacturers is fierce. In particular, reduction in size and weight and reduction in power consumption, that is, extension of continuous operation time by a built-in battery have become major development issues.

[0003] The prior art relating to such a receiving terminal device is as follows.
For example, Japanese Patent Application Laid-Open No. 6-125329 entitled "Diagnosis apparatus and multipath signal selection method",
No. 732, entitled "R in Direct Spread CDMA Transmission System".
AKE receiver ”and“ CD of JP-A-11-8568 ”
Signal receiving apparatus in MA communication system "
251962, "Cellular system, mobile portable device, base station device, optimal path detection method and device"
And Japanese Patent Application Laid-Open No. 11-266180, entitled "Array Antenna System for Wireless Base Station".

FIGS. 5 and 6 show a conventional CDMA (Code).
FIG. 3 is a block diagram illustrating a configuration of a receiving terminal device of a Division Multiple Access (Code Division Multiple Access) system. FIG.
6 shows the overall configuration of the receiving terminal device, and FIG.
The detailed configuration of the timing control circuit therein is shown together with its peripheral circuits.

First, a description will be given with reference to FIG. This conventional receiving terminal device includes an antenna 30, a radio circuit 31, a finger circuit 32, a rake circuit 35, and a timing control circuit 36. The finger circuit 32
Is composed of a plurality of despreading circuits 33a to 33n and level measuring circuits 34a to 34n. Wireless circuit 31
Are input to the despreading circuits 33a to 33n of the finger circuit 32 and the timing control circuit 36. The timing control circuit 36 outputs a reference timing pulse to each of the despreading circuits 33a to 33n of the finger circuit 32. Outputs of the despreading circuits 33a to 33n are supplied to a rake circuit 35 via level measuring circuits 34a to 34n. That is, in the receiving terminal device of FIG.
Of the received signal output from the
Despread with the spread data through n. Then, based on the data after the despreading, the level measurement circuits 34a to 34a
In n, the SIR is measured, and the despread data and the measured SIR are output to the rake circuit 35.

On the other hand, as shown in FIG. 6, a timing control circuit 36 includes a delay profile block 3 including a plurality of Delayprofile circuits 37a to 37n.
7, a timing block 39 including a path search circuit 38 and a plurality of timing generation circuits 39a to 39n. The delay control circuit 36
An operation clock is supplied from the crystal oscillator 40 to the le block 37, the path search circuit 38, and the timing block 39. Regarding the received signal output from the radio circuit 31, each Delayprofile circuit 3 of the Delayprofile block 37
In 7a to 37n, correlation with known data is obtained while shifting the phase. Then, the correlation data for each phase is output to the path search circuit 38. The path search circuit 38 searches for a peak phase from the correlation result for each phase, and outputs the phase information to the timing generation circuit 3 of the timing block 39.
Output to 9a to 39n. Timing generation circuit 39a
In steps 39 to 39n, the reference timing pulse signal is updated according to the phase information.

[0007]

However, in the above-mentioned prior art, the power consumption is increased because the path search circuit operates regardless of the validity of the path determined by the level measurement circuit. There has been a problem that the continuous operation time of the built-in battery is relatively short.

Accordingly, an object of the present invention is to provide a receiving terminal device capable of reducing the power consumption of such a receiving terminal device, in other words, the continuous operation time of the built-in battery is relatively long and the size can be reduced. It is.

[0009]

Means for Solving the Problems To solve the above-mentioned problems, a receiving terminal device according to the present invention employs the following characteristic configuration.

(1) A plurality of despreading circuits for receiving a signal received via an antenna and subjected to radio processing by a radio circuit, despreading by a plurality of despreading circuits and outputting despread data, In response to the clock from the control circuit,
A receiving terminal comprising: a finger circuit having a plurality of level measurement circuits for measuring the SIR level, receiving an output from each despreading circuit; and a rake circuit receiving the output from the finger circuit and synthesizing the despread data. In the apparatus, controlling the maximum number of paths to be searched in the path search based on the SIR level from the plurality of level measurement circuits,
2. The receiving terminal device according to claim 1, wherein the rake circuit combines only valid paths.

(2) SI from the plurality of level measuring circuits
The receiving terminal device according to (1), wherein when the R level is lower than a predetermined threshold value, the level measurement circuit of the finger circuit notifies path control information to the timing control circuit to change the maximum number of searches for the path.

(3) The path search circuit has a path valid /
The receiving terminal device according to the above (1), which searches for peaks for the number of valid paths for a predetermined time from the invalid information.

(4) The receiving terminal device according to (1), wherein the path search circuit searches for the peak again after a predetermined time has elapsed.

(5) a radio circuit connected to the antenna;
A finger terminal and a timing control circuit to which a reception signal from the radio circuit is input, and a rake circuit connected to an output side of the finger circuit, wherein the reception terminal device receives signals from a plurality of propagation paths, A receiving terminal device, wherein path valid / invalid information output from a level measuring circuit of the finger circuit according to an electric field level of the received signal is input to the timing control circuit.

(6) The receiving terminal device according to (5), wherein the maximum number of peaks searched by a path search circuit included in the timing control circuit is adjusted based on the path valid / invalid information from the finger circuit.

(7) The receiving terminal device according to (5), wherein the operation clock to a plurality of timing generation circuits included in the timing control circuit is selectively stopped according to the path valid / invalid information.

(8) The receiving terminal device according to (7), wherein operation clocks of the timing generation circuit and the path search circuit are stopped according to the path valid / invalid information.

(9) Each of the circuits in the timing control circuit is supplied with a clock from a crystal oscillator (5).
The receiving terminal device according to any one of (8) to (8).

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a receiving terminal device according to the present invention will be described below in detail with reference to the accompanying drawings.

The receiving terminal device according to the present invention is, for example, a CDM.
When receiving signals from a plurality of propagation paths in the A-system receiving terminal device, the effectiveness of the propagation path is determined from the strength of the electric field level of the received signal from each propagation path by the finger circuit, and the number of effective paths is determined. The operation clock of the path search circuit is changed accordingly to reduce power consumption.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a receiving terminal device according to the present invention. This receiving terminal device includes an antenna 1, a radio circuit 2, a finger circuit 3, a rake circuit 4, and a timing control circuit 5 similar to the conventional receiving terminal device shown in FIG. The finger circuit 3 includes a plurality of despreading circuits 6a to 6n and level measuring circuits 7a to 7n. The received signal from the wireless circuit 2 is input to each of the despreading circuits 6 a and the timing control circuit 5 of the finger circuit 3. The outputs of the despreading circuits 6a to 6n are output from the level measuring circuits 7a to 7
The data becomes despread data via n and is input to the rake circuit 4 and the timing control circuit 5. The timing control circuit 5 outputs a reference timing pulse to the despreading circuits 6a to 6n of the finger circuit 3. Here, the finger circuit 3 performs despreading of the received signal output from the wireless circuit 2 and measurement of the SIR level. When the SIR level is lower than a certain threshold value, path valid / invalid information is notified from the level measuring circuits 7a to 7n of the finger circuit 3 to the timing control circuit 5, as described later. Then, the maximum number of paths searched is changed according to the path valid / invalid information, and the operation clock is suppressed.

FIG. 2 is a block diagram showing a detailed configuration of the timing control circuit 5 shown in FIG. 1 and its peripheral circuits. The timing control circuit 5 includes a plurality of delay profiles.
Delayprofile block 15 including circuits 15a to 15n
And the path search circuit 16 and the plurality of timing generation circuits 1
And a timing block 17 including 7a to 17n. Each of these circuits 15 of the timing control circuit 5
A reference clock signal is supplied from the crystal oscillator 14 to the devices 17 to 17. The finger valid / invalid information from the finger circuit 3 is input to the path search circuit 16 of the timing control circuit 5 and the timing generation circuits 17a to 17n of the timing block 17.

In the receiving terminal device of the present invention, the level measuring circuits 7a to 7n of the finger circuit 3 determine the strength of the SIR level of the received signal. When the SIR level is equal to or smaller than a predetermined threshold, the path control circuit notifies the path search circuit 16 of the timing control circuit 5 of path valid / invalid information and changes the maximum number of paths searched by the path search circuit 16. Is provided.

The finger circuit 3 is connected to the rake circuit 4, the radio circuit 2 and the timing control circuit 5, and uses the timing pulse signal notified from the timing circuit 5 as a trigger to trigger a reception signal output from the radio circuit 2. Take in. Thus, the received signal acquired is
The despreading with the spread data is performed by the despreading circuits 6a to 6n of the finger circuit 3, and the level measuring circuits 7a to 7n are despread.
n is notified of the despread data. In the level measurement circuits 7a to 7n, the despread data of the despread circuits 6a to 6n are used.
Perform SIR measurement. The measured result is compared with the above-described threshold value, and information for determining whether the despread data is valid or invalid is output to the rake circuit 4 and the timing control circuit 5. The timing control circuit 5 is connected to the finger circuit 3, and outputs a reference timing pulse signal to the despreading circuits 6a to 6n every 10 ms, for example.

Next, referring to FIG. 2, each Delayprofi of the Delayprofile block 15 constituting the timing control circuit 5 will be described.
The le circuits 15a to 15n correlate with the reception signal output from the radio circuit 2, and output the correlation result to the path search circuit 1.
Notify 6. Therefore, the path search circuit 16
The peak value of the correlation result is searched from the correlation results notified from the rofile circuits 15a to 15n, and the phase information of each peak value is notified to the timing generation circuits 17a to 17n of the timing block 17. The path search circuit 16 changes the maximum number of peak value searches according to the path valid / invalid information output from the level measuring circuits 7a to 7n of the finger circuit 3. The timing generation circuits 17a to 17n transmit, for example, 10
Output at ms intervals. According to the phase information of the peak value notified from the path search circuit 16, the timing control circuit 5
Adjust the phase of the reference timing pulse from. The crystal oscillator 14 is connected to each circuit of the timing control circuit 5 and supplies an operation clock.

Next, the operation of the receiving terminal shown in FIGS. 1 and 2 will be described in detail. Normally, the finger circuit 3 despreads the received signal output from the radio circuit 2 via the antenna 1 by the despreading circuits 6a to 6n, and outputs the despread data to the level measuring circuits 7a to 7n. The level measuring circuits 7a to 7n calculate the SI
The R measurement is performed, and the rake circuit 4 is notified of the despread data and the SIR measurement result. The rake circuit 4 synthesizes the despread data output from the finger circuit 3.

The timing control circuit 5 converts the received signal output from the radio circuit 2 into a delay profile block 15.
The known profile and the received signal are correlated by the delay profile circuits 15a to 15n while shifting the phase. And
The correlation result for each shifted phase is output to the path search circuit 16. The path search circuit 16 is a delay profile circuit 1
Some peak phases are searched from the correlation result with the known data whose phases are shifted from 5a to 15n, and each phase information is searched for in the timing generation circuit 1 of the block 17.
Notify 7a to 17n. Therefore, the timing generation circuits 17a to 17n adjust the phase of the reference timing pulse according to each phase information.

In the present invention, the level measuring circuits 7a to 7n
In the step, the SIR measurement result is compared with a threshold. When the SIR level falls below the threshold, the path search circuit 16 and the rake circuit 4 are notified that this path is invalid. It is assumed that the path search circuit 16 searches for the number of valid paths for a certain period of time from the path valid / invalid information. The path search circuit 16 also has a function of searching for peaks again for the despreading circuits 6a to 6n after a predetermined time has elapsed. The rake circuit 4 combines only valid paths.

Next, a description will be given with reference to the flowchart of FIG. The despreading circuits 6a to 6n despread the received signal output from the wireless circuit 2 and output despread data to the level measurement circuits 7a to 7n (step A).
1). The despreading circuits 6a to 6n take in the received signals by using, for example, a pulse signal every 10 ms output from the timing control circuit 5 as a trigger. At this time, a process of performing despreading of the spread data and the fetched data, demodulating the spread data into data in symbol units, and outputting the data to the level measurement circuits 7a to 7n is performed. Level measurement circuits 7a to 7
n calculates the power value of the pilot symbol part output from the despreading circuits 6a to 6n for each slot (0.625 ms). The result is added for one frame, a difference from the ISSI level is obtained, and the SIR level for one frame is measured (step A2). Further, the level measuring circuits 7a to 7n
Then, the SIR level is compared with the threshold Tg (step A3). SIR
If the level is below the threshold Tg, the level measurement circuit 7a
The paths measured in steps 7 to 7n are regarded as invalid, and path invalid information is notified to the path search circuit 16 and the rake circuit 4 (step A4). Conversely, if the threshold value Tg is exceeded, the paths measured by the level measuring circuits 7a to 7n are regarded as valid, and path valid information is notified to the path search circuit 16 and the rake circuit 4 (step A5). After the level measurement, the despread data is output to the rake circuit 4 (step A).
6). In the rake circuit 4, according to the path valid / invalid information,
Only the paths determined to be valid by the level measurement circuits 7a to 7n are combined.

Next, a description will be given with reference to the flowchart of FIG. The delay profile circuits 15a to 15n correlate the received signal output from the wireless circuit 2 with the known data, and output the correlation result to the path search circuit 16 (step B1). Delayprofile circuits 15a to 15n
For example, a pulse signal every 10 ms output from the timing control circuit 5 is used as a trigger to receive a received signal. At this time, the correlation between the known data and the acquired data is obtained by shifting the phase of the known data to 31 ns while shifting the phase of the known data by 61 ns (shift) from the reference timing pulse signal output from the timing control circuit 5 to 31 ns. Output to the path search circuit 16. The path search circuit 16 searches the correlation results output from the Delayprofile circuits 15a to 15n to find out which phase has the maximum peak value.
(Step B3). At this time, the number of peak value searches depends on the valid / invalid information of the path notified from the finger circuit 3. For example, when three valid paths are notified from the finger circuit 3, the path search circuit 16 searches for only three peak values for a certain period of time. Further, after a certain time has elapsed, the path search circuit 16 again performs the despreading circuits 6a to 6a.
Search for peaks for n number of minutes. After the peak search, the path search circuit 16 outputs data for adjusting the phase of the reference timing pulse output from the timing generation circuits 17a to 17n to the timing generation circuits 17a to 17n based on the detected phase of the peak (step B4). ). The timing generation circuits 17a to 17n update the reference timing according to the phase adjustment data (Step B5).

The configuration and operation of the preferred embodiment of the wireless communication circuit according to the present invention have been described above in detail. However, this embodiment is merely an exemplification of the present invention, and various modifications can be made without departing from the gist of the present invention. For example, the despreading circuits 6a to 6n in FIG. 1 operate with a timing control pulse signal output from the timing control circuit 5 as a trigger. Therefore, when the paths of the level measurement circuits are regarded as invalid by the level measurement circuits 7a to 7n, not only the operation clock of the path search circuit 16 is suppressed, but also the operation clock of the corresponding timing generation circuit is stopped for a certain time. It is also possible. In this modification, when the level measurement circuits 7a to 7n consider that the path is invalid, the operation clock of only the path search circuit 16 is suppressed, and the operation clock of the timing generation circuit 17a is also stopped. Power consumption can be reduced.

[0032]

As is apparent from the above description, according to the radio communication circuit of the present invention, the following various remarkable effects can be obtained in practical use. First, power consumption can be reduced compared to the conventional CDMA method. The reason is that the number of peaks searched by the path search circuit can be suppressed according to the path valid / invalid information notified from the level measurement circuit in the finger circuit. Further, the power consumption can be reduced by suppressing the operation clock according to the number of search peaks.

Second, no special hardware is required. The reason is that the finger circuit determines whether the path is valid / invalid (determines the operation clock is suppressed).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a receiving terminal device according to the present invention.

2 is a block diagram of a detailed configuration of a timing control circuit in FIG. 1 and peripheral circuits thereof.

FIG. 3 is a flowchart illustrating an operation centering on a finger circuit of the receiving terminal device of FIG. 1;

FIG. 4 is a flowchart illustrating an operation of a circuit centering on the timing control circuit of FIG. 2;

FIG. 5 is a block diagram showing a configuration of a conventional receiving terminal device.

6 is a block diagram showing a detailed configuration of a timing control circuit of the conventional receiving terminal device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Antenna 2 Radio circuit 3 Finger circuit 4 Rake circuit 5 Timing control circuit 6a-6n Despreading circuit 7a-7n Level measurement circuit 14 Crystal oscillator 15a-15n Delay profile
Circuit 16 Path search circuit 17a-17n Timing generation circuit

Claims (9)

[Claims] A plurality of despreading circuits for receiving a signal received via an antenna and wirelessly processed by a radio circuit, despreading the signals by a plurality of despreading circuits, and outputting despread data;
In response to a clock from the timing control circuit, a finger circuit having a plurality of level measuring circuits for receiving the output from each despreading circuit and measuring the SIR level, and receiving the output from the finger circuit, A rake circuit for synthesizing data, wherein the rake circuit is enabled by controlling a maximum number of paths to be searched in a path search based on SIR levels from the plurality of level measurement circuits. A receiving terminal device combining only paths. 2. When the SIR levels from the plurality of level measurement circuits are lower than a predetermined threshold, the level measurement circuit of the finger circuit notifies the timing control circuit of path invalidity information to search for the maximum of the path. The receiving terminal device according to claim 1, wherein the number is changed. 3. The receiving terminal device according to claim 1, wherein said path search circuit searches for the number of valid paths for a predetermined time from the path valid / invalid information. 4. The path search circuit according to claim 1, wherein after a predetermined time elapses,
The receiving terminal device according to claim 1, wherein the search for the peak is performed again. 5. A radio circuit, comprising: a radio circuit connected to an antenna; a finger circuit and a timing control circuit to which a signal received from the radio circuit is input; and a rake circuit connected to an output side of the finger circuit. A receiving terminal device for receiving a signal from a propagation path of the path, wherein path valid / invalid information output from the level measuring circuit of the finger circuit according to the electric field level of the received signal is input to the timing control circuit. Receiving terminal device. 6. The method according to claim 6, wherein said path from said finger circuit is valid /
6. The receiving terminal device according to claim 5, wherein the maximum number of peak searches of the path search circuit included in the timing control circuit is adjusted based on the invalid information. 7. The receiving terminal device according to claim 5, wherein an operation clock to a plurality of timing generation circuits included in the timing control circuit is selectively stopped according to the path valid / invalid information. 8. The receiving terminal device according to claim 7, wherein operation clocks of said timing generation circuit and said path search circuit are stopped according to said path valid / invalid information. 9. Each of the circuits in the timing control circuit includes:
9. The receiving terminal device according to claim 5, wherein a clock is supplied from a crystal oscillator.