JP2001185625A - Wiring design method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring design method of a semiconductor integrated circuit which can adjust capacitance formed by adjacent two signal lines and a delay value of a signal running in a signal line. SOLUTION: In this wiring design of a semiconductor integrated circuit, a signal line 201 is arranged. Adjacent lines which are adjacent to the signal line 201 and whose output ends 204o, 205o are opened are arranged. Capacitance formed by the signal line 201 and the adjacent lines 204, 205 is calculated. Wiring lengths L2, L3 of the adjacent lines 204, 205 are adjusted based on the capacitance. When the wiring lengths L2, L3 are adjusted, the capacitance changes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit wiring design method capable of adjusting a delay value of a signal flowing through a signal line of a semiconductor integrated circuit, and a semiconductor integrated circuit design for executing the wiring design method. Regarding support systems.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is designed using a design support system. The design support system supports circuit design and layout design. Design support system is CA
It is a computer equipped with a D tool (Computer Aided design) and a database.

FIG. 9 shows a configuration of a conventional semiconductor integrated circuit design support system. The design support system 1 shown in the figure includes an automatic placement tool 11, an automatic wiring tool 12,
An RC extraction tool 13, a delay calculation tool 14, a timing analysis tool 15, a correction value calculation tool 16, and a timing correction tool 17 are provided. These tools are controlled by a computer processor. The processor operates with reference to a tool program and a database stored in the computer.

FIG. 10 shows wiring of a conventional semiconductor integrated circuit. The semiconductor integrated circuit 2 shown in FIG.
1, a second signal line 22, and a third signal line 23. The first signal line 21 includes a first inverter 24 and a second inverter 25.

[0005] The input 21i of the first signal line 21 is coupled to an output buffer (not shown). An input 22i of the second signal line 22 and an input 23i of the third signal line 23 are coupled to an output buffer (not shown).

The delay value of the signal flowing through the first signal line 21 is
It is affected by the capacitance formed by the first signal line 21 and the wiring board. The delay value of the signal flowing through the first signal line 21 changes when the driving capability (output level) of the output buffer coupled to the first signal line 21 is changed. The delay value of the signal flowing through the first signal line 21 changes the driving capability of the output buffer,
Alternatively, the capacitance is changed and adjusted by changing the wiring length L0 of the first signal line 21.

A technique for correcting the delay value of a signal is disclosed in
-330934. This document discloses a technique for canceling a delay value by using a leading signal whose phase is ahead of a signal flowing through a signal line and a delay signal whose phase is behind a signal flowing through the signal line.

[0008]

In order to change the driving capability of the output buffer, the output buffer is provided with a selectable magnification of the driving capability. The number of options differs for each output buffer. The magnification of the driving capability is represented by, for example, × 1, × 2, × 4.

If the selectable drive magnification is limited to an integral multiple, a situation occurs in which a desired delay value cannot be set. When the drive magnification of the output buffer is changed, the input capacitance value of the output buffer changes, and the delay value of the signal line located before the first signal line 21 changes. Adjusting the delay value of one signal line in this way requires readjustment of the delay value of another signal line.

When the wiring length L0 of the first signal line 21 is changed, the arrangement position on the chip of a cell (element group) coupled to the signal line is naturally changed. Since the cell occupies a wider area than the wiring, the position where the cell can be arranged is limited. If the wiring length of the signal line is restricted, it becomes difficult to match the wiring length with the cell arrangement position.

As the technology of fine processing advances, the spacing between the wirings becomes narrower. When the interval between the wirings is reduced, the capacitance formed by two adjacent signal lines affects the delay value. A wiring layout that performs the above-mentioned matching and also takes into account the capacitance between the two signal lines is very difficult.

[0012]

Means for solving the problem are described as follows. The technical items appearing in the expression are appended with numbers, symbols, etc. in parentheses (). The numbers, symbols, etc. are technical items that constitute at least one embodiment or a plurality of examples of the embodiments or examples of the present invention, in particular, the embodiments or the examples. Corresponds to the reference numerals, reference symbols, and the like assigned to the technical matters expressed in the drawings corresponding to the above. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or the examples.

The present invention provides a wiring design method for a semiconductor integrated circuit that can adjust a capacitance formed by two adjacent signal lines and a delay value of a signal flowing through the signal lines.

According to the wiring design method for a semiconductor integrated circuit of the present invention, the capacitance formed by the signal line (201) and the adjacent lines (204, 205) adjacent to the signal line (201) is calculated, and the adjacent line is calculated based on the capacitance. Line (204,205)
Adjust the wiring length (L2, L3).

According to another wiring design method for a semiconductor integrated circuit according to the present invention, a delay value of a signal flowing through a signal line (201) is calculated, a delay difference between the delay value and a desired delay value is calculated, and the delay is calculated. Calculation of the wiring length of the adjacent line (204, 205) based on the difference is performed.

In a further method for designing a semiconductor integrated circuit according to the present invention, calculation of a difference capacitance corresponding to a delay difference and calculation of the wiring length based on a capacitance ratio of an adjacent line and the difference capacitance are executed.

In a further semiconductor integrated circuit designing method according to the present invention, the phase of the control signal supplied to the adjacent lines (204, 205) is determined according to the phase adjustment direction of the signal flowing through the signal line (201).

In a further method for designing a semiconductor integrated circuit according to the present invention, when the phase adjustment direction indicates a signal delay, the control signal supplied to the adjacent lines (204, 205) is set to a phase-free fixed potential.

In a further method for designing a semiconductor integrated circuit according to the present invention, when the phase adjustment direction indicates a signal advance, the control signal supplied to the adjacent line is set to the first control signal having the same phase as the signal.

In a further method for designing a semiconductor integrated circuit according to the present invention, when the phase adjustment direction indicates a signal delay, the control signal supplied to the adjacent line (204, 205) is set to a second control signal having a phase opposite to that of the signal. You.

A semiconductor integrated circuit design support system according to the present invention comprises a signal line (201), a signal line (201),
In addition, a wiring tool (102) for wiring the adjacent lines (204, 205) whose output ends are open, and a timing for determining the wiring length of the adjacent lines (204, 205) according to the delay value of the signal flowing through the signal line (201). Adjustment tools (106, 107).

A further design support system for a semiconductor integrated circuit according to the present invention is a timing adjustment tool (106, 107).
Measures a delay value of a signal flowing through the signal line (201), calculates a delay difference indicating a difference between the measured delay value and a desired delay value, and calculates a wiring length corresponding to the delay difference.

A further design support system for a semiconductor integrated circuit according to the present invention is a timing adjustment tool (106, 107).
Calculates the difference capacitance according to the delay difference, and calculates the wiring length of the adjacent line with reference to the capacitance ratio and the difference capacitance of the adjacent line.

A further semiconductor integrated circuit design support system according to the present invention is a timing adjustment tool (106, 107).
Determines the phase of the control signal supplied to the adjacent line according to the phase adjustment direction of the signal flowing through the signal line.

A further design support system for a semiconductor integrated circuit according to the present invention is a timing adjustment tool (106, 107).
However, if the phase adjustment direction indicates a signal delay, the control signal supplied to the adjacent line is set to a phase-free fixed potential.

[0026] A further semiconductor integrated circuit design support system according to the present invention is a timing adjustment tool (106, 107).
However, when the phase adjustment direction indicates the advance of the signal, the control signal supplied to the adjacent line is set to the first control signal having the same phase as the signal.

A further design support system for a semiconductor integrated circuit according to the present invention is a timing adjustment tool (106.107).
However, when the phase adjustment direction indicates a signal delay, the control signal supplied to the adjacent line is set to a second control signal having a phase opposite to that of the signal.

[0028]

FIG. 1 shows a configuration of a design support system for a semiconductor integrated circuit according to the present invention. The design support system 10 shown in the figure includes an automatic placement tool 101, an automatic wiring tool 102, an RC extraction tool 103, and a delay calculation tool.
104, timing analysis tool 105, wiring length calculation tool
106 and a timing correction tool 107.

The automatic placement tool 101 determines a placement position of a cell of a semiconductor integrated circuit. The automatic wiring tool 102 determines a wiring path of the signal line. The RC extraction tool calculates the resistance value and the capacitance of the wiring. Delay calculator
104 calculates a delay value flowing through the signal line. The timing analysis tool 105 detects the transmission timing of a signal flowing through a signal line. The wiring length calculation tool 106 calculates the wiring length of the adjacent wiring based on the analysis result of the timing analysis tool 105. The timing correction tool determines a wiring length of the adjacent wiring and a control signal to be supplied to the adjacent wiring based on the calculation result of the adjacent length calculation tool.

These tools are controlled by a computer processor. The processor operates with reference to a tool program and a database stored in the computer.

The wiring length calculation tool 106 calculates the wiring length of the adjacent wiring with reference to the delay correspondence table (for example, FIGS. 2 and 3).

FIG. 2 shows a capacitance characteristic diagram according to the present invention. The vertical axis of the capacitance characteristic diagram shown in the figure indicates time (sec). The horizontal axis indicates the capacity (F). The capacitance characteristic diagram is a correspondence table showing the correspondence between the capacitance and the delay value. The capacitance is formed by the signal line and the adjacent line. The delay value indicates a delay value of a signal flowing through the signal line. If the capacitance is 40 fF,
The signal flowing through the signal line has a delay of 105 psec. When the capacitance is 0.12 pF, a signal flowing through the signal line has a delay of 255 psec.

The timing correction tool 107 instructs the automatic wiring tool 102 to instruct rewiring and the type of control signal. The automatic wiring tool 102 selects an appropriate control signal from the fixed potential, the first control signal, and the second control signal. The fixed potential is selected when delaying the phase of the signal flowing through the signal line. The first control signal is selected when the phase of the signal flowing through the signal line is advanced. The second control signal is
This is selected when the phase of the signal flowing through the signal line is delayed. The phase delay is greater when the second control signal is supplied than when a fixed potential is applied.

FIG. 3 shows a characteristic waveform of a control signal according to the present invention. The vertical axis of the characteristic waveform diagram shown in FIG.
c) is shown. The horizontal axis represents the ratio (%) of the wiring length of the adjacent line to the wiring length of the signal line. The ratio is 0 to 200
(%) Are shown. When one adjacent line is arranged for one signal line, a numerical value of 0 to 100 (%) is referred to. When two adjacent lines are arranged for one signal line, a numerical value of 0 to 200 (%) is referred to. Ratio 100
(%) Indicates a state in which, when there is one adjacent line, the wiring length of the adjacent line is set to the same length as the signal line length. Ratio 100
(%) Indicates a state in which, when there are two adjacent lines, the wiring length of the adjacent lines is set to 50 (%). Ratio 120 (%)
In the case of (2), a state is shown in which two adjacent lines having a wiring length set to 60 (%) are prepared. The wiring length is 1 when the ratio is 200 (%).
This shows a state in which two adjacent lines set to 00 (%) are prepared.

One or more adjacent lines are provided for one signal line. When two adjacent lines are arranged on one signal line, the adjacent lines are arranged above, below, or on the left and right of the signal line. When a fixed potential is applied to an adjacent line, the delay value increases or decreases in proportion to the wiring length of the adjacent line. The adjacent line can be installed in a coil shape around the signal line.

When the first control signal, which is a signal having the same phase as the signal flowing through the signal line, is supplied to the adjacent line, the delay value increases or decreases in inverse proportion to the wiring length of the adjacent line. When the second control signal, which is a signal having the opposite phase to the signal flowing through the signal line, is supplied to the adjacent line, the delay value increases or decreases in proportion to the wiring length of the adjacent line.

For example, in the example of FIG. 3, when a fixed potential is applied to the adjacent line, the delay value for the rising edge (LH) of the signal is larger than the delay value for the falling edge (HL) of the signal.
When the first control signal is supplied to the adjacent line, the delay value for the rising edge (LH) of the signal is larger than the delay value for the falling edge (HL) of the signal. When the second control signal is supplied to the adjacent line, the delay value for the rising edge (LH) of the signal is larger than the delay value for the falling edge (HL) of the signal.

The design support system 10 according to the present invention can execute processing by referring to data for a rise and data for a fall. The design support system 10 according to the present invention can execute processing with reference to the average value of these data.

FIG. 4 shows wiring of a semiconductor integrated circuit according to the present invention. The illustrated semiconductor integrated circuit 20 includes a first signal line 201, a second signal line 202, and a third signal line 203. The semiconductor integrated circuit 20 includes a first adjacent line 204 and a second adjacent line 205. The first signal line 201 has an input 201i and an output 201o.
Is provided. The first signal line 201 is connected to the first inverter 206 and the second
An inverter 207 is provided. The second signal line 202 has an input 202i and an output 202o. The third signal line 203 has an input 203i and an output 2
Equipped with 03o. The first adjacent line 204 has an input 204i and an open end 204o.
Is provided. The first adjacent line 204 includes an inverter 208.
The second adjacent line 205 has an input 205i and an open end 205o. The second adjacent line 205 includes an inverter 209.

The input 201i of the first signal line 201 is coupled to an output buffer (not shown). Input 202 of second signal line 202
i and the input 203i of the third signal line 203 are coupled to an output buffer (not shown). The input 204i of the first adjacent line 204 and the input 205i of the second adjacent line 205 are coupled to an output buffer (not shown).

The wiring length between the output of the first inverter 206 and the input of the second inverter 207 is set to L1. Third
The wiring length between the output of the inverter 208 and the open end 204o is L2
Can be changed. The wiring length L3 between the output of the fourth inverter 209 and the open end 205o can be changed.

FIG. 5 shows an arrangement of capacitances of a semiconductor integrated circuit according to the present invention. The circuit shown in FIG.
Is a part of the semiconductor integrated circuit 20 shown in FIG.

Between the first signal line 201 and the first adjacent line 204,
A first capacitance 31 is formed. First signal line 201
A second capacitance 32 is formed between the first and second adjacent lines 205. The third capacitor 33 is formed between the first signal line 201 and the substrate 210. The fourth capacitor 34 is formed between the first adjacent line 204 and the substrate 210. 2nd adjacent line
A fifth capacitor 35 is formed between 205 and the substrate 210.

When the wiring length L2 of the first adjacent line 204 is changed, the capacitance C1 of the capacitance 31 changes.
When the wiring length L3 of the second adjacent line 205 is changed, the capacitance C2 of the capacitance 32 changes.

A wiring design method for a semiconductor integrated circuit according to the present invention will be described with reference to FIGS. Here, the process of adjusting the delay value of the signal flowing through the first signal line 201 will be described.

The automatic placement tool 101 places cells (not shown) so that the mounting area is used efficiently.
The automatic wiring tool 102 connects the first to third signal lines 201 to 203. The automatic wiring tool 102 is configured to use the first and second adjacent lines 2
Wire 04,205. These wirings are provided with first to fourth inverters 206 to 209. RC extraction tool 103
The resistance and capacitance values formed by the first to third signal lines 201 to 203 are detected. RC extraction tool 103
And the resistance and capacitance values formed by the second adjacent lines 208 and 209 are detected. The delay calculation tool 104 refers to the resistance value and the capacitor detected by the RC extraction tool 103,
A delay value of a signal flowing through the first signal line 201 is calculated. The timing analysis tool 15 analyzes whether the delay value of the signal flowing through the first signal line 201 is an allowable value. When the analysis result of the timing analysis tool 15 indicates “permissible”, the design is completed.

The analysis result of the timing analysis tool 15 is "
If "Unacceptable" is indicated, the wiring length calculation tool 106 is activated. The wiring length calculation tool 106 calculates the wiring length of the adjacent wiring with reference to the delay value correspondence table (FIG. 2). Then, a delay difference Tdef between the desired delay value and the current delay value is obtained, and the delay difference Tdef is converted into a difference capacitor Cdef.

The difference capacitor Cdef is expressed as follows: Cdef = ε (s /
d). ε indicates a dielectric constant. s indicates the area of the signal line and the adjacent line facing each other. d indicates the opposing length of the signal wiring and the adjacent wiring. From this equation, the wiring length of the adjacent wiring is derived. The wiring length calculated by the wiring length calculation tool 106 is
The timing correction tool 107 is notified.

The capacitance ratio (capacitance per unit length) can also be referred to. When the difference capacitor is divided by the capacitance ratio, the amount of change in the wiring length of the adjacent wiring is calculated.

The timing correction tool 107 refers to the notified wiring length, and notifies the automatic wiring tool 102 of a change in the wiring length of the adjacent wirings 202 and 203. The automatic wiring tool 102 changes the wiring length of the adjacent wirings 204 and 205 and activates the RC extraction tool 103.

The timing correction tool 107 selects a control signal to be supplied to the adjacent wirings 204 and 205 in addition to correcting the wiring length of the adjacent wiring. The control signal is set according to the adjustment direction and the degree of the phase of the signal flowing through the signal line. When advancing the phase of the signal, the timing correction tool 107 supplies a first control signal having the same phase as the signal of the signal line to the adjacent wiring. When the timing correction tool 107 significantly delays the phase of a signal, the timing correction tool 107 adds a second signal having a phase opposite to that of the signal of the signal line to the adjacent wiring.
Supply control signals. When slightly delaying the phase of the signal, the timing correction tool 107 applies a fixed potential to the adjacent wiring.

FIG. 6 shows an equivalent circuit of a first wiring method for a semiconductor integrated circuit according to the present invention. The wiring shown in the figure includes the signal line 201 shown in FIG. 4 and the first and second adjacent lines 20.
4,205 is shown in detail. A first control signal is supplied to the adjacent lines 204 and 205 connected to the inverters 208 and 209 shown in FIG.

The input of the signal line 201 connected to the inverter 206 and the inputs of the first and second adjacent wirings 204 and 205 are supplied through the inverter 220. The output of signal line 201 is coupled to output 312. Between the first inverter 206 and the second inverter 207,
An equivalent resistance 41 is formed. An equivalent resistor 42 is formed at the output of the third inverter 208. Fourth inverter 209
, An equivalent resistance 43 is formed.

A capacitance 31 is formed between the signal line 201 and the adjacent line 204. A capacitance 32 is formed between the signal line 201 and the adjacent line 205. A capacitance 33 is formed between the signal line 201 and a ground terminal (substrate). A capacitance 34 is formed between the adjacent line 204 and the ground terminal. A capacitance 35 is formed between the adjacent line 205 and the ground terminal. RC extraction tool 103
Are equivalent resistances 41 to 43 and capacitances 31 to 35
Is extracted.

A first control signal having the same phase as the signal is supplied to the adjacent lines 204 and 205. The first control signal is generated based on a signal flowing through the signal line 201. The phase of the signal flowing through the signal line 201 is advanced.

FIG. 7 shows an equivalent circuit of a second wiring method for a semiconductor integrated circuit according to the present invention. The wiring shown in the figure includes the signal line 201 shown in FIG. 4 and the first and second adjacent lines 20.
The configuration according to 4,205 is shown in detail. As shown in FIG. 7, the adjacent lines 204 and 205 are separated from the inverters 208 and 209. A fixed potential is applied to the adjacent lines 204 and 205.

As shown in FIG. 7, the input of the signal line 201 connected to the inverter 206 is supplied via the inverter 301. The output of signal line 201 is coupled to output 312. Inverter 301 supplies a signal to inverter 206. The adjacent lines 204 and 205 separated from the inverters 208 and 209 connected to the inverter 301 are coupled to the ground terminal when the above-mentioned fixed potential is the ground potential. The first inverter 206 and the second
An equivalent resistance 41 is formed between the inverters 207.
In the case of the configuration shown in FIG. 7 on the output side of the third inverter 208, the equivalent resistance 42 is formed on the adjacent line 204. 4th
The output side of the inverter 209, in the case of the configuration shown in FIG.
The equivalent resistance 43 is formed on the adjacent line 205. Since the adjacent lines 204 and 205 on the output side of the inverters 208 and 209 are coupled to the ground terminal, the equivalent resistances 42 and 43 are coupled to the ground terminal.

A capacitance 31 is formed between the signal line 201 and the adjacent line 204. A capacitance 32 is formed between the signal line 201 and the adjacent line 205. A capacitance 33 is formed between the signal line 201 and a ground terminal (substrate). A capacitance 34 is formed between the adjacent line 204 and the ground terminal. A capacitance 35 is formed between the adjacent line 205 and the ground terminal. RC extraction tool 103
Are equivalent resistances 41 to 43 and capacitances 31 to 35
Is extracted.

A fixed potential is applied to the adjacent lines 204 and 205. The phase of the signal flowing through the signal line 201 is delayed.

FIG. 8 shows an equivalent circuit of a third wiring method for a semiconductor integrated circuit according to the present invention. The wiring shown in the figure includes the signal line 201 shown in FIG. 4 and the first and second adjacent lines 20.
The configuration according to 4,205 is shown in detail. As shown in FIG. 8, the adjacent lines 204 and 205 are separated from the inverters 208 and 209. In addition, a second control signal is supplied to the adjacent lines 204 and 205 via the inverters 302 and 303.

As shown in FIG. 8, the input of the signal line 201 connected to the inverter 206 is supplied via the inverter 301. The output of the signal line 201 passes through the second inverter 207 and is output to the output 322. Inverter 301, inverter 20
Supply signal to 6.

The input 321 is supplied with a signal having the same phase as that of the signal line 201. A second control signal having a phase opposite to that of the signal flowing through the signal line 201 is supplied to the adjacent lines 204 and 205.

The equivalent resistance 41 is formed between the first inverter 206 and the second inverter 207. Third inverter 20
8, the equivalent resistance 42 is formed in the adjacent line 204. In the case of the configuration shown in FIG. 8 on the output side of the fourth inverter 209, the equivalent resistance 43 is formed on the adjacent line 205.

A capacitance 31 is formed between the signal line 201 and the adjacent line 202. A capacitance 32 is formed between the signal line 201 and the adjacent line 203. A capacitance 33 is formed between the signal line 201 and a ground terminal (substrate). A capacitance 34 is formed between the adjacent line 204 and the ground terminal. A capacitance 35 is formed between the adjacent line 205 and the ground terminal. RC extraction tool 103
Are equivalent resistances 41 to 43 and capacitances 31 to 35
Is extracted.

A fixed potential is applied to the adjacent lines 204 and 205. The phase of the signal flowing through the signal line 201 is delayed. The delay amount is larger than when a fixed potential is applied to the adjacent lines 204 and 205.

[0066]

According to the semiconductor integrated circuit wiring design method of the present invention, when the wiring length of the adjacent line is changed, the capacitor formed by the signal line and the adjacent line changes. When the capacitor changes, the delay value of the signal flowing through the signal line changes. When the delay value of the signal flowing through the signal line is adjusted, it is not necessary to change the wiring length of the signal line. The delay value of the signal flowing through the signal line is
It is not affected by other signal lines adjacent via the adjacent line.
Therefore, a situation in which a cell is moved to adjust a delay value of a signal flowing through a signal line does not occur, and fine delay adjustment can be performed without a large-scale layout change.

[Brief description of the drawings]

FIG. 1 shows a configuration of a semiconductor integrated circuit design support system according to the present invention.

FIG. 2 shows a capacitance characteristic according to the present invention.

FIG. 3 shows a characteristic waveform of a painter fish signal according to the present invention.

FIG. 4 shows wiring of a semiconductor integrated circuit according to the present invention.

FIG. 5 shows a capacitance arrangement of a semiconductor integrated circuit according to the present invention.

FIG. 6 shows an equivalent circuit of a first wiring of the semiconductor integrated circuit according to the present invention.

FIG. 7 shows an equivalent circuit of a second wiring of the semiconductor integrated circuit according to the present invention.

FIG. 8 shows an equivalent circuit of a third wiring of the semiconductor integrated circuit according to the present invention.

FIG. 9 shows a configuration of a conventional semiconductor integrated circuit design support system.

FIG. 10 shows wiring of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 10: Design support system for semiconductor integrated circuits 101: Automatic placement tool 102: Automatic wiring tool 103: RC extraction tool 104: Delay calculation tool 105: Timing analysis tool 106: Wire length calculation tool 107: Timing correction tool 201: First signal Line 202: Second signal line 203: Third signal line 204: First adjacent line 205: Second adjacent line

Claims (15)

[Claims] 2. A wiring design method for a semiconductor integrated circuit, comprising: calculating a capacitance formed between a signal line and an adjacent line adjacent to the signal line; and adjusting a wiring length of the adjacent line based on the capacitance. 2. The method according to claim 1, wherein a delay value of a signal flowing through the signal line is calculated, a delay difference between a delay value and a desired delay value is calculated, and the wiring corresponding to the delay difference is calculated. A wiring design method for a semiconductor integrated circuit in which a length is calculated. 3. The method according to claim 2, wherein calculation of a difference capacitance corresponding to the delay difference and calculation of the wiring length based on a capacitance ratio of the adjacent line and the difference capacitance are performed. Circuit wiring design method. 4. The method according to claim 3, wherein a phase of a control signal supplied to the adjacent line is determined according to a phase adjustment direction of a signal flowing through the signal line. 5. The method according to claim 4, wherein when the phase adjustment direction indicates a delay of the signal, a control signal supplied to the adjacent line is set to a phase-free fixed potential. Wiring design method. 6. The method according to claim 4, wherein when the phase adjustment direction indicates the advance of the signal, a control signal supplied to the adjacent line is set to a first control signal having the same phase as the signal. A wiring design method for a semiconductor integrated circuit. 7. The method according to claim 4, wherein when the phase adjustment direction indicates a delay of the signal, a control signal supplied to the adjacent line is set to a second control signal having a phase opposite to the signal. Wiring design method for semiconductor integrated circuits. 8. A signal line, adjacent to the signal line, and
A design support system for a semiconductor integrated circuit, comprising: a wiring tool for setting an adjacent line; and a timing adjustment tool for determining a wiring length of the adjacent line according to a delay value of a signal flowing through the signal line. 9. The system according to claim 8, wherein the timing adjustment tool includes: measuring a delay value of a signal flowing through the signal line; and a delay difference indicating a difference between the measured delay value and a desired delay value. And a calculation support system for calculating the wiring length corresponding to the delay difference. 10. The system according to claim 9, wherein the timing adjustment tool calculates a difference capacitance corresponding to the delay difference, and calculates the wiring length based on a capacitance ratio of the adjacent line and the difference capacitance. A design support system for a semiconductor integrated circuit that performs the following. 11. The semiconductor integrated circuit according to claim 10, wherein the timing adjustment tool determines a phase of a control signal supplied to the adjacent line according to a phase adjustment direction of a signal flowing through the signal line. Design support system. 12. The system according to claim 11, wherein the timing adjustment tool sets a control signal supplied to the adjacent line to a phase-free fixed potential when the phase adjustment direction indicates a delay of the signal. Design support system for semiconductor integrated circuits. 13. The system according to claim 11, wherein the timing adjustment tool includes: a first control unit that, when the phase adjustment direction indicates the advance of the signal, controls a control signal supplied to the adjacent line to be in phase with the signal. A design support system for semiconductor integrated circuits that sets signals. 14. The system according to claim 11, wherein, when the phase adjustment direction indicates a delay of the signal, the timing adjustment tool sends a control signal to be supplied to the adjacent line to a second phase opposite to the signal. A design support system for a semiconductor integrated circuit set in a control signal. 15. A computer-readable storage medium storing a program for controlling the method according to claim 1. Description: