JP2001177442A - Spread spectrum receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the inverse spread processing by a spread spectrum receiver. SOLUTION: A DLL circuit 100 is provided with a 1st inverse spread circuit 110 that uses a spread code with an advanced phase to apply inverse spread processing to an output of a quasi-synchronization detection circuit 10 to obtain a 1st correlation value and with a 2nd inverse spread circuit 120 that uses a spread code with a delayed phase to apply inverse spread processing to an output of the quasi-synchronization detection circuit 10 to obtain a 2nd correlation value. The DLL circuit 100 applies phase control to the spread code so that the 1st correlation value is equal to the 2nd correlation value. An inverse spread circuit 30 consists of two adders 31, 32 and the adder 31 adds real parts IL', IL'' of the 1st and 2nd correlation values respectively outputted from the 1st and 2nd inverse spread circuits 110, 120 of the DLL circuit 100 to provide the output of a real part IL of the inverse spread signal. Furthermore, the adder 32 adds imaginary parts QL', QL'' of the 1st and 2nd correlation values respectively outputted from the 1st and 2nd inverse spread circuits 110, 120 to provide the output of an imaginary part QL of the inverse spread signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum receiver.

[0002]

2. Description of the Related Art Conventionally, in a communication system using a code division multiple access (CDMA) system, an information symbol is transmitted at the time of transmission.
The spectrum is spread by a spreading code, orthogonally modulated by a carrier, and transmitted. In the receiver, the received signal is quasi-synchronously detected by the quasi-synchronous detection circuit. The quasi-coherently detected signal is despread by each of a plurality of fingers using the same spreading code as that used for transmission, and further subjected to synchronous detection using channel estimation. The synchronous detection output from each finger, that is, the demodulated signal is synthesized by the combiner.

FIG. 6 shows a partial configuration of one finger in a conventional spectrum receiver.

At the receiver, the received signal Rx is
The signal is input to the quasi-synchronous detection circuit 10. The quasi-synchronous detection circuit 10 uses a multiplier 11 to perform COS (ω
t + θfc (t)), and multiplied by −SI
N (ωt + θfc (t)) is applied to perform quadrature detection, and low-pass filters (LPF) 13 and 14 remove harmonic components to output quasi-synchronous detection signals I and Q. A / A (not shown) is provided after the LPFs 13 and 14.
D converters are provided, respectively, and the quasi-synchronous detection signals I and Q are converted into digital signals by the respective A / D converters. Note that the above θ
fc (t) indicates a difference (phase shift) between the carrier frequency on the transmitting side and the frequency of the oscillator of the receiver.

The quasi-synchronous detection signal is represented by a complex number of an in-phase component (real part) I and a quadrature component (imaginary part) Q, and is expressed by Equation 1.

[0006]

[Number 1] ^{A (t) · e j θ} d · e j θ c · e j θ (t) where, A (t) is amplitude, e ^j θ ^d is the transmission signal of the information symbol, e ^j θ ^c Indicates a spread code used for transmission, and e ^j θ ^(t) indicates a phase change due to fading and a phase change due to a frequency shift of an oscillator of a receiver.

At each finger, the quasi-synchronous detection signal I,
Q is input to the despreading circuit 20. Despreading circuit 20
Performs complex multiplication of the quasi-synchronous detection signals I and Q by spread codes (complex conjugate signals) Ci and Cq having the same code and the same phase as those used for transmission. That is, the multipliers 21 and 22, the adder 2
3, the real part signal IS (= I · Ci + Q · Cq) is obtained, and the multipliers 25 and 26 and the adder 27 obtain the imaginary part signal Qs (= Q · Ci−I · Cq). Then, in order to remove interference noise such as signals from other channels and the like, correlation detection (one symbol length integration) is performed by the integrators 24 and 28, respectively, to obtain despread signals IL and QL. This despread signal is represented by Equation 2 when the amplitude components are collectively expressed by R (t).

[0008]

To Equation 2] ^{R (t) · e j θ} d · e j θ (t) The despread signal, the synchronous detection circuit (not shown), performs channel estimation, remove the components of e ^j θ ^(t) , E ^j θ ^d to obtain a demodulated signal.

Also, each of the above-mentioned fingers has a structure shown in FIG.
As shown in the figure, a DLL for synchronously following a spreading code
A (Delay Locked Loop) circuit 100 is provided.

The DLL circuit 100 includes a spread code Ci,
A spreading code Ci ′ (= Ci (τ + 0.5)) with a phase advanced by a predetermined value with respect to Cq, for example, 1/2 chip, Cq ′
(= (Τ + 0.5)), a first despreading circuit 110 for despreading the quasi-synchronous detection signals I and Q, and a spreading code Ci,
Spreading code C delayed in phase by 1/2 chip with respect to Cq
i ″ (= Ci (τ−0.5)), Cq ″ (= Cq (τ−
0.5)), a second despreading circuit 120 for despreading the quasi-synchronous detection signals I and Q is provided. Note that τ indicates the phase difference between the spreading codes Ci and Cq whose phases are controlled by the DLL circuit 100. When synchronization is established, the phase difference τ becomes zero.

In the first despreading circuit 110, a multiplier 11
1, 112 and Is ′ (= I · Ci ′ +
Q · Cq ′), and the correlation is detected by the integrator 114 to obtain the first
To obtain the real part IL 'of the correlation value of
5, 116, and Qs ′ (= Q · Ci′−
I · Cq ′), and the integrator 118 detects the correlation to obtain the first
To obtain the imaginary part QL ′ of the correlation value of Then, the real part IL 'and the real part QL' of the first correlation value are squared by the squarers 131 and 132, respectively, and the results are added by the adder 133.
The magnitude (power or power) of the first correlation value is output.

In the second despreading circuit 120, the multiplier 12
1, 122, and Is ″ (= I · Ci ″) by the adder 123.
+ Q · Cq ″), and the correlation is detected by the integrator 124 to obtain the real part IL ″ of the second correlation value.
5, 126, and Qs ″ (= Q · Ci ″) by the adder 127.
−I · Cq ″), and a correlation is detected by the integrator 128 to obtain an imaginary part QL ″ of the second correlation value. Then, the real part IL ″ and the real part QL ″ of the second correlation value are converted to the squares 134 and 13.
5 are squared, and the results are added by an adder 136 to output the magnitude (power or power) of the second correlation value.

The outputs of the adder 133 and the adder 136 are input to the adder 137. The adder 137
The difference D between the output of the adder 133 and the output of the adder 136, that is, the difference D between the magnitude of the correlation value where the 1/2 chip phase is advanced and the magnitude of the correlation value where the 1/2 chip phase is delayed. Ask. As shown in FIG. 7, the magnitude of the correlation value becomes maximum when synchronization is established and the phase difference is 0. At this time, the magnitude of the correlation value where the 1/2 chip phase is advanced is equal to the magnitude of the correlation value where the 1/2 chip phase is delayed, and the magnitude of the correlation value output from the adder 136 is obtained. The output D indicating the difference is 0. However, if the phase is shifted, there is a difference between the magnitude of the correlation value where the 1/2 chip phase is advanced and the magnitude of the correlation value where the 1/2 chip phase is delayed. D does not become 0 and has a predetermined size.

The output D of the adder 136 is input to the phase control spread code generator 139 via the LPF 138. The phase control spreading code generator 139 generates the spreading codes Ci, Cq, Ci ′,... So that the output D of the adder 136 becomes zero.
Cq ′, Ci ″, and Cq ″ are generated. This allows
The output D of the adder 136 is set to 0, that is, 1 /
The magnitude of the correlation value where the two-chip phase has advanced, and 1 /
The phase tracking control of the spreading code is performed so that the magnitude of the correlation value at the point where the two-chip phase is delayed becomes equal.

[0015]

In this type of spread spectrum receiver, there is a demand for downsizing the receiver or simplifying the arithmetic processing. According to the configuration described above, each of the plurality of fingers includes the despreading circuit 20 and the DLL circuit 100, and performs the same despreading processing on each of the fingers.

It is an object of the present invention to obtain a despread signal by using a part of the phase tracking control processing by paying attention to the above-mentioned points, so that the receiver can be reduced in size or the arithmetic processing can be simplified. .

[0017]

In order to achieve the above object, according to the first aspect of the present invention, a quasi-synchronous detection means (10) is provided by using an advanced spreading code whose phase is advanced by a predetermined value.
Is despread to obtain a first correlation value, and a second correlation value is obtained by despreading the output of the quasi-synchronous detection means with a delay spread code obtained by delaying the phase of the spread code by a predetermined value,
Phase control means (1) for controlling the phase of the spreading code so that the magnitudes of the first correlation value and the second correlation value become equal.
00, 100A), a despread signal is output from a despreading means (30, 140) using the first correlation value and the second correlation value.
By using the first and second correlation values obtained by the phase control means (100), the processing by the despreading means (30, 140) can be simplified.
In this case, as the despreading means (30, 140), specifically, the real part of the first correlation value obtained from the phase control means (100) and the second First adding means (31) for adding the real part of the correlation value of
A second adding means (32) for adding an imaginary part of the first correlation value and an imaginary part of the second correlation value, so that the first and second adding means output despread signals. Can be configured.

According to a first aspect of the present invention, as in the second aspect of the invention, the first signal spread by the first spreading code and the first signal spread by the second spreading code are used. The sum of the two signals may be applied to a receiving receiver as a received signal. In other words, according to the second aspect of the present invention, the quasi-synchronous detection means determines, as a received signal, the first signal spread by the first spreading code and the second signal spread by the second spreading code. Quasi-synchronous detection of the sum and phase control means (100A)
Calculates a first correlation value by despreading the output of the quasi-synchronous detection means with a leading spreading code obtained by advancing the phase of the first spreading code by a predetermined value, and setting the phase of the first spreading code to a predetermined value. The second correlation value is obtained by despreading the output of the quasi-synchronous detection means using the delayed spread code, and the first spread value is set so that the magnitudes of the first correlation value and the second correlation value become equal. The phase control of the code is performed, and the despreading means (140) outputs a despread signal of the first signal using the first correlation value and the second correlation value. By using the first and second correlation values obtained by the phase control means (100A) in this manner, the processing of the despread signal of the first signal by the despreading means (140) is simplified. Can be.

Specifically, the phase control means (110A)
In the first aspect of the present invention, the first spread code is complex-multiplied by the advanced spread code obtained by advancing the phase of the first spread code by a predetermined value and the output of the quasi-synchronous detection means, and correlation detection is performed. A second correlation value is obtained by performing a complex detection on the correlation value and complexly multiplying the output of the quasi-synchronous detection means by a delayed spreading code obtained by delaying the phase of the first spreading code by a predetermined value to obtain a second correlation value. The phase control of the first spreading code is performed so that the magnitude of the correlation value becomes equal to the magnitude of the second correlation value, and the despreading means (140) outputs the first and second addition means ( 141, 142)
To output the first despread signal.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a partial configuration of a spectrum receiver according to a first embodiment of the present invention. The configuration shown in FIG. 1 corresponds to the configuration shown in FIG. 6, and portions denoted by the same reference numerals as those shown in FIG. 6 indicate that they are the same or equivalent.

In this embodiment, the despreading circuit 30
It comprises two adders 31 and 32. Adder 31
Is the real part I of the first correlation value output from the integrator 114 in the first despreading circuit 110 of the DLL circuit 100.
L ′ and an integrator 124 in the second despreading circuit 120.
Is added to the real part IL ″ of the second correlation value output from the.

The real part IL ′ of the first correlation value has a phase of 1
The real part IL of the second correlation value corresponds to the real part IL of the despread signal where the phase is delayed by 1/2 chip. Therefore, in a state where synchronization is established, the sum of the real part IL ′ of the first correlation value and the real part IL ″ of the second correlation value is equal to a value substantially equal to the real part IL of the despread signal. Become.

Similarly, the adder 32 outputs the imaginary part QL ′ of the first correlation value output from the integrator 118 in the first despreading circuit 110 and the imaginary part QL ′ of the first correlation value from the integrator 128 in the second despreading circuit 120. The imaginary part Q of the output second correlation value
Add L ''.

The imaginary part QL 'of the first correlation value has a phase of 1
The imaginary part QL of the second correlation value corresponds to the imaginary part QL of the despread signal where the phase is delayed by チ ッ プ chip. Therefore, in the synchronized state, the sum of the imaginary part QL ′ of the first correlation value and the imaginary part QL ″ of the second correlation value is set to a value substantially equal to the imaginary part QL of the despread signal. Become.

Therefore, the despreading circuit 3 of the first embodiment
At 0, as in the despreading circuit 20 shown in FIG. 6, four multipliers 21, 22, 25, 26, adders 23, 27,
Even without using the integrators 24 and 28, the two adders 31,
32, it is possible to reduce the size of the circuit and reduce the current consumption.

(Second Embodiment) In recent years, spectrum communication of a code multiplex system has been proposed. In the second embodiment, a code multiplex system spectrum receiver is shown in FIG.
This will be described with reference to FIGS. However, the reception signal Rx of the code multiplexing method is a spreading code (first spreading code) Cip, Cp.
It consists of the sum of the pilot signal (known signal) spread by qp and the information signal spread by the spreading codes (second spreading code) Ci and Cq. Information signal (information channel)
Is composed of a plurality of information symbols, and a pilot signal (pilot channel) is composed of a plurality of pilot symbols. Note that the spreading codes Cip, C
qp is different from the spreading codes Ci and Cq.

FIGS. 2 and 3 show a partial configuration of one finger in a code multiplexing type spectrum receiver studied by the present inventors. In the configurations shown in FIGS. 2 and 3, the portions denoted by the same reference numerals as those shown in FIG. 1 indicate that they are the same or equivalent. First,
In the code multiplexed spectrum receiver, the received signal Rx is input to the quasi-synchronous detection circuit 10. In the quasi-synchronous detection circuit 10, the received signal R
Multipliers 11 and 12 perform quadrature detection on x, and low-pass filters (LPFs) 13 and 14 remove harmonic components to output quasi-synchronous detection signals I and Q.

Next, in each finger, the quasi-synchronous detection signals I and Q are input to the despreading circuit 20, and the quasi-synchronous detection signals I and Q are substantially the same as in the first embodiment. I and Q are subjected to complex multiplication by in-phase spreading codes (complex conjugate signals) Ci and Cq in the information signal. That is, the real part signal IS (= I · Ci + Q · Cq) is obtained by the multipliers 21 and 22 and the adder 23, and the imaginary part signal Qs (=) is obtained by the multipliers 25 and 26 and the adder 27.
Q · Ci−I · Cq). Then, in order to remove the interference noise, the integrators 24 and 28 respectively perform correlation detection (one symbol length integration) to obtain a despread signal I of the information signal.
L and QL are obtained. However, the spreading codes Ci and Cq are generated by a DLL circuit 100A described later.

Also, each of the above-mentioned fingers has the structure shown in FIG.
As shown in the figure, a DLL for synchronously following a spreading code
A circuit 100A is provided. DLL circuit 100A
Is a spreading code Cip ′ (= Cip (τ + 0.5)) with a phase advanced by a predetermined value with respect to the spreading codes Cip and Cqp of the pilot signal, for example, 1/2 chip, Cqp ′ (= Cq
p (τ + 0.5)), a first despreading circuit 110A for despreading the quasi-synchronous detection signals I and Q, and a delay having a phase delayed by チ ッ プ chip with respect to the spreading codes Cip and Cqp of the pilot signal. The spreading code Cip ″ (= Cip (τ−0.
5)), a second despreading circuit 1 that despreads the quasi-synchronous detection signals I and Q using Cqp ″ (= Cqp (τ−0.5)).
20A. Note that τ indicates the phase difference between the spreading codes Cip and Cqp of the pilot signal whose phase is controlled by the DLL circuit 100A. When synchronization is established, the phase difference τ becomes zero.

In the first despreading circuit 110A, the multiplier 1
11A, 112A, and Isp '(=
I · Cip ′ + Q · Cqp ′) is obtained, the correlation is detected by the integrator 114A to obtain the real part ILp ′ of the first correlation value, and Qsp ′ (= Q · C) is obtained by the multipliers 115A and 116A and the adder 117A. Cip′−I · Cqp ′), and a correlation is detected by the integrator 118A, and the imaginary part QL of the first correlation value is obtained.
Obtain p '. Then, the real part ILp 'and the imaginary part QLp' of the first correlation value are squared by the squarers 131A and 132A, respectively, and the results are added by the adder 133A to obtain the magnitude of the first correlation value in the pilot signal. (Power or electric power) is output.

In the second despreading circuit 120A, the multiplier 1
21A and 122A, and Isp ″ (=
I · Cip ″ + Q · Cqp ″) to obtain the integrator 124A.
To obtain the real part ILp ″ of the second correlation value, and obtain Qsp ″ (= Q · Cip ″ −I · Cqp ″) by the multipliers 125A and 126A and the adder 127A. The correlation is detected by the integrator 128A to obtain the imaginary part QLp ″ of the second correlation value. Then, the real part IL of the second correlation value
p ″ and the imaginary part QLp ″ are squared by the squarers 134A and 135A, and the results are added by the adder 136A.
The magnitude (power or power) of the second correlation value in the pilot signal is output.

The respective outputs of the adder 133A and the adder 136A are input to the adder 137A,
A is the difference between the output of the adder 133A and the output of the adder 136A, that is, the magnitude of the correlation value where the 1/2 chip phase is advanced and the magnitude of the correlation value where the 1/2 chip phase is delayed. Find the difference Dp. The magnitude of the correlation value is greatest when synchronization is achieved and the phase difference is zero. At this time, 1
The magnitude of the correlation value where the / 2 chip phase has advanced, and 1
The magnitude of the correlation value at the point where the / 2 chip phase is delayed becomes equal, and the output Dp indicating the difference between the magnitudes of the correlation values output from the adder 136 becomes zero. However, if the phase is shifted, there is a difference between the magnitude of the correlation value where the 1/2 chip phase is advanced and the magnitude of the correlation value where the 1/2 chip phase is delayed. Dp has a predetermined size.

The output Dp of the adder 136 is the LPF 138
Is input to the phase control spreading code generator 139A through The phase control spreading code generator 139A includes an adder 1
The spreading codes Ci and C are output so that the output D of the 36A becomes 0.
q, Cip, Cqp, Cip ′, Cqp ′, Cip ″, C
qp ″ is generated. Thereby, the magnitude of the correlation value where the output D of the adder 136A becomes 0, that is, the magnitude of the correlation value where the 1/2 chip phase is advanced, and the magnitude of the correlation value where the 1/2 chip phase is delayed are changed. To be equal,
Phase tracking control of the spreading code is performed.

Further, each of the above-mentioned fingers is provided with a pilot channel despreading demodulation circuit 40 for despreading the pilot signal, as shown in FIG. In this pilot channel despreading demodulation circuit 40,
The quasi-synchronous detection signals I and Q are complex-multiplied by the spreading codes Cip and Cqp (generated by the DLL circuit 100A) of the pilot channel. That is, the real part signal ISp ′ ″ (= I · Cip) is calculated by the multipliers 41 and 42 and the adder 43.
+ Q · Cqp) and multipliers 45 and 46,
By the adder 47, the imaginary part signal Qsp ′ ″ (= Q · Ci
pI · Cqp). Then, in order to remove the interference noise, the integrators 44 and 48 respectively perform correlation detection (one symbol length integration) to obtain despread signals ILp and QLp of the pilot signal.

Each of the above-mentioned fingers is provided with a channel estimation circuit 50 for obtaining a channel estimation value indicating a phase change and an amplitude change due to fading. In this channel estimation circuit 50, pilot symbols Di and D are added to despread signals ILP and QLP of pilot signals.
complex multiply p (prestored). That is, the multipliers 51 and 52 and the adder 53 cause the real part signal Im (=
ILp · Di + QLp · Dp) and the imaginary part signal Qm (=
QLpDi-ILpDp). Averaging circuit 57
Then, using a predetermined number of values for each symbol in the real part signal Im, an average value of values for each predetermined number of symbols is obtained as a real part IH of the channel estimation value, and a value for each symbol in the imaginary part signal Qm is determined by a predetermined number. By using this, the average value of the values for each predetermined number of symbols is obtained as the imaginary part QH of the channel estimation value.

Further, each of the above-mentioned fingers is provided with a synchronous detection circuit 60 for correcting phase fluctuation and amplitude fluctuation in the information signal. In this synchronous detection circuit 60, the despread signals IL and QL of the information signal are complex-multiplied by the channel estimation values IH and QH. That is, the multiplier 61,
62, the adder 63 causes the real part signal Ig (= IL · I
H + QL · QH) and the multipliers 54, 5
5. The imaginary part signal Qg (= QL · IH)
−IL · QH).

The inventors of the present invention have studied the miniaturization (or simplification of arithmetic processing) of the above-described code multiplexed spectrum receiver, and obtained the results shown in FIGS. 4 and 5. Was done. Hereinafter, the spectrum multiplexed spectrum receiver shown in FIGS. 4 and 5 will be described. The configuration shown in FIGS. 4 and 5 corresponds to the configuration shown in FIGS. 2 and 3, and the parts denoted by the same reference numerals as those shown in FIGS. 4 and 5 are the same or equivalent. Is shown.

As shown in FIG. 4, the pilot channel despreading circuit 140 is composed of two adders 141 and 142. The adder 141 outputs the real part ILp ′ of the first correlation value output from the integrator 114A in the first despreading circuit 110A of the DLL circuit 100A and the output from the integrator 124 in the second despreading circuit 120. The real part ILp ″ of the second correlation value is added.

The real part ILp ′ of the first correlation value corresponds to the real part ILp of the despread signal (in the pilot signal) where the phase has advanced by チ ッ プ chip, and the real part ILp of the second correlation value. '' Is the real part I of the despread signal (in the pilot channel) where the phase is delayed by 位相 chip
Lp, the first state in the synchronized state
The real part ILp 'of the correlation value of the second correlation value and the real part IL of the second correlation value
The added value of p ″ is a value substantially equal to the real part ILp of the despread signal of the pilot signal. Similarly, the adder 142
The imaginary part QLp 'of the first correlation value output from the integrator 118A in the first despreading circuit 110A and the imaginary part of the second correlation value output from the integrator 128A in the second despreading circuit 120A QLp ″ is added.

The imaginary part QLp 'of the first correlation value corresponds to the imaginary part QLp of the despread signal (in the pilot signal) where the phase advances by １ ／ chip, and the imaginary part QLp of the second correlation value. ″ Is the imaginary part QLp of the despread signal (in the pilot signal) where the phase is delayed by チ ッ プ chip
In the state where synchronization is established, the imaginary part QLp ′ of the first correlation value and the imaginary part QLp ″ of the second correlation value
Is the imaginary part QL of the despread signal of the pilot signal.
The value is substantially equal to p.

Accordingly, the despreading circuit 14 of the second embodiment
At 0, four multipliers 41, 42, 44, 45 as in pilot channel despreading demodulation circuit 40 shown in FIG.
And the two adders 141 and 142 without using the adders 43 and 47 and the integrators 44 and 48.
The size of the circuit can be reduced, and the current consumption can be reduced.

In the second embodiment, the spreading codes Cip, Cp of the pilot signal in the DLL circuit 100A are used.
The example in which the circuit of the pilot channel despreading demodulation circuit 140 (40) is reduced in size by using the phase control of qp has been described.
In A, the spreading codes Cip, Cqp of the pilot signal
Instead, the phase control of the spread codes Ci and Cq of the information signal is performed, and the circuit of the information signal despreading circuit 20 is downsized using the phase control of the spread codes Ci and Cq. Good.

However, the components shown in FIGS. 1 to 6 are not limited to those configured by hardware, but can be configured by software.
It is understood as a means to realize each function.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a partial configuration of a spectrum receiver according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a part of a partial configuration of a spectrum receiver.

FIG. 3 is a diagram showing the rest of the partial configuration of the spectrum receiver.

FIG. 4 is a diagram showing a part of a partial configuration of a spectrum receiver according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the rest of the partial configuration of the spectrum receiver according to the second embodiment.

FIG. 6 is a diagram showing a partial configuration of a conventional spectrum receiver.

FIG. 7 is a diagram illustrating a relationship between a phase difference and a magnitude of a correlation value.

[Explanation of symbols]

10: quasi-synchronous detection circuit, 30: despreading circuit, 31, 32
... Adder, 100 DLL circuit, 110 despreading (advance angle) circuit, 120 despreading (retardation) circuit, 139 phase control spreading code generator.

Continued on the front page (72) Inventor Isao Hasegawa 1-1-1, Showa-cho, Kariya-shi, Aichi Pref. Denso Corporation (72) Inventor Masayuki Ishikawa 1-1-1, Showa-cho, Kariya-shi, Aichi pref. Inventor, etc. Kuroyagi, 1-1-1 Showa-cho, Kariya-shi, Aichi Pref. Denso Co., Ltd. (72) Inventor Hideyuki Morita 14th Iwatani, Shimoba-Kakucho, Nishio-shi, Aichi F-term in Japan Automobile Parts Research Institute Co., Ltd. (Reference) 5K004 AA05 FG04 FH08 5K022 EE01 EE14 EE36 5K047 AA16 BB01 CC01 EE02 GG27 GG34 HH15 JJ06 LL06 MM13 MM36 MM59

Claims (4)

[Claims] 1. A quasi-synchronous detection means (10) for quasi-synchronous detection of a received signal; And the second correlation value is obtained by despreading the output of the quasi-synchronous detection means with a delay spread code obtained by delaying the phase of the spread code by the predetermined value to obtain the first correlation value. Phase control means (100, 100A) for controlling the phase of the spreading code so that the magnitudes of the second correlation value and the second correlation value become equal.
And a despreading means (30, 140) for outputting a despread signal using the first correlation value and the second correlation value. 2. The quasi-synchronous detection means quasi-synchronizes the sum of a first signal spread by a first spreading code and a second signal spread by a second spreading code as the reception signal. The phase control means (100A) despreads the output of the quasi-synchronous detection means with a leading spreading code obtained by advancing the phase of the first spreading code by a predetermined value, and calculates the first correlation value. The second correlation value is obtained by despreading the output of the quasi-synchronous detection means with a delay spread code obtained by delaying the phase of the first spread code by the predetermined value to obtain the second correlation value. And the phase control in the first spreading code so that the magnitude of the second correlation value becomes equal to the value of the second correlation value. The despreading means (140) performs the phase control on the first correlation value and the second correlation value. Outputting the despread signal of the first signal using Spectrum receiver according to claim 1. 3. A quasi-synchronous detection means (10) for quasi-synchronous detection of a received signal; To obtain a first correlation value, and complexly multiplies the delayed spread code obtained by delaying the phase of the spread code by the predetermined value and the output of the quasi-synchronous detection means to perform correlation detection and perform second correlation. Phase control means (100, 110A) for determining the value of the first correlation value and controlling the phase of the spreading code so that the magnitudes of the first correlation value and the second correlation value become equal. First adding means (31, 141) for adding a real part and a real part of the second correlation value, and a second adding means for adding an imaginary part of the first correlation value and an imaginary part of the second correlation value. 2 adding means (32, 142), wherein the first and second adding means Spectrum receiver comprising the despreading means (30,140) for outputting a despread signal. 4. The quasi-synchronous detection means quasi-synchronizes the sum of a first signal spread by a first spreading code and a second signal spread by a second spreading code as the reception signal. The phase control means (110A) performs complex detection on the output of the quasi-synchronous detection means and the output of the quasi-synchronous detection means by complexly multiplying the output of the quasi-synchronous detection means by the advanced spread code obtained by advancing the phase of the first spread code by a predetermined value. 1 and a complex multiplication of the delayed spreading code obtained by delaying the phase of the first spreading code by the predetermined value and the output of the quasi-synchronous detection means to perform correlation detection and perform the second correlation. And calculating the phase of the first spreading code such that the magnitudes of the first correlation value and the second correlation value are equal. The despreading means (140) As a signal,
4. The first despread signal is output from the first and second adding means (141, 142).
2. The spectrum receiver according to 1.