JP2001177071A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the resistance up of a storage node contact. SOLUTION: The depth of a recess 31 by the overetching of an insulating film 13 when having removed an insulating film 13 over a conductive film 14 is reduced by forming an insulating film 15 on the surface of a conductive film 14, by oxidation treatment or the like of a conductive film 14, and simultaneously performing the etching of the insulating film 15 together with the etching of the insulating film 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device and a method suitable for manufacturing a DRAM having trench cells.

[0002]

2. Description of the Related Art In a conventional trench cell, a BEST (buried trap) is used to reduce the cell size.
Some use cells. In this BEST cell, the connection between the diffusion layer of the transfer gate and the capacitor electrode in the trench is performed on the inner wall of the trench by using the buried contact, and the STI (shallow trench) is formed.
The element isolation width is reduced by performing element isolation by means of isolation.

FIG. 9 is a sectional view showing a part of a manufacturing process of a conventional BEST cell. In FIG. 9A, a Pad film 2 made of silicon oxide is formed on a p-type silicon substrate 1.
And a pad film 3 made of silicon nitride are formed.
A trench 6 is formed in the silicon substrate 1 corresponding to the opening 5 of the ad films 2 and 3. Further, a buried plate 10 is formed in a region below the trench 6, and a conductive film 12 serving as a storage node is embedded via a capacitor insulating film 11. An insulating film 13 made of a silicon oxide film is formed on the side wall of the trench 6 above the capacitor insulating film 11.
A conductive film 14 made of a polycrystalline silicon film is buried in the trench 6 via 3. Here, the conductive film 14
Etching is performed so that the surface of the conductive film 14 is lower than the surface of the p-type silicon substrate 1.

Next, in FIG. 9B, the insulating film 13 is selectively etched by isotropic etching such as wet etching so that the p-type silicon substrate 1 above the conductive film 14 in the trench 6 is exposed. Etch. At this time,
In order to completely remove the insulating film 13 above the conductive film 14 in the trench 6, the insulating film 13 is over-etched. For this reason, the insulating film 1 is larger than the surface of the conductive film 14.
3, the surface of the trench 3 is turned down, and a recess 31 is formed between the sidewall of the trench 6 and the conductive film 14.

Next, a diffusion layer 16 of a transfer gate is formed in the side wall of the trench 6 near the surface of the silicon substrate 1 by obliquely implanting ions into the trench 6.

Next, in FIG. 9C, a conductive film 17 made of polycrystalline silicon is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. At this time, since the thickness of the insulating film 13 is about 75 nm, the width of the concave portion 31 is about 75 nm. As a result, the recess 31 is not completely filled with the conductive film 17, and voids 32 are generated in the recess 31.

Next, CDE (Chemical Dry) is used.
Etching) or the like, the surface of the conductive film 17 is 50n more than the surface of the p-type silicon substrate 1
The conductive film 17 is selectively etched so as to be below m. As a result, a storage node contact connecting the conductive film 12 serving as a storage node and the diffusion layer 16 of the transfer gate via the conductive film 14 is formed in the trench 6.

Next, as shown in FIG. 10, an STI 33 for element isolation is formed by etching the p-type silicon substrate 1. Here, in order to make the buried contact possible only on the side of the transistor,
STI 33 is formed across trench 6.

[0009]

However, in the conventional method of manufacturing a trench DRAM, since the STI 33 is formed across the trench 6, in the oxidation step after the formation of the STI 33, an oxidizing gas is supplied from the side of the STI 33. It enters the void 32. Therefore, there is a problem that the conductive films 14 and 17 around the void 32 are oxidized and the resistance of the storage node contact is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device, which can prevent a storage node contact from having a high resistance.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a trench in a substrate; Forming a buried plate in a predetermined region on the side, forming an insulating film on sidewalls in the trench, filling a conductor in the trench, and etching the conductor to a predetermined depth. A step of forming an insulating layer on the conductor, a step of etching an insulating film formed on the trench sidewall, and a step of etching an insulating layer formed on the conductor. Forming a transfer gate diffusion layer in a region on the substrate side in the trench, and forming a storage node contact connecting the conductor and the diffusion layer in the trench; And a step.

Accordingly, even when a recess is formed between the conductor buried in the trench and the trench side wall because the insulating film formed on the trench side wall is etched, the insulating film is formed on the conductor. By selectively etching the insulating layer, a step between the insulating film formed on the side wall of the trench and the conductor embedded in the trench can be reduced. For this reason, when forming the conductive film serving as the storage node contact, the conductive film serving as the storage node contact can be completely buried in the concave portion, and the occurrence of voids in the concave portion can be prevented. It becomes possible. As a result, it is possible to prevent the resistance of the storage node contact from increasing in the subsequent oxidation step.

Here, it is preferable to simultaneously perform the step of etching the insulating film formed on the trench side wall and the step of etching the insulating layer formed on the conductor.

Further, the insulating layer formed on the conductor has a low selectivity by isotropic etching with the insulating film formed on the side wall of the trench, and has a high selectivity by the isotropic etching with the conductor. Is preferred.

The thickness of the insulating layer formed on the conductor is approximately the same as that of the etching of the insulating layer formed on the conductor and the insulating film formed on the side walls of the trench at the same time. It is preferable to set so as to be peeled.

Further, the insulating layer formed on the conductor is preferably a thermal oxide film.

Further, according to the method of manufacturing a semiconductor device according to the second invention, a step of forming a trench in the substrate;
Forming a buried plate in a predetermined region on the substrate side where the trench is formed, forming an insulating film on a side wall of the trench, embedding a conductor in the trench; A step of etching the insulating film, a step of forming a diffusion layer of a transfer gate in a substrate-side region in the trench, and a step of etching the insulating film based on an etching amount of the insulating film. The method further comprises the steps of: etching a part of the body; and forming a storage node contact in the trench for connecting the conductor and the diffusion layer.

Accordingly, even when a recess is formed between the conductor buried in the trench and the trench side wall because the insulating film formed on the trench side wall is etched, the etching of the conductor can be selectively performed. By doing so, it is possible to reduce the step between the insulating film formed on the trench side wall and the conductor buried in the trench. Therefore, even when a conductive film serving as a storage node contact is formed after etching the insulating film formed on the trench side wall, it is possible to prevent voids from being generated. It is possible to prevent the resistance of the node contact from increasing.

Further, according to the semiconductor device of the present invention, the depth of the concave portion formed between the conductor buried in the trench and the trench side wall via the insulating film on the trench side wall is smaller than that of the concave portion. It is a range that can be embedded with a conductive film formed thereon.

Thus, even when the conductive film serving as a storage node contact is formed on the conductor embedded in the trench after etching the insulating film on the trench side wall, it is possible to prevent generation of voids. This makes it possible to prevent the resistance of the storage node contact from increasing in the subsequent oxidation step.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 5 are sectional views showing the steps of manufacturing a semiconductor device according to the first embodiment of the present invention. In the following embodiments, a method of manufacturing a 64 MDRAM will be described as an example, but the present invention is not limited to this embodiment.

In FIG. 1A, a p-type silicon substrate 1
Pad films 2, 3, and 4 are sequentially stacked on the entire surface by, for example, a method such as CVD or sputtering. Where, for example,
The Pad films 2 and 4 can be silicon oxide films, and the Pad film 3 can be a silicon nitride film. Further, for example, the thickness of the Pad film 2 is 8 nm, the thickness of the Pad film 3 is 220 nm,
The thickness of the ad film 4 can be 700 nm.

Next, by using lithography technology and anisotropic etching technology such as RIE, Pad
The openings 5 are formed in the films 2, 3, and 4. Here, the shape of the opening 5 when viewed from the surface of the p-type silicon substrate 1 may be an oval (brow or oval) having a minor axis of 0.3 μm and a major axis of 0.8 μm.

Next, in FIG. 1B, a trench 6 is formed in the p-type silicon substrate 1 by performing anisotropic etching such as RIE using the Pad film 4 as a mask. Here, the depth of the trench 6 can be, for example, 7 μm. Next, in FIG. 1C, an impurity-containing film 7 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. Here, the impurity-containing film 7 is made of, for example, AsS
G (arsenic mixed silicon oxide film). Further, the thickness of the impurity-containing film 7 can be, for example, 45 nm.

Next, an organic film 8 is formed on the entire surface of the p-type silicon substrate 1.
Is formed by a method such as spin coating. Here, the organic film 8 can be, for example, a photoresist film.

Next, in FIG. 2A, isotropic etching such as CDE (chemical dry etching) is performed so that a part of the organic film 8 remains at the bottom of the trench 6 and Is selectively removed. Here, the etching of the organic film 8 can be performed, for example, so that the surface of the organic film 8 is 1.5 μm below the surface of the p-type silicon substrate 1.

Next, isotropic etching such as wet etching is performed using the organic film 8 as a mask.
The impurity-containing film 7 above the surface of the organic film 8 is selectively removed.

Next, in FIG. 2B, the organic film 8 remaining at the bottom of the trench 6 is selectively removed by performing isotropic etching such as wet etching.

Next, a Cap film 9 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. Here, the Cap film 9
Can be, for example, a silicon oxide film. The thickness of the Cap film 9 can be, for example, 25 nm.

Next, an impurity such as arsenic contained in the impurity-containing film 7 is diffused around the trench 6 in the p-type silicon substrate 1 by performing a heat treatment such as annealing.
A buried plate 10 made of an n-type diffusion layer is formed.
Here, by covering the impurity-containing film 7 with the Cap film 9, it is possible to prevent impurities such as arsenic contained in the impurity-containing film 7 from evaporating into the outside air during the heat treatment.

Next, as shown in FIG. 2C, isotropic etching such as wet etching is performed to obtain the cap film 9 covering the entire surface of the p-type silicon substrate 1 and the impurities remaining at the bottom of the trench 6. The film 7 is selectively removed.

Next, a capacitor insulating film 11 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. here,
The capacitor insulating film 11 is, for example, a silicon oxide film, O
N (silicon oxynitride) film, Ti ₂ O ₅ (tantalum oxide) film, BST (strontium barium titanate)
Film or STO film. The thickness of the capacitor insulating film 11 can be, for example, 30 nm when converted to a silicon oxide film.

Next, in FIG. 3A, a conductive film 12 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. Here, the conductive film 12 can be, for example, a polycrystalline silicon film or a ruthenium (Ru) film.
Further, the thickness of the conductive film 12 can be, for example, 500 nm.

Next, referring to FIG. 3B, by using a planarization technique such as CMP (chemical mechanical polishing),
The conductive film 12 and the capacitor insulating film 11 on the surface of the p-type silicon substrate 1 are removed, and a part of the Pad film 4 is removed.

Next, in FIG. 3C, by performing isotropic etching such as wet etching, Pa
The capacitor insulating film 11 on the side walls of the d film 4 and the pad film 4 is selectively removed.

Next, in FIG. 4A, anisotropic etching such as RIE is performed so that a portion of the conductive film 12 remains at the bottom of the trench 6, and the conductive film 12 is selectively removed. I do. Here, the etching of the conductive film 12 can be performed, for example, so that the surface of the conductive film 12 is 1.3 μm below the surface of the p-type silicon substrate 1.

Next, by performing isotropic etching such as wet etching, the capacitor insulating film 11 above the conductive film 12 is selectively removed, and the p-type silicon on the side wall of the trench 6 above the conductive film 12 is removed. The substrate 1 is exposed.

With the above processing, a storage node made of the conductive film 12 is formed in the trench 6 via the capacitor insulating film 11, and the charge storage layer of the DRAM is
Can be formed within.

Next, in FIG. 4B, an insulating film 13 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. Here, the insulating film 13 can be, for example, a silicon oxide film. Further, the thickness of the insulating film 13 can be, for example, 75 nm.

Next, in FIG. 4C, the insulating film 13 and the conductive film 12 on the surface of the Pad film 3 are left by performing anisotropic etching such as RIE while leaving the insulating film 13 on the side wall of the trench 6. The insulating film 13 on the surface is selectively removed.

Next, in FIG. 5A, a conductive film 14 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. Here, the conductive film 14 can be, for example, a polycrystalline silicon film. Further, the thickness of the conductive film 14 can be, for example, 500 nm.

Next, the conductive film 14 is selectively removed by performing isotropic etching such as CDE so that a part of the conductive film 14 remains in the trench. Here, the etching of the conductive film 14 can be performed, for example, so that the surface of the conductive film 14 is located at a position 110 nm below the surface of the p-type silicon substrate 1.

Next, the conductive film 14 is oxidized or the like.
An insulating film 15 is formed on the surface of the conductive film 14. Here, the insulating film 15 can be, for example, a silicon oxide film. The thickness of the insulating film 15 can be, for example, 75 nm.

It is preferable that the insulating film 15 has a low selectivity by the isotropic etching with the insulating film 13 and a high selectivity by the isotropic etching with the conductive film 14. The thickness of the insulating film 15 is set such that the insulating film 13 above the conductive film 14 is removed by isotropic etching.
Is preferably set so as to be removed at the same time. For example, when the insulating films 13 and 15 are both silicon oxide films, it is preferable that the thicknesses of the insulating films 13 and 15 be made equal.

Next, in FIG. 5B, an isotropic etching such as a wet etching is performed to form an insulating film 1 formed on the side wall of the trench 6 above the conductive film 14.
3 is removed, and p on the side wall of the trench 6 above the conductive film 14 is removed.
The mold silicon substrate 1 is exposed. At this time, the etching of the insulating film 15 is performed simultaneously with the etching of the insulating film 13. For this reason, when the insulating film 13 above the conductive film 14 is removed, the depth of the concave portion 31 is reduced by the thickness of the insulating film 15, and the depth of the concave portion 31 due to over-etching of the insulating film 13 is reduced. Can be.

Next, ions are obliquely implanted into the trench 6 using the pad film 3, the insulating film 13 and the conductive film 14 as a mask, so that the ion implantation is performed in the sidewall of the trench 6 near the surface of the p-type silicon substrate 1. The n-type diffusion layer 16 of the transfer gate is formed in a self-aligned manner.

Next, in FIG. 5C, a conductive film 17 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. At this time, since the depth of the concave portion 31 of the insulating film 13 is small, the concave portion 31 is completely filled with the conductive film 17. Therefore, it is possible to prevent a void from being generated in the concave portion 31 when the conductive film 17 is buried, and it is possible to prevent the storage node contact from having a high resistance due to a later oxidation step. Here, the conductive film 17 can be, for example, a polycrystalline silicon film. Further, the thickness of the conductive film 17 can be, for example, 400 nm.

Next, a portion of the conductive film 17 is left in the trench by isotropic etching such as CDE,
The conductive film 17 is selectively removed. As a result, the conductive film 12
A storage node contact that connects conductive film 14 formed above and n-type diffusion layer 16 is formed in trench 6. Here, the etching of the conductive film 17 is performed, for example, such that the surface of the conductive film 17 is 50 n from the surface of the p-type silicon substrate 1.
m below.

The formation of the insulating film 13 on the side wall of the trench 6 separately from the capacitor insulating film 11
3 is thicker than the capacitor insulating film 11 so that the transfer gate n-type diffusion layer 16 and the n-type buried plate 10
This is to prevent a channel from being formed between them.

Next, the manufacturing process of the semiconductor device according to the second embodiment of the present invention will be described. FIG. 6 and FIG.
FIG. 11 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention. The second embodiment is the same as the first embodiment up to the step of FIG.

In FIG. 6A, after the step of FIG. 4C is completed, a conductive film 14 is formed over the entire surface of the p-type silicon substrate 1 by C.
It is deposited by a method such as VD. Here, the conductive film 14 can be, for example, a polycrystalline silicon film. Further, the thickness of the conductive film 14 can be, for example, 500 nm.

Next, the conductive film 14 is selectively removed by performing isotropic etching such as CDE so that a part of the conductive film 14 remains in the trench. Here, the etching of the conductive film 14 can be performed, for example, so that the surface of the conductive film 14 is located at a position 110 nm below the surface of the p-type silicon substrate 1.

Next, in FIG. 6B, isotropic etching such as wet etching is performed to form an insulating film 1 formed on the sidewall of the trench 6 above the conductive film 14.
3 is removed, and p on the side wall of the trench 6 above the conductive film 14 is removed.
The mold silicon substrate 1 is exposed. At this time, the concave portion 41 of the insulating film 13 is formed between the conductive film 14 and the side wall of the trench 6 due to the over-etching of the insulating film 13.

Next, ions are obliquely implanted into the trench 6 using the Pad film 3, the insulating film 13 and the conductive film 14 as a mask, so that the trench 6 near the surface of the p-type silicon substrate 1 has The n-type diffusion layer 16 of the transfer gate is formed in a self-aligned manner.

Next, anisotropic etching 21 such as RIE
Is performed, a part of the conductive film 14 is selectively removed. As a result, as shown in FIG. 7A, the surface of the conductive film 14 can be made lower than the surface of the concave portion of the insulating film 13.

Next, in FIG. 7B, a conductive film 22 is deposited on the entire surface of the p-type silicon substrate 1 by a method such as CVD. At this time, since the surface of the conductive film 14 is located below the surface of the insulating film 13, no void is generated on the insulating film 13. For this reason, it is possible to prevent the resistance of the storage node contact from increasing due to the subsequent oxidation step. Here, the conductive film 22 can be, for example, a polycrystalline silicon film. The thickness of the conductive film 22 can be, for example, 400 nm.

Next, the conductive film 22 is partially left in the trench by isotropic etching such as CDE.
The conductive film 22 is selectively removed. As a result, the conductive film 12
A storage node contact that connects conductive film 14 formed above and n-type diffusion layer 16 is formed in trench 6. Here, the etching of the conductive film 22 is performed, for example, such that the surface of the conductive film 22 is 50 n from the surface of the p-type silicon substrate 1.
m below.

FIG. 8 is a sectional view showing the structure of a semiconductor device according to the third embodiment of the present invention. In the third embodiment,
The present invention is applied to a substrate plate type trench cell using a substrate as a common plate electrode. By using the substrate plate type trench cell, the leak between trenches can be reduced.

In FIG. 8, an n-well 51 serving as an n-type buried plate is formed on a silicon substrate, and a p-well 52 is formed on the n-well 51. A pad film 53 made of silicon oxide and a pad film made of silicon nitride are formed on the silicon substrate on which the p-well 52 is formed.
A film 54 is formed. A trench 55 is formed in the n-well 51 in the silicon substrate 1 corresponding to the opening 62 of the pad films 53 and 54 via a p-well 52.

Further, in a region below the trench 55,
A conductive film 57 serving as a storage node is embedded via a capacitor insulating film 56. An insulating film 58 is formed on the side wall of the trench 55 above the capacitor insulating film 56, and a conductive film 59 is buried in the trench 55 via the insulating film 58. Here, the conductive film 59 is etched such that the surface of the conductive film 59 is lower than the surface of the silicon substrate.

The trench 55 above the insulating film 58
On the inner side wall, an n-type diffusion layer 60 of a transfer gate is formed, and trenches 6 on insulating film 58 and conductive film 59 are formed.
In 1, a conductive film 61 connecting the conductive film 59 and the n-type diffusion layer 60 is formed.

Here, the depth of the recess formed between the conductive film 59 buried in the trench 55 and the sidewall of the trench 55 via the insulating film 58 on the sidewall of the trench 55 is determined by the depth of the conductive film formed on the recess. This is a range that can be embedded by the film 61.

For this reason, the insulating film 58 on the side wall of the trench 55
Even if conductive film 61 serving as a storage node contact is formed on conductive film 59 buried in trench 55 after etching, voids can be prevented from being generated, and in a subsequent oxidation step, In addition, it is possible to prevent the storage node contact from having a high resistance.

[0065]

As described above, according to the present invention,
Even if a conductive film serving as a storage node contact is formed on a conductor buried in the trench after etching the insulating film on the trench side wall, it is possible to prevent the occurrence of voids, In the oxidation step, it is possible to prevent the resistance of the storage node contact from increasing.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 10A is a plan view showing a structure of a conventional semiconductor device, and FIG. 10B is a cross-sectional view taken along a plane AA in FIG. 10A.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 3, 4, 53, 54 Pad film 5 Opening 6, 55 Trench 7 Impurity containing film 8 Organic film 9 Cap film 10 Beled plate 11, 56 Capacitor insulating film 12, 14, 17, 57, 61 Conductive films 13, 15, 58 Insulating films 16, 60 Diffusion layer 51 N-type well 52 P-type well

Claims (3)

[Claims] A step of forming a trench in a substrate; a step of forming a buried plate in a predetermined region on the substrate side where the trench is to be formed; a step of forming an insulating film on a side wall of the trench; Embedding a conductor in a trench; etching the conductor to a predetermined depth; forming an insulating layer on the conductor; and etching an insulating film formed on a sidewall of the trench. A step of etching an insulating layer formed on the conductor; a step of forming a diffusion layer of a transfer gate in a substrate-side region in the trench; and connecting the conductor and the diffusion layer. Forming a storage node contact in the trench. 2. a step of forming a trench in the substrate; a step of forming a buried plate in a predetermined region on the substrate side where the trench is to be formed; a step of forming an insulating film on a side wall of the trench; A step of embedding a conductor in the trench; a step of etching the conductor to a predetermined depth; a step of etching the insulating film; and forming a diffusion layer of a transfer gate in a substrate-side region in the trench. A step of further etching a part of the conductor based on an etching amount of the insulating film; and a step of forming a storage node contact connecting the conductor and the diffusion layer in the trench. A method for manufacturing a semiconductor device, comprising: 3. The depth of a recess formed between a conductor buried in the trench via an insulating film on the trench side wall and the trench side wall is buried by a conductive film formed on the recess. A semiconductor device characterized by being within a possible range.