JP2001176985A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a CMOS improved in the characteristics of respective nMOS and pMOS transistors. SOLUTION: A work function ΦMn of a gate electrode 6 of nMOS is made into value between electron affinity χs of silicon and an energy difference Φi of intrinsic Fermi level εi of silicon and the vacuum level of silicon, namely, set so as to establish the relation of χs<ΦMn<Φi. Besides, a work function ΦMp of a gate electrode 7 of pMOS is made into value between the added result of the electron affinity χs of silicon and a band gap energy Eg of silicon and the energy difference Φi of the intrinsic Fermi level εi of silicon and the vacuum level of silicon, namely, set so as to establish the relation of Φi<ΦMp<χs+Eg. Thus, in CMOS, the original performance of respective nMOS and pMOS can be effectively utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a complementary field effect transistor used for a memory device or a logic device.
ary Metal Oxide Semiconductor, hereinafter referred to as "CMOS". ).

[0002]

2. Description of the Related Art Conventionally, nMOS (n-channel Metal)
Oxide Semiconductor) and pMOS (p-channel Metal)
Oxide Semiconductor). Hereinafter, a conventional CMOS will be described with reference to FIGS.

First, a conventional CMO will be described with reference to FIGS.
An example of S will be described. FIG. Taur et.
al. , IEDM Tech. Dig. , P. 127
(1993) discloses a polycrystalline silicon in which an nMOS gate electrode is doped with an n-type impurity (hereinafter, referred to as polycrystalline silicon).
It is called “n-type polycrystalline silicon”. ), And a conventional dual-gate CMOS structure using polycrystalline silicon in which a p-type gate electrode is doped with p-type impurities (hereinafter referred to as “p-type polycrystalline silicon”). ing.

As shown in FIG. 7, a conventional CMOS has an element formation region in which a p-type silicon substrate 101 whose main surface is a (100) plane is separated by an element isolation insulating film 102. An n-type well 103 for forming a pMOS and a p-type well 104 for forming an nMOS are formed from the main surface of the element formation region to a predetermined depth. On the semiconductor substrate 101 in the nMOS region and the pMOS region, the gate insulating films 105a, 105
05b are respectively formed. Gate insulating film 105
An n-type polysilicon gate electrode 116 and a p-type polysilicon gate electrode 117 are formed on a and 105b.

On both sides of the gate insulating films 105a and 105b, the n-type polysilicon gate electrode 116 and the p-type polysilicon gate electrode 117, source / drain regions 109 of an nMOS region into which n-type impurities are implanted, respectively.
And the source of the pMOS region into which the p-type impurity is implanted /
A drain region 110 is formed. On both sides of the source / drain regions 109 and 110, the source / drain region 112 of the nMOS into which the n-type impurity is implanted and the source / drain region 1 of the pMOS into which the p-type impurity is implanted
13 are formed respectively.

On the source / drain regions 112 and 113, refractory metal silicide layers 114a and 114b for reducing contact resistance between the source / drain regions 112 and 113 and other conductive layers are formed, respectively. . Further, n-type polycrystalline silicon gate electrode 116 and
On the upper surface of the p-type polycrystalline silicon gate electrode 117, a refractory metal silicide layer 114a for reducing the contact resistance between the gate electrode 116, 117 and another conductive layer is also provided.
114b are respectively formed. Gate insulating film 10
5a, both side walls of n-type polycrystalline silicon gate electrode 116 and refractory metal silicide layer 114a, gate insulating film 105b, p-type polycrystalline silicon gate electrode 11
Sidewall insulating films 111a and 111b are formed on both side walls of the metal silicide layer 114b and the refractory metal silicide layer 114b, respectively.

The dual gate C constructed as described above
In the MOS, the conductivity types of the impurities of the nMOS and the pMOS are all symmetrical. for that reason,
The feature is that both nMOS and pMOS transistors can be designed with the same guidelines.

FIGS. 8 and 9 schematically show energy band diagrams of the channel region when the gate voltage of each of the nMOS and pMOS is not applied. Hereinafter, a conventional CMOS will be described with reference to FIGS.
The energy state near the gate insulating film will be described.

First, the nMOS will be described. nMO
The n-type polycrystalline silicon gate electrode 116 of S is heavily doped with n-type impurities. The work function Φn of the n-type polycrystalline silicon gate electrode 116 is substantially the same as the electron affinity シ リ コ ン s of silicon. In this case, since the Fermi level εi of silicon in the channel region matches the Fermi level εf of polycrystalline silicon in the gate electrode,
In the vicinity of the gate insulating film, the intrinsic Fermi level εi of silicon in the channel region tends to approach the Fermi level εf of polycrystalline silicon of the gate electrode. Therefore, as shown in FIG. 8, the energy band structure at a gate voltage of 0 V is such that the conduction band .epsilon.c is greatly lowered on the surface of the channel region, that is, the conduction band .epsilon.c of silicon in the channel region is n-type of the gate electrode. The state becomes closer to the Fermi level εf of polycrystalline silicon. Therefore, the threshold voltage becomes low. In such a case, in order to set the threshold voltage to an appropriate value, that is, to keep the conduction band εc of silicon in the channel region away from the Fermi level εf of n-type polysilicon of the gate electrode, Usually, the p-type impurity concentration near the surface of the channel region of the p-type well is increased.

However, by increasing the p-type impurity concentration near the surface of the channel region of the p-type well, the electric field becomes strong near the surface of the channel region.
Carrier mobility is reduced. Further, since polycrystalline silicon, which is a semiconductor, is used as the gate electrode, a depletion layer is formed near the interface between the gate insulating film and the gate electrode, so that the capacity of the gate electrode is reduced.

Next, the pMOS will be described. pMO
The S p-type polycrystalline silicon gate electrode 17 is heavily doped with p-type impurities. The work function Φp of the p-type polycrystalline silicon gate electrode 17 is approximately the same as the sum of the electron affinity シ リ コ ン s of silicon and the band gap energy Eg. In this case, since the Fermi level εi of silicon in the channel region matches the Fermi level εf of polycrystalline silicon in the gate electrode, the intrinsic Fermi level εi of silicon in the channel region is close to the gate insulating film. An attempt is made to approach the Fermi level εf of the polycrystalline silicon of the electrode. Therefore, as shown in FIG. 9, the energy band structure at a gate voltage of 0 V is a state in which the valence band εv is greatly increased on the surface of the channel region, that is, the valence band εv of silicon in the channel region.
Is the Fermi level εf of p-type polycrystalline silicon for the gate electrode
It becomes a state approaching. Therefore, the threshold voltage becomes low. Even in such a case, in order to set the threshold voltage to an appropriate value, that is, to keep the valence band εv of silicon in the channel region away from the Fermi level εf of p-type polycrystalline silicon of the gate electrode. ,Normal,
The n-type impurity concentration near the surface of the channel region of the n-type well is increased.

However, by increasing the n-type impurity concentration near the surface of the channel region of the n-type well, the electric field becomes strong near the surface of the channel region.
Carrier mobility is reduced. Furthermore, a problem that a depletion layer is formed near the interface between the gate electrode and the gate insulating film occurs similarly to the nMOS, and the capacitance of the gate electrode is reduced. In the case of p-type polycrystalline silicon, it is difficult to implant boron as an impurity at a high concentration.
The phenomenon in which a depletion layer is formed in the vicinity of the interface between the gate electrode and the gate insulating film appears more remarkably than in the case of.

On the other hand, it is conceivable to use the same conductivity type polycrystalline silicon film as the gate electrode for the nMOS and the pMOS. For example, instead of the p-type polysilicon gate electrode 117 shown in FIG. 7, an n-type polysilicon gate electrode 116 is used as shown in FIG. The same type, ie, single gate CMOS
It is conceivable to use.

However, when a single-gate CMOS is used and the same channel structure as that of the CMOS shown in FIG. 7 is used, the energy band structure of the pMOS channel region is as shown in FIG. In other words, contrary to the energy band structure of FIG. 9, the valence band εv slightly lowers on the surface of the channel region of the n-type well. Therefore, the Fermi level εf of the polysilicon in the gate electrode and the Fermi level εi of the silicon in the channel region
Is significantly different from the above. Therefore, the threshold voltage increases significantly. Therefore, in order to set the threshold voltage to an appropriate value, it is necessary to form a p-type counter-doped layer 118 having a conductivity type opposite to that of the n-type well near the channel surface of the pMOS. By providing this p-type counter-doped layer 118, a so-called buried channel structure is formed, and as shown in FIG. 12, the valence band εv at a portion away from the surface of the channel region by a predetermined distance is raised. Thereby, in a portion away from the surface of the channel region by a predetermined distance, the difference between the Fermi level εf of polycrystalline silicon of the gate electrode and the valence band εv of silicon in the channel region is reduced. As a result, the threshold voltage can be set to an appropriate value in a portion away from the channel region surface by a predetermined distance. Further, since the p-type impurity is implanted into the n-channel region, the electric field on the surface of the channel region slightly increases unlike the channel region having the energy band structure shown in FIG. Therefore, a decrease in carrier mobility in the channel region can be suppressed.

However, in the case of the buried channel structure,
Problems such as deterioration of short channel characteristics and increase of sub-threshold coefficient occur. Such a phenomenon also occurs when a single gate structure is formed using p-type polycrystalline silicon for the gate electrode of the nMOS.

[0016]

As described above, an n-type polycrystalline silicon or a p-type polycrystalline silicon is
In the conventional CMOS used as the gate electrode of
In addition to the problem that the capacitance of the gate electrode decreases due to the depletion of the gate electrode, the mobility of carriers near the surface of the channel region decreases due to the increase in the electric field near the surface of the channel region. In such a case, problems such as deterioration of short channel characteristics and increase in subthreshold coefficient occur. As a result, in a CMOS structure,
The original performances of the MOSFETs of the nMOS and the pMOS cannot be sufficiently exhibited. However, performance may be improved by using a material other than polycrystalline silicon for the gate electrode. However, there is no clear guide for the work function of the material.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object the purpose of nMOS and pMO.
An object of the present invention is to provide a semiconductor device having a CMOS structure in which an optimum work function as a gate electrode of each S is clarified and transistor characteristics of each of an nMOS and a pMOS are improved.

[0018]

According to a first aspect of the present invention, there is provided a semiconductor device having a complementary field effect transistor including n-type and p-type field effect transistors formed using a silicon substrate. The device, wherein the work function of the gate electrode of the n-type field-effect transistor is larger than the electron affinity of silicon, at least in the vicinity of the gate insulating film, and is smaller than the energy difference between the intrinsic Fermi level of silicon and the vacuum level of silicon. The work function of the gate electrode of the p-type field-effect transistor is set to be smaller than the energy difference between the intrinsic Fermi level of silicon and the vacuum level of silicon at least near the gate insulating film, and the electron affinity of silicon And the bandgap energy.

By providing such a structure, nM
The work functions of the gate electrodes of the OS and the pMOS are set to appropriate values different from the work functions of the n-type polysilicon or the p-type polysilicon. Thus, since it is not necessary to implant impurities into the channel region, the electric field intensity on the surface of the channel region is reduced, and a decrease in carrier mobility is suppressed. In addition, even when the buried channel structure is not formed, an appropriate threshold voltage can be set. As a result, it is possible to obtain a semiconductor device including a CMOS in which the transistor characteristics of the nMOS and the pMOS are improved without increasing the sub-threshold coefficient and deteriorating the short channel characteristics.

According to a second aspect of the present invention, there is provided a semiconductor device comprising:
2. The semiconductor device according to claim 1, wherein the work function of the gate electrode of the n-type field effect transistor is 4.11 eV.
４4.41 eV, and the work function of the gate electrode of the p-type field effect transistor is 4.71 eV.
It is set in the range of 5.01 eV.

With such a structure, the work function is set in a range near the optimum value, and thus a semiconductor device having a CMOS having a high driving force is obtained.

According to a third aspect of the present invention, there is provided a semiconductor device comprising:
3. The semiconductor device according to claim 1, wherein a gate electrode of the n-type field-effect transistor includes a first conductive layer on a gate insulating film side and a first conductive layer formed on the first conductive layer. 4. And a second conductive layer having a low resistance value, wherein the gate electrode of the p-type field effect transistor is formed on the third conductive layer on the gate insulating film side and on the third conductive layer. And a fourth conductive layer having a lower resistance value.

By providing such a structure, pM
In order to form a material having a work function suitable for each of the OS and the nMOS near each gate electrode and the gate insulating film, even if a material having a high resistance value is selected as the first and third conductive layers, the first and third conductive layers may be formed. Since the second and fourth conductive layers having low resistance values are formed on the respective third conductive layers, the resistance value of the entire gate electrode can be reduced. As a result, it is possible to further improve the performance of each of the nMOS and pMOS transistors in the CMOS.

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
4. The semiconductor device according to claim 3, wherein the first and the third
The conductive layer is formed of a metal film.

With such a structure, formation of a depletion layer between the gate insulating film and the gate electrode is prevented. Thereby, the performance of the CMOS gate electrode is improved. As a result, the performance of the semiconductor device including the CMOS is improved.

According to a fifth aspect of the present invention, in the semiconductor device according to the third or fourth aspect, the first conductive layer is formed of aluminum, titanium, vanadium, gallium, niobium, or silver. , Indium and thallium, the third conductive layer may include one or more materials selected from the group consisting of cobalt, ruthenium, and tellurium. .

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising:
The semiconductor device according to claim 3, wherein
The second and fourth conductive layers include at least one of aluminum and copper.

By forming the second and fourth conductive layers with such a metal film, even if a material having a high resistance value is used for the first and third conductive layers, the entire gate electrode has high conductivity. It becomes possible.

According to a seventh aspect of the present invention, there is provided a semiconductor device comprising:
The semiconductor device according to claim 3, wherein
A barrier metal layer for preventing mutual diffusion between the first conductive layer and the second conductive layer between each of the gate electrodes of the n-type and p-type field-effect transistors between the first conductive layer and the second conductive layer Further comprising, between the third conductive layer and the fourth conductive layer,
The semiconductor device further includes a barrier metal layer that prevents mutual diffusion between the third conductive layer and the fourth conductive layer.

With such a structure, the mutual diffusion between the first conductive layer and the second conductive layer and the mutual diffusion between the third conductive layer and the fourth conductive layer can be suppressed.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. In the semiconductor device of the present embodiment, as shown in FIG. 1, first, an element formation region separated by an element isolation insulating film 2 is formed on a p-type silicon substrate 1 whose main surface is a (100) plane. ing. An n-type well 3 for forming a pMOS and a p-type well 4 for forming an nMOS are formed from the main surface of the element formation region to a predetermined depth.

Gate insulating films 5a and 5b are formed on the semiconductor substrate 1 in the n-type well 3 region and the p-type well 4 region, respectively. A gate electrode 6 made of a first metal film and a gate electrode 7 made of a second metal film having a different conductivity from the first metal film are formed on the gate insulating films 5a and 5b, respectively. However, the gate electrode 6 made of the first metal film and the gate electrode 7 made of the second metal film have different work functions. On gate electrode 6 and gate electrode 7, insulating films 8a and 8b used as a gate etching mask remain.

The source / drain region 9 of the nMOS region into which the n-type impurity is implanted and the source / drain region 9 of the pMOS region into which the p-type impurity is implanted are formed in regions in the semiconductor substrate 1 near both ends of the gate insulating films 5a and 5b. / Drain region 10 is formed. Source / drain regions 9, 10
NMOS with n-type impurities implanted on each side
Are formed, and a pMOS source / drain region 13 into which a p-type impurity is implanted is formed.

On the source / drain regions 12, 13, refractory metal silicide layers 14a, 14b for reducing contact resistance between the source / drain regions 12, 13 and other conductive layers are formed, respectively. . Sidewall insulating films 11a and 11b are provided on both side walls of gate insulating film 5a, gate electrode 6 and insulating film 8a, and on both side walls of gate insulating film 5b, gate electrode 7 and insulating film 8b.
b are formed respectively.

Next, the nMO of the semiconductor device of the present embodiment will be described.
S will be described. NM of the semiconductor device of the present embodiment
FIG. 2A schematically shows the energy band of the channel portion of the OS when the gate voltage is not applied. As can be seen from FIG. 2A, the work function ΦMn of the gate electrode 6 of the nMOS is changed by the electron affinity シ リ コ ン of silicon.
It is set to a value between s and the energy difference Φi between the intrinsic Fermi level εi of silicon and the vacuum level of silicon, that is, the value is set such that the relationship χs <ΦMn <Φi is satisfied. Thereby, the nMOS of the semiconductor device of the present embodiment is
In the case where the gate voltage is 0 V, the conduction band εc of silicon in the vicinity of the surface of the channel region in the energy band structure decreases as shown in FIG.
It becomes smaller than the lowering of the conduction band εc of S silicon. That is, the conduction band εc of silicon and the first metal film 6 forming the gate electrode in the vicinity of the surface of the channel region of the nMOS of the semiconductor device of the present embodiment shown in FIG.
Is different from the Fermi level εf of the conventional n shown in FIG.
Silicon conduction band ε near the surface of the MOS channel region
It is slightly larger than the difference between c and the Fermi level εf of the first metal film 6 constituting the gate electrode.

Therefore, the threshold voltage has an appropriate value. This eliminates the need to increase the concentration of the p-type impurity in the vicinity of the channel surface in order to set the threshold voltage to an appropriate value. As a result, the electric field in the vicinity of the surface of the channel region can be suppressed low, so that a decrease in the mobility of carriers near the surface of the channel region can be suppressed.

More specifically, when ΦMn = χs, as shown in FIG. 2B, in the energy band structure, the conduction band εc decreases greatly near the surface of the channel region. Therefore, similarly to the nMOS of the semiconductor device shown in the prior art, the silicon conduction band εc near the surface of the channel region and the first electrode forming the gate electrode are formed.
The difference from the Fermi level εf of the metal film 6 becomes smaller than an appropriate value. Therefore, the threshold voltage becomes smaller than an appropriate value. Therefore, it is necessary to increase the p-type impurity concentration near the surface of the channel region in order to set the threshold voltage to an appropriate value. As a result, the electric field on the surface of the channel region becomes strong, and the mobility of carriers decreases. Therefore, the driving capability of the nMOS when ΦMn = χs is ΦM
NMO of the semiconductor device of the present embodiment when Mn> χs
It is lower than S.

However, according to the structure of the semiconductor device of the present embodiment, as shown in FIG.
Since s is set to s, the manner in which the conduction band εc decreases near the surface of the channel region is smaller than in the case of FIG.
Therefore, in order to set the threshold voltage to an appropriate value,
It is not necessary to increase the concentration of the p-type impurity near the surface of the channel region. As a result, the electric field in the vicinity of the surface of the channel region can be suppressed low, so that it is possible to suppress a decrease in the mobility of carriers in the vicinity of the surface of the channel region.

On the other hand, when ΦMn = Φi, it is necessary to make a buried channel structure in order to set the threshold voltage to an appropriate value, and the energy band structure becomes a structure as shown in FIG. . In the buried channel structure, it is more difficult to control the potential of the channel region by the gate electrode than in the surface channel structure. As a result, the short channel characteristics deteriorate and the sub-threshold coefficient increases. As a result, by setting the threshold voltage higher to suppress the sub-threshold leakage current, the driving capability of the nMOS decreases.

However, according to the structure of the semiconductor device of the present embodiment, since the gate electrode is formed so as to satisfy the condition of ΦMn <Φi, the threshold voltage can be set to an appropriate value even in the surface channel structure. Can be set to Therefore, it is not necessary to set a higher threshold voltage in order to suppress a sub-threshold leakage current, which is required when the buried channel structure is used.
As a result, a decrease in the driving capability of the nMOS is suppressed.

The first metal film is used as a gate electrode. Therefore, no depletion layer is formed near the interface between the gate electrode 6 made of the first metal film and the gate insulating film 5a. Therefore, the capacitance of the gate electrode 6 does not decrease.

Next, the pMO of the semiconductor device of the present embodiment will be described.
S will be described. PM of the semiconductor device of the present embodiment
FIG. 3A schematically shows the band of the channel portion of the OS when the gate voltage is not applied. FIG. 3 (a)
As can be seen from FIG. 7, the work function ΦMp of the gate electrode 7 formed of the pMOS second metal film is changed by the electron affinity シ リ コ ン of silicon.
s and the energy difference Φi between the intrinsic Fermi level εi of silicon and the vacuum level of silicon, that is,
It is set so that the relationship of Φi <ΦMp <χs + Eg is satisfied. Thereby, the pMO of the semiconductor device of the present embodiment is
In the energy band structure of S when the gate voltage is 0 V, the rise of the valence band εv on the surface of the channel region is higher than the rise of the valence band εv of the pMOS shown in FIG. Become smaller. That is, the nMO of the semiconductor device of this embodiment shown in FIG.
Valence band εv of silicon near the surface of the channel region of S
And the Fermi level ε of the first metal film 6 forming the gate electrode
is slightly larger than the difference between the valence band εv of silicon near the surface of the channel region of the conventional pMOS shown in FIG. 9 and the Fermi level εf of the second metal film 7 forming the gate electrode. Become.

Therefore, the threshold voltage has an appropriate value. Thus, as in the case of the nMOS, it is not necessary to increase the concentration of the n-type impurity near the surface of the channel region in order to set the threshold voltage to an appropriate value. for that reason,
The electric field near the surface of the channel region can be kept low. As a result, a decrease in carrier mobility on the surface of the channel region can be suppressed.

More specifically, ΦMp = χs +
In the case of Eg, as shown in FIG. 3B, the energy band structure is such that the rise of the valence band εv near the surface of the channel region increases the valence band εv of the pMOS of the semiconductor device of the present embodiment. A little bigger than. Therefore, in order to set the threshold voltage to an appropriate value, it is necessary to increase the concentration of the n-type impurity near the surface of the channel region. Thereby, the electric field on the surface of the pMOS channel region becomes stronger. As a result, the mobility of carriers is reduced, and the driving capability of the pMOS is reduced.

However, according to the structure of the semiconductor device of the present embodiment, as shown in FIG.
To set s + Eg, the rise of the valence band εv on the surface of the channel region of the pMOS depends on the rise of the valence band εv on the surface of the channel region of the pMOS of the semiconductor device when ΦMp = χs + Eg shown in FIG. Smaller. As a result, as in the case of the nMOS, it is not necessary to increase the concentration of the n-type impurity near the surface of the channel region for setting the threshold voltage to an appropriate value. Thus, the electric field near the surface of the pMOS channel region can be suppressed low, so that the decrease in carrier mobility near the surface of the pMOS channel region can be suppressed.

On the other hand, when ΦMp = Φi, a buried channel structure must be used to set the threshold voltage to an appropriate value, and the energy band structure becomes a structure as shown in FIG. This makes it more difficult to control the potential of the channel region by the gate electrode in the buried channel structure than in the surface channel structure. for that reason,
Deterioration of short channel characteristics and an increase in subthreshold coefficient occur. Therefore, it is necessary to set a higher threshold voltage in order to suppress the sub-threshold leakage current. As a result, the driving capability of the pMOS is reduced.

However, according to the semiconductor device of the present embodiment, by setting ΦMp> Φi, the threshold voltage can be set to an appropriate value in the surface channel structure. Therefore, it is not necessary to set a higher threshold voltage in order to suppress a sub-threshold leakage current required in the case of a buried channel structure. As a result, a decrease in the driving capability of the pMOS is suppressed.

Since the second metal film is used as the gate electrode, depletion does not occur near the interface between the gate electrode 7 and the gate insulating film 5b. Therefore, the gate electrode 7
Does not occur.

As described above, in the semiconductor device of this embodiment, the work function ΦMn of the gate electrode 6 made of the first metal film of the nMOS and the work function ΦMp of the gate electrode 7 made of the second metal film of the pMOS are It has been described that by setting to an appropriate value, a decrease in carrier mobility in the vicinity of the surface of the channel region can be suppressed.
How the characteristics of the MOS and pMOS transistors are affected will be described based on the results of investigation using device simulation.

FIG. 4 shows that the gate length Lg = 0.12 μm,
The thickness tox of the gate insulating film = 2 nm, the power supply voltage Vdd = 1.
The ON current Ion of the nMOS at 2 V, that is, the drain current and the drain voltage when the drain voltage and the gate voltage are 1.2 V shows the ΔΦMSn dependency, that is, the Φi−ΦMn dependency. FIG. 5 shows the ON current Ion of the pMOS, that is, the ΔΦMSp dependency of the drain current when the drain voltage and the gate voltage are 1.2 V, that is, Φi−Φ
Shows Mp dependence. Further, the off current Ioff, that is,
The threshold voltage is controlled by optimizing the channel structure according to the work function of the gate electrode so that the drain current at a drain voltage of 1.2 V and a gate voltage of 0 V is constant at 1 nA / μm.

As can be seen from FIGS. 4 and 5, nMO
In both S and pMOS, the value of the ON current Ion depends on ΔΦMSn and ΔΦMSp, and it can be seen that there are optimal values of ΔΦMSn and ΔΦMSp for maximizing the ON current Ion, respectively. Also, nMO
In S, Ion decreases when ΔΦMSn increases to the positive side, and Ion decreases when ΔΦMSp increases to the negative side in pMOS because the electric field on the surface of the channel region increases and the mobility of carriers decreases. It is.

Further, for both nMOS and pMOS, ΔΦ
The reason why Ion decreases even when MSn and ΔΦMSp approach 0 is that it is necessary to use a buried channel structure in order to make the threshold voltage appropriate, and the sub-threshold coefficient increases. .

As can be seen from FIGS. 4 and 5, n
In MOS, 0.2 eV <ΔΦMSn <0.5 e
In the pMOS, −
By setting the relation of 0.4 eV <ΔΦMSp <−0.1 eV, the performance of the CMOS can be improved. Therefore, Φi = 4.61 eV at room temperature
Therefore, in the nMOS, the work function of the gate electrode near the gate insulating film is set to 4.11 eV <ΦMn <4.4.
For 1 eV and pMOS, the work function of the gate electrode near the gate insulating film is 4.71 eV <ΦMp <5.01.
It can be seen that, if they are formed so that the relationship of eV holds, the performance of each of the nMOS and the pMOS can be improved.

Further, Δs = 4.05 and Eg = 1.1
2 eV, χs <Φ in the nMOS described above.
Mn <Φi holds, and in the pMOS, Φi <ΦMp
<Χs + Eg holds. From this, nMO
In each of S and pMOS, it can be said that the threshold voltage can be set to an appropriate value without excessive impurity implantation using the surface channel structure. Therefore, the work function of the nMOS gate electrode near the gate insulating film is 4.11 eV <ΦMn <4.41 eV, pMO
3. The work function of the S gate electrode near the gate insulating film
If 71 eV <ΦMp <5.01 eV, the CMO
It is possible to obtain the above-described effect of preventing the drive capability of the S from lowering, and to enhance the performance.

In the above, it has been described that the performance of the CMOS can be improved by setting the work function of the gate electrode to an appropriate value. However, in the following, the work function of the gate electrode is set to an appropriate value. Describe how to set. As a method of setting the work function of the gate electrode to an appropriate value,
First, there is a method of changing the material of the gate electrode itself. For example, M. Sze, Physics of
Semiconductor Devices, 2n
d ed. , P251, J.M. Wiley and So
As disclosed in ns, New York (1981), the work function differs depending on the material. Therefore, it is conceivable to improve the performance of the CMOS by using a material having an appropriate work function as the gate electrode of each of the nMOS and the pMOS. For example, the work function of the nMOS gate electrode is 4.3e.
V aluminum, vanadium with a work function of 4.35 eV, gallium with a work function of 4.3 eV, work function 4.35
niobium at eV, silver at work function 4.3 eV, work function 4.
Indium with 2 eV and thallium with a work function of 4.3 eV are suitable. As the pMOS gate electrode, cobalt having a work function of 5.0 eV and work function of 4.8 were used.
Ruthenium with an eV and tellurium with a work function of 5.0 eV are suitable.

Further, even when the same material is used for the gate electrode, the K.I. Nakajima et
a. , Symp. VLSI Tech. Dig. , P9
5 (1999), a titanium nitride film is formed by reactive sputtering using a mixed gas of argon and nitrogen without heating, or TiCl ₄
The work function can be appropriately set depending on whether or not to perform chemical vapor deposition at 450 ° C. using NH ₃ and NH ₃ gas. Using this method, even if the same material is used for each of the nMOS and the pMOS, the work function can be optimized by changing the film forming conditions.

Further, for example, M. Kakumu et
al. , IEDM Tech. Dig. , P. 415
(1985), a film thickness of 0.35 μm
A silicon-rich molybdenum silicide film is deposited by sputtering, arsenic is ion-implanted into the silicon-rich molybdenum silicide film at a dose of 1 × 10 ¹⁵ cm ⁻² , and then dry oxidation is performed at 900 ° C. ,
The work function of the molybdenum silicide film can be set to 4.4 eV. In addition, boron is implanted into the silicon-rich molybdenum silicide film in an amount of 1 × 10
The work function of the molybdenum silicide film can be set to 4.9 eV by performing ion implantation under the condition of ¹² cm ⁻² and then performing dry oxidation at 900 ° C. According to this method, the work function of the gate electrode near the gate insulating film can be adjusted by doping impurities by ion implantation. Therefore, considering the conductivity of the entire gate electrode, n
It is not necessary to form each of the MOS and pMOS gate electrodes in a two-layer structure. Therefore, a gate electrode set to an appropriate work function can be formed by one film formation process, so that the manufacturing process of the semiconductor device can be simplified.

Second Embodiment Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 6, the semiconductor device of the present embodiment has a structure substantially similar to that of the semiconductor device of the first embodiment shown in FIG. 1, except that the gate electrode 6 of the nMOS has a lower first metal layer. The difference is that the gate electrode 7 of the pMOS is composed of the lower third metal film 17 and the upper fourth metal film 15b.

The work function of the gate electrode material near the interface between the gate electrodes 6 and 7 and the gate insulating films 5a and 5b originally affects the threshold voltage and the like. The work function of the gate electrode material above the vicinity of the interface with the films 5a and 5b does not affect the threshold voltage. Therefore, in the CMOS of the present embodiment,
As shown in FIG. 6, the gate electrodes 6 and 7 and the gate insulating film 5
The first and third metal films 16 and 17 having an appropriate work function are arranged only near the interface between the gate electrodes a and 5b, and the resistance is set above the vicinity of the interface between the gate electrode and the gate insulating films 5a and 5b. Second and fourth metal films 15a, 15 having a small value
b, for example, by arranging aluminum or copper or the like, gate electrodes 6 and 7 having a two-layer structure are formed.

The first metal film 16 and the second metal film 15a
Between the first metal film 16 and the second metal film 15a and between the third metal film 17 and the fourth metal film 15a in order to suppress mutual diffusion between the first metal film 16 and the fourth metal film 15b. Metal film 1
It is more preferable to have a multilayer structure in which a barrier metal film such as a titanium nitride film is inserted between each of the layers 5b.

With such a structure, the first metal film 16 and the third metal film 17 having appropriate work functions are provided near the interfaces between the gate electrodes 6 and 7 and the gate insulating films 5a and 5b.
Are disposed, the first metal film 16 and the third metal film 1
7, the second and fourth metal films 15
If a material having a small resistance value is used for a and 15b, the overall resistance value of each of the gate electrodes 6 and 7 can be reduced. Therefore, a semiconductor device provided with a CMOS in which the performance of each of the nMOS and the pMOS is improved without lowering the conductivity of the entire gate electrodes 6 and 7 is formed.

It should be noted that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0064]

According to the semiconductor device of the present invention, the work functions of the gate electrodes of the nMOS and the pMOS are different from those of the n-type polysilicon or the p-type polysilicon. Set to an appropriate value. This eliminates the need for impurity implantation for adjusting the threshold voltage, so that the electric field intensity near the surface of the channel region decreases. Therefore, a decrease in the mobility of carriers near the surface of the channel region is suppressed. Even when the buried channel structure is not formed, an appropriate threshold voltage can be set, so that an increase in sub-threshold coefficient and deterioration of short channel characteristics do not occur. Therefore, pMO
The performance of each of the S and nMOS is improved.

According to the semiconductor device of the third aspect of the present invention, even if a material having a large resistance value is selected as the first and third conductive layers in order to use a material having an appropriate work function, Since the second and fourth conductive layers having small resistance values are formed on the first and third conductive layers, respectively, the resistance value of the entire gate electrode can be suppressed low. As a result, nM can be obtained without deteriorating the conductivity of the gate electrode.
The performance of each of the OS and the pMOS is improved.

According to the semiconductor device of the fourth aspect of the present invention, since the formation of a depletion layer between the gate insulating film and the gate electrode is prevented, the conductivity of the gate electrode is improved. The performance of the semiconductor device is improved.

According to the semiconductor device of the sixth aspect of the present invention, by limiting the material of the second and fourth conductive layers as described above, the first and third conductive layers are made of a material having a high resistance value. Can realize the function of increasing the conductivity of the entire gate electrode.

According to the semiconductor device of the present invention, the mutual diffusion between the first conductive layer and the second conductive layer and the mutual diffusion between the third conductive layer and the fourth conductive layer are prevented. Can be suppressed.

[Brief description of the drawings]

FIG. 1 schematically illustrates a cross-sectional structure of a CMOS according to a first embodiment of the present invention.

FIGS. 2A and 2B are diagrams for explaining the effectiveness of the CMOS according to the first embodiment of the present invention; FIG. 2A illustrates energy in the depth direction near the channel region of an nMOS in the CMOS according to the first embodiment of the present invention; It is a figure which shows a band, (b) and (c) are figures which show the energy band of the depth direction near the channel region of nMOS when the work function of the gate electrode of nMOS becomes a boundary condition.

FIGS. 3A and 3B are diagrams for explaining the effectiveness of the CMOS according to the first embodiment of the present invention; FIG. 3A illustrates the energy in the depth direction near the channel region of the pMOS in the CMOS according to the first embodiment of the present invention; FIGS. 4B and 4C are diagrams illustrating energy bands in the depth direction near the channel region of the pMOS when the work function of the gate electrode of the pMOS is a boundary condition. FIGS.

FIG. 4 shows a CMOS according to the first embodiment of the present invention.
FIG. 9 is a diagram illustrating the work function dependence of the ON current of the nMOS based on the result of the simulation.

FIG. 5 shows a CMOS according to the first embodiment of the present invention.
FIG. 6 is a diagram illustrating the work function dependence of the ON current of a pMOS based on a simulation.

FIG. 6 is a diagram schematically illustrating a cross-sectional structure of a CMOS according to a second embodiment of the present invention;

FIG. 7 is a diagram schematically showing a cross-sectional structure of a conventional CMOS having a dual gate structure.

8 is a CM having a conventional dual gate structure shown in FIG.
FIG. 4 is a diagram illustrating an energy band in a depth direction near a channel region of an nMOS in an OS.

FIG. 9 shows a conventional CM having a dual gate structure shown in FIG.
FIG. 4 is a diagram illustrating an energy band in a depth direction near a channel region of a pMOS in an OS.

FIG. 10 is a diagram schematically showing a cross-sectional structure of a conventional CMOS having a single gate structure.

FIG. 11 shows a conventional p-type CMOS having a single gate structure shown in FIG.
FIG. 3 is a diagram illustrating an energy band in a depth direction near a channel region of a MOS.

FIG. 12 is a cross-sectional view of a conventional single-gate CMOS shown in FIG.
FIG. 3 is a diagram illustrating an energy band in a depth direction near a channel region of a MOS.

[Explanation of symbols]

1 silicon substrate, 2 element isolation insulating film, 3 n-type well, 4 p-type well, 5a, 5b gate insulating film, 6,
7 gate electrode, 8a, 8b insulating film, 9 n-type source / drain region, 10 p-type source / drain region, 1
1 sidewall insulating film, 12 n-type source / drain regions, 13 p-type source / drain regions, 14 a, 1
4b refractory metal silicide film, 15a second metal film,
15b fourth metal film, 16 first metal film, 17 third metal film, 116 n-type polycrystalline silicon gate electrode, 117
p-type polysilicon gate electrode, 118 p-type counter-doped layer.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiyuki Oishi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Katsuomi Shiozawa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F term (reference) in Ryo Denki Co., Ltd.

Claims (7)

[Claims] 1. A semiconductor device comprising a complementary field-effect transistor including an n-type and p-type field-effect transistor formed using a silicon substrate, wherein a work of a gate electrode of the n-type field-effect transistor is performed. The function is set to be larger than the electron affinity of silicon and smaller than the energy difference between the intrinsic Fermi level of silicon and the vacuum level of silicon at least in the vicinity of the gate insulating film, and the work of the gate electrode of the p-type field effect transistor The function is set to be larger than the energy difference between the intrinsic Fermi level of silicon and the vacuum level of silicon at least in the vicinity of the gate insulating film, and smaller than the sum of the electron affinity of silicon and the band gap energy of silicon. Semiconductor device. 2. The work function of the gate electrode of the n-type field effect transistor is set in a range of 4.11 eV to 4.41 eV, and the work function of the gate electrode of the p-type field effect transistor is 4.71 eV to 5.01 e
The semiconductor device according to claim 1, wherein the semiconductor device is set in a range of V. 3. The n-type field-effect transistor, wherein the gate electrode is formed on a first conductive layer on the gate insulating film side of the n-type field-effect transistor, and on the first conductive layer. A second conductive layer having a lower resistance than the first conductive layer, wherein the gate electrode of the p-type field effect transistor is a third conductive layer on the gate insulating film side of the p-type field effect transistor. 3. The semiconductor device according to claim 1, further comprising: a fourth conductive layer formed on the third conductive layer and having a lower resistance than the third conductive layer. 4. 4. The semiconductor device according to claim 3, wherein said first and third conductive layers are formed of a metal film. 5. The first conductive layer includes one or two or more substances selected from the group consisting of aluminum, titanium, vanadium, gallium, niobium, silver, indium and thallium, wherein the third conductive layer comprises Including one or more substances selected from the group consisting of cobalt, ruthenium and tellurium,
The semiconductor device according to claim 3. 6. The semiconductor device according to claim 3, wherein each of said second and fourth conductive layers contains at least one of aluminum and copper. 7. The gate electrode of the n-type field effect transistor, wherein the gate electrode is disposed between the first conductive layer and the second conductive layer, and is disposed between the first conductive layer and the second conductive layer. The p-type field effect transistor further includes a barrier metal layer that prevents diffusion,
7. The semiconductor device according to claim 3, further comprising a barrier metal layer between the third conductive layer and the fourth conductive layer, the barrier metal layer preventing interdiffusion between the third conductive layer and the fourth conductive layer. 3. The semiconductor device according to claim 1.