JP2001176884A - Field-effct transistor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor that can suppress the phase shift of an amplifying signal, and to provide its manufacturing method. SOLUTION: This field-effect transistor has a semi-insulating GaAs substrate 1, impurities layer 120, undoped GaAs buffer layer 2, undoped AlGaAs buffer layer 3, undoped GaAs buffer layer 4, n-type GaAs channel layer 5, gate electrode 15, source electrode 19, and drain electrode 18. The impurity layer 120 contains n-type impurities, p-type impurities, and oxygen. Furthmore, the layer thickness of the undoped GaAs buffer layer 4 is formed 10 nm to 100 nm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to a field effect transistor having excellent high frequency characteristics and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a power amplifier such as a high-output amplifier for handling a high-frequency signal and an amplifier used for satellite communication or a portable telephone, a field-effect transistor (FET) using a compound semiconductor capable of high-output and high-speed response is used. ing. FIG. 8 is a schematic diagram showing the structure of a field-effect transistor.

As shown in FIG. 8, a field effect transistor comprises a semi-insulating GaAs substrate 201, an undoped GaAs buffer layer 202 having a thickness of 800 nm, and a
m undoped AlGaAs buffer layer 203, undoped GaAs buffer layer 204 having a thickness of 5 nm, and layer thickness 150 doped with 2 × 10 ¹⁷ cm ^{−3 of} silicon
nm n-type GaAs channel layer 205 and silicon
An n-type AlGaAs Schottky layer 206 having a thickness of 20 nm doped with × 10 ¹⁷ cm ⁻³ and 5 × 1 of silicon
0 ¹⁷ cm ^-3 doped 150 nm thick n-type G
It is composed of an aAs contact layer 207, a gate electrode 215, an ohmic metal 217, a drain electrode 218, a source electrode 219, and a back electrode 221.

The basic characteristics of the field effect transistor configured as described above are that the maximum drain current (Imax) is 3
80 mA / mm (gate-source voltage (Vgs) = +
1V), and the saturation drain current (Idss) is 280 mA /
mm (gate-source voltage (Vgs) = 0 V), and transconductance (gm) is 130 mS / mm (gate
The source-to-source voltage (Vgs) = 0 V) and the drain-gate withstand voltage (BVgd) was 18 V.

When the drain voltage (Vds) is changed from 2 V to 10 V, the relationship between the drain voltage (Vds) and the threshold voltage (Vth) is as shown in FIG. The characteristic that the threshold voltage (Vth) changes by about −50 mV was shown.

[0006]

The input / output characteristics of a field effect transistor (gate width 1.5 mm) having such basic characteristics were measured at a frequency of 4 GHz (C band). In this measurement, the bias point is set at the drain voltage of 7
The test was performed at a place where the drain current was narrowed down to a value corresponding to 15% of the saturated drain current (Idss) at V. The input / output matching state of the field effect transistor was adjusted to match the efficiency. Then, with reference to the output phase at a low input power, a change in the output phase when the input power was increased was measured. FIG. 9 shows the measurement results. As shown in FIG. 9, as the input power increases, the output phase changes to the positive (+) side (phase distortion), and the amount of phase change until the output saturation (phase shift) is about 23 degrees. Was.

In general, power amplifiers are required to operate with low distortion and high efficiency. Therefore, the field effect transistor used in the power amplifier has phase distortion (phase shift).
There is a demand that the size be further reduced. This is because a large phase shift causes a problem in the performance of the power amplifier.

Japanese Patent Application Laid-Open No. Hei 6-232164 proposes a field effect transistor in which a GaAs or InGaAs buffer layer contains silicon and oxygen directly bonded thereto. However, Japanese Patent Application Laid-Open No. 6-232164
The publication only discloses that inter-element interference and soft error due to the injection of minority carriers are significantly reduced, but does not disclose phase distortion (phase shift) at all.

Further, Japanese Patent Application Laid-Open No. 61-194878 discloses that by providing an oxygen injection layer below a channel region of a GaAs field-effect transistor, variations in threshold voltage can be reduced. However, since the oxygen injection layer is provided below the channel region, the fluctuation of the threshold voltage is small, and for example, phase distortion (phase shift) increases at a bias point where the drain current is reduced.

[0010] The phase distortion (phase shift) at the bias point where the drain current is reduced is caused by
Mainly the transconductance (g) of the field effect transistor
m) and the drain conductance (gd) are considered to be affected by nonlinearity near the pinch-off, and appear in the form of phase distortion. The pinch-off characteristics of the field-effect transistor are affected by the structure of the buffer layer and the interface between the semi-insulating GaAs substrate and the buffer layer.

The present invention has been made in view of the above problems, and has as its object to provide a field effect transistor having excellent high-frequency characteristics and a method of manufacturing the same. Another object of the present invention is to provide a field effect transistor capable of suppressing a phase shift of an amplified signal and a method for manufacturing the same.

[0012]

To achieve the above object, a field-effect transistor according to a first aspect of the present invention comprises a channel layer, a gate electrode, A field effect transistor having a source electrode and a drain electrode, wherein an impurity layer containing an n-type impurity, a p-type impurity, and oxygen is provided at an interface between the substrate and the buffer layer.

In this configuration, an impurity layer containing an n-type impurity, a p-type impurity, and oxygen is provided at the interface between the substrate and the buffer layer, and the change in the threshold voltage (Vth) with respect to the drain voltage (Vds) increases. . Therefore, the pinch-off property of the field effect transistor is slightly reduced, and the non-linearity of the mutual conductance (gm) and the drain conductance (gd) near the threshold voltage is reduced. As a result, changes in the mutual conductance (gm) and the drain conductance (gd) in the vicinity of the threshold voltage are reduced, and the phase shift of the amplified signal can be suppressed.

The substrate is composed of, for example, a semi-insulating GaAs substrate. The buffer layer includes, for example, a first undoped GaAs buffer layer, an undoped AlGaAs buffer layer, and a second undoped GaAs buffer layer from the semi-insulating GaAs substrate side.

When the thickness of the second undoped GaAs buffer layer is 10 nm to 100 nm, the change in the threshold voltage (Vth) with respect to the drain voltage (Vds) is further increased, and the phase shift of the amplified signal can be suppressed.

The n-type impurity is 1 × 10 ¹² cm ⁻² to
3 × 10 ¹³ cm ⁻² and the p-type impurity is 1 × 1
^{0 12 cm -2 ~1 × 10 13} cm -2 is included, when the oxygen is contained ^{1 × 10 12 cm -2 ~5 ×} 10 13 cm -2, particularly, the threshold voltage (Vth for the drain voltage (Vds) ) Is increased, and the phase shift of the amplified signal can be suppressed.

The p-type impurity is composed of, for example, at least one element of carbon, zinc, magnesium and beryllium. The n-type impurity is, for example, silicon,
It is composed of at least one element of sulfur, selenium, and tin.

The threshold voltage with respect to the drain voltage applied to the drain electrode is-
When the voltage changes by 100 mV to -300 mV, a state where the pinch-off property of the field effect transistor is slightly reduced can be created, and the phase shift of the amplified signal can be suppressed.

A method of manufacturing a field-effect transistor according to a second aspect of the present invention includes forming a buffer layer on a substrate made of a compound semiconductor, and forming a source electrode and a drain electrode on the buffer layer via a channel layer. And a method of manufacturing a field-effect transistor for forming a gate electrode, comprising: forming an impurity layer containing an n-type impurity, a p-type impurity, and oxygen on the substrate; and forming the buffer layer on the impurity layer. It is characterized by the following.

In this configuration, an impurity layer containing an n-type impurity, a p-type impurity, and oxygen is formed on the substrate, and the change in the threshold voltage (Vth) with respect to the drain voltage (Vds) increases. Therefore, the pinch-off property of the field effect transistor is slightly reduced, and the transconductance (g) near the threshold voltage is reduced.
m) and the non-linearity of the drain conductance (gd) are reduced. As a result, changes in the mutual conductance (gm) and the drain conductance (gd) in the vicinity of the threshold voltage are reduced, and the phase shift of the amplified signal can be suppressed.

The substrate is composed of, for example, a semi-insulating GaAs substrate. The buffer layer is formed in three layers, for example, a first undoped GaAs buffer layer, an undoped AlGaAs buffer layer, and a second undoped GaAs buffer layer from the semi-insulating GaAs substrate side.

When the thickness of the second undoped GaAs buffer layer is 10 nm to 100 nm, the change in the threshold voltage (Vth) with respect to the drain voltage (Vds) is further increased, and the phase shift of the amplified signal can be suppressed.

The n-type impurity is 1 × 10
^{12 cm -2 ~3 × 10 13 cm} - 2 contained, the p-type impurity ^{1 × 10 12 cm -2 ~1 ×} 10 13 cm -2
1 × 10 ¹² cm ^{−2 to} 5 × 10
^{When 13} cm ^{−2 is} included, the drain voltage (Vd
s), the change of the threshold voltage (Vth) becomes large,
The phase shift of the amplified signal can be suppressed.

The p-type impurities include, for example, carbon, zinc,
At least one element of magnesium and beryllium is used. Further, for the n-type impurity, for example, at least one element of silicon, sulfur, selenium, and tin is used.

When the impurity layer is formed on the semi-insulating GaAs substrate by planar doping the n-type impurity, the p-type impurity and the oxygen, the n-type impurity
The controllability of the concentration of the type impurities and oxygen is improved.

[0026]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a schematic diagram of a field-effect transistor according to the present embodiment.

As shown in FIG. 1, an impurity layer 120 is formed on a semi-insulating GaAs substrate 1 of a field effect transistor. The impurity layer 120 has a thickness of, for example, 0.1 nm to
10 nm is formed. The impurity layer 120 contains an n-type impurity, a p-type impurity, and oxygen (O ₂ ).

The n-type impurity is, for example, silicon (S
i), at least one element of sulfur (S), selenium (Se), and tin (Sn) (any one or a plurality of elements). This n-type impurity is, for example,
By doping in areal density of ^{1 × 10 12 cm -2 ~3 ×} 10 1 3 cm -2, contained in the impurity layer 120. In this embodiment, the n-type impurity is composed of silicon and sulfur, and silicon (Si) is 1.5 × 10 ^13.
cm ⁻² and sulfur (S) are doped at an area density of 1 × 10 ¹² cm ⁻² .

The p-type impurities include, for example, carbon (C), zinc (Zn), magnesium (Mg), beryllium (Be)
Is composed of any one element or a plurality of elements. This p-type impurity is, for example, 1 × 10 ¹² cm ^−2.
It is included in the impurity layer 120 by being doped at an area density of about 1 × 10 ¹³ cm ⁻² . In this embodiment, the p-type impurity is composed of carbon, and carbon is 3 × 10
It is doped at an area density of ¹² cm ⁻² .

The oxygen is, for example, 1 × 10 ¹² cm ⁻² to
By being doped at an area density of 5 × 10 ¹³ cm ⁻² , the semiconductor layer is included in the impurity layer 120. In the present embodiment, oxygen is doped at an area density of 1 × 10 ¹³ cm ⁻² .

On the impurity layer 120, undoped GaAs
An s buffer layer 2 is formed. Undoped GaAs
The buffer layer 2 is formed, for example, to a thickness of 800 nm. On the undoped GaAs buffer layer 2, an undoped AlGaAs buffer layer 3 is formed. The undoped AlGaAs buffer layer 3 has a thickness of, for example, 200 n.
m.

On the undoped AlGaAs buffer layer 3, an undoped GaAs buffer layer 4 is formed. The undoped GaAs buffer layer 4 has, for example, a thickness of 1
0 nm to 100 nm, and the conventional undoped Ga
It is formed thicker than the As buffer layer. It is preferable that the thickness of the undoped GaAs buffer layer 4 be around 50 nm.

On the undoped GaAs buffer layer 4,
An n-type GaAs channel layer 5 is formed. n-type Ga
The As channel layer 5 is made of silicon, for example, 2 × 10¹⁷
cm ^-3Formed by doping, the layer thickness is
For example, it is formed to have a thickness of 150 nm.

On the n-type GaAs channel layer 5, an n-type A
An lGaAs Schottky layer 6 is formed. n-type Al
The GaAs Schottky layer 6 is made of silicon, for example, 2 × 1
0 is formed by ^{1 7} cm ^-3 doping layer thickness is formed, for example, to 20 nm.

On the n-type AlGaAs Schottky layer 6,
An n-type GaAs contact layer 7 is formed. n-type G
The aAs contact layer 7 is made of silicon, for example, 5 × 10
It is formed by doping at ¹⁷ cm ⁻³ , and has a layer thickness of, for example, 150 nm.

On the n-type AlGaAs Schottky layer 6, a gate electrode 15 is formed. Gate electrode 1
5 is a Schottky metal made of, for example, WSi, TiN
And a barrier metal such as TiPt or Au. On the gate electrode 15, a protective film 16 is formed so as to cover the gate electrode 15. The protection film 16 is formed of, for example, SiO ₂ or SiN.

The drain electrode 1 is formed on the n-type GaAs contact layer 7 via an ohmic metal 17 for making an ohmic contact with the n-type GaAs contact layer 7.
8 and a source electrode 19 are formed. The drain electrode 18 and the source electrode 19 are formed by Au plating. Further, a back electrode 21 is formed below the semi-insulating GaAs substrate 1.

Next, a description will be given of a method of manufacturing the field effect transistor configured as described above. FIG.
(F) is a schematic diagram for explaining the outline of the manufacturing process flow of the field-effect transistor.

First, the semi-insulating G which has been subjected to the crystal growth pretreatment
On the aAs substrate 1, for example, silicon as an n-type impurity is 1.5 × 10 ¹³ cm ⁻² and sulfur is 1 × 10 ¹² c.
m ^{- 2,} carbon as a p-type impurity 3 × ¹⁰ 12 cm
⁻² and oxygen are planar-doped at an area density of 1 × 10 ¹³ cm ⁻² to form an impurity layer 120.

Next, as shown in FIG. 2A, an undoped GaAs buffer is formed on a semi-insulating GaAs substrate 1 which has been subjected to a crystal growth pretreatment by using, for example, metal organic chemical vapor deposition (MOVPE). The growth from the layer 2 to the n-type GaAs contact layer 7 is performed. At this time, the n-type or p-type residual carrier concentration of the undoped buffer layer, 1E15 cm ^{- 3}
The growth is performed under such a condition that the size becomes smaller.

Subsequently, as shown in FIG. 2B, portions other than the ohmic electrodes such as the drain electrode 18 and the source electrode 19, for example, the wide recess portion 9 and the field portion 10 are formed by a crystal dry etching apparatus. Etching is performed up to the n-type AlGaAs Schottky layer 6 using the photoresist 8 as a mask. Then, boron (B ⁺ ) is ion-implanted to insulate the outside 11 of the operation region of the field-effect transistor. This ion implantation is performed to a depth reaching the undoped GaAs buffer layer 2.

Next, as shown in FIG. 2C, a gate oxide film 12 is formed on the wide recess 9 and the field 10. Then, using the photoresist 13 as a mask, an opening 14 for forming a Schottky gate is formed in the wide recess 9 by an insulating film dry etching apparatus. The width of the opening 14, that is, the gate length is 0.5 μm
Formed.

After the opening 14 is formed, as shown in FIG. 2D, a Schottky metal made of WSi, a barrier metal made of TiPt, and Au are formed on the opening 14 and the photoresist 13 by sputtering. Then, portions other than the opening 14 are removed to form the gate electrode 15. After removing the gate oxide film 12, a protective film 16 made of, for example, SiO _{2 is formed} so as to cover the gate electrode 15.

Next, as shown in FIG.
An ohmic metal 17 is formed on the As contact layer 7. Then, a drain electrode 18, a source electrode 19, and a via-hole electrode 20 made of Au plating are formed on the ohmic metal 17, and the surface process is completed.

Finally, as shown in FIG. 2F, the semi-insulating GaAs substrate 1 is polished to a thickness of 40 μm to reduce thermal resistance, and a via hole 22 reaching the via-hole electrode 20 is formed by dry etching. After that, the back electrode 21 is formed by Au plating, and the field effect transistor is manufactured.

Next, the basic characteristics of the field effect transistor manufactured as described above were examined. Specifically, the drain voltage (Vds) is changed from 2 V to 10 V, and the drain voltage (Vds) and the threshold voltage (Vt) during this period are changed.
h) was measured. The result is shown in FIG. As shown in FIG. 3, it has been confirmed that the threshold voltage (Vth) per drain voltage (Vds) changes by about -160 mV.

As for other basic characteristics, the maximum drain current (Imax) is 380 mA / mm (gate-source voltage (Vgs) = + 1 V), and the saturated drain current (Idss) is 280 mA / mm (gate-source Voltage (Vgs) = 0 V), transconductance (gm) is 130 mS / mm (gate-source voltage (Vgs) =
0V), withstand voltage (BVgd) between drain and gate of 18V
This is similar to the conventional field effect transistor.

Further, the input / output characteristics of the field effect transistor (gate width 1.5 mm) having such basic characteristics were measured at a frequency of 4 GHz (C band). The bias point and the input / output matching conditions are the same as in the conventional example.
Was set at a place corresponding to and adjusted to match efficiency. And
When the phase shift characteristics were measured, as shown in FIG.
The phase shift accompanying the increase in input power was ± 3 degrees or less up to output saturation (2 dB output compression point). The efficiency of the field effect transistor was 60% as in the conventional case.

As described above, the phase shift is changed from 23 degrees to ± 3 degrees.
The reason why the impurity voltage can be greatly reduced to less than or equal to that is that the drain voltage (Vds) can be obtained by providing the impurity layer 120 at the interface between the semi-insulating GaAs substrate 1 and the undoped GaAs buffer layer 2.
Of the threshold voltage (Vth) with respect to
This is because the voltage has increased from mV to about -160 mV in the present embodiment. Further, an undoped GaAs buffer layer 4
Formed to a thickness of 10 to 100 nm (thicker than before)
Therefore, the change of the threshold voltage (Vth) with respect to the drain voltage (Vds) is further increased. As a result, a state in which the pinch-off property of the field-effect transistor is slightly reduced as compared with the conventional field-effect transistor can be created.

As a result, the nonlinearity of the mutual conductance (gm) and the drain conductance (gd) near the threshold voltage is reduced. As a result, the mutual conductance (gm) and the drain conductance (g
The change in d) becomes gentle, and the phase shift of the amplified signal can be suppressed.

In order to confirm the scope of application of the present invention, the areal densities of n-type impurities, p-type impurities, and oxygen to be doped were examined. By doping in the following ranges, the phase shift of the amplified signal was suppressed. I confirmed that I can do it. 1 × 10 ¹² cm ⁻² ≦ n-type impurity ≦ 3 × 10 ¹³ cm
⁻² 1 × 10 ¹² cm ⁻² ≦ p-type impurity ≦ 1 × 10 ¹³ cm
⁻² 1 × 10 ¹² cm ⁻² ≦ oxygen ≦ 5 × 10 ¹³ cm ⁻²

Therefore, by using the epitaxial substrate on which the impurity layer 120 in which the n-type impurity, the p-type impurity, and oxygen are present in this range is formed, the change in the threshold voltage (Vth) with respect to the drain voltage (Vds) can be reduced. For example, it can be increased to -100 mV to -300 mV. Therefore, the phase shift of the amplified signal can be suppressed.

Further, when the layer thickness of the undoped GaAs buffer layer 4 was examined, the phase shift of the amplified signal was further suppressed by setting the layer thickness of the undoped GaAs buffer layer 4 to 10 nm to 100 nm, more preferably 40 nm to 60 nm. I confirmed that I can do it.

Semi-insulating GaAs substrate 1 and undoped Ga
FIG. 5 shows the result of SIMS (secondary ion mass spectrometry) of the impurity layer 120 provided between the As layers 2. For comparison, FIG. 10 shows the result of SIMS (secondary ion mass spectrometry) of a conventional field-effect transistor having no impurity layer 120. As shown in FIG. 5, semi-insulating GaAs
It was confirmed that a doped impurity was present between the substrate 1 and the undoped GaAs layer 2 (between the substrate and the buffer layer).

As described above, according to this embodiment, since the impurity layer 120 is provided at the interface between the semi-insulating GaAs substrate 1 and the undoped GaAs buffer layer 2, the threshold voltage (Vds) with respect to the drain voltage (Vds) is obtained. Vth) can be increased. Therefore, the phase shift of the amplified signal can be suppressed.

Further, according to the present embodiment, the thickness of the undoped GaAs buffer layer 4 is set to 10 nm to 100 nm.
Therefore, the change in the threshold voltage (Vth) with respect to the drain voltage (Vds) can be further increased,
Further, the phase shift of the amplified signal can be suppressed.

The present invention is not limited to the above embodiment. For example, a substrate made of a compound semiconductor is not limited to the semi-insulating GaAs substrate 1 and exhibits high electron mobility. Any mixed crystal semiconductor made of a group III-V compound or the like may be used.

As shown in FIG. 6, the field effect transistor may have a general MESFET structure in which the GaAs layer 5 is a Schottky layer. Further, as shown in FIG. 7, an undoped InGaAs channel layer 51 is formed on the undoped GaAs buffer layer 4.
Alternatively, a structure in which the n-type AlGaAs electron supply layer 61 is formed may be used. Also in the case of these structures, the phase shift of the amplified signal can be suppressed.

Semi-insulating GaAs substrate 1 and undoped Ga
The method of providing the impurity layer 120 at the interface of the As buffer layer 2 is not limited to planar doping, and may be, for example, a molecular beam epitaxial method (MBE method). In this case, it is preferable that the time of the heat treatment time in the MBE furnace is shortened, and the crystal growth is performed in a state where the impurities and natural oxide films adsorbed on the wafer surface after the pre-treatment of the semi-insulating GaAs substrate 1 are appropriately left.

The method for growing crystals from the undoped GaAs buffer layer 2 to the n-type GaAs contact layer 7 is not limited to the metal organic chemical vapor deposition, but may be, for example, a molecular beam epitaxy (MBE). Is also good.

The combination of the n-type impurity and the p-type impurity is not limited to the present embodiment. In addition to the combination of silicon and sulfur as the n-type impurity, for example, any one element of selenium, tin, silicon, and sulfur, or a combination of these elements may be used. Further, in addition to carbon, any one element of zinc, magnesium, and beryllium, or a combination thereof may be used as the p-type impurity.

Further, the concentrations of oxygen, n-type impurities and p-type impurities are not limited to the present embodiment. However, these concentrations are set to 1 × 10 ¹² cm ^{−2 to} 5% in order to effectively suppress the phase shift of the amplified signal.
× 10 ¹³ cm ⁻² , the concentration of the n-type impurity is 1 × 10 ¹²
cm ^{−2 to} 3 × 10 ¹³ cm ⁻² , and the concentration of the p-type impurity is preferably 1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ^−2.

[0063]

As described above, according to the present invention,
The phase shift of the amplified signal can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a field-effect transistor according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining an outline of a manufacturing through process of the field-effect transistor according to the embodiment of the present invention.

FIG. 3 shows a threshold voltage (Vth) and a drain voltage (Vds) of an embodiment of the present invention and a conventional field-effect transistor.
6 is a graph showing the relationship of.

FIG. 4 is a graph showing input / output / efficiency characteristics and phase shift characteristics of the field effect transistor according to the embodiment of the present invention.

FIG. 5 is a SIMS profile of an epitaxial substrate used for the field-effect transistor according to the embodiment of the present invention.

FIG. 6 is a schematic view of a field-effect transistor according to another embodiment.

FIG. 7 is a schematic diagram of a field-effect transistor according to another embodiment.

FIG. 8 is a schematic view of a conventional field-effect transistor.

FIG. 9 is a graph showing input / output / efficiency characteristics and phase shift characteristics of a conventional field effect transistor.

FIG. 10 is a SIMS profile of an epitaxial substrate used for a conventional FET field-effect transistor.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating GaAs substrate 2 undoped GaAs buffer layer 3 undoped AlGaAs buffer layer 4 undoped GaAs buffer layer 5 n-type GaAs channel layer 18 drain electrode 19 source electrode 120 impurity layer

Claims (14)

[Claims] 1. A method according to claim 1, wherein a channel layer, a gate electrode, a source electrode,
A field-effect transistor having a drain electrode, wherein an n-type impurity and a p-type impurity are provided at an interface between the substrate and the buffer layer.
A field-effect transistor having an impurity layer containing a type impurity and oxygen. 2. The field effect transistor according to claim 1, wherein said substrate is formed of a semi-insulating GaAs substrate. 3. The semiconductor device according to claim 2, wherein the buffer layer is formed of the semi-insulating GaAs.
A first undoped GaAs buffer layer, an undoped AlGaAs buffer layer, and a second undoped Ga
3. The field effect transistor according to claim 2, comprising an As buffer layer. 4. The field effect transistor according to claim 3, wherein the second undoped GaAs buffer layer has a thickness of 10 nm to 100 nm. 5. The method according to claim 1, wherein the n-type impurity is 1 × 10 ¹² cm ⁻² or ^less .
3 × 10 ¹³ cm ⁻² and the p-type impurity is 1 × 1
5. The method according to claim 1, wherein said oxygen is contained in an amount of 0 ¹² cm ^-2 to 1 x 10 ¹³ cm ^-2 , and said oxygen is contained in an amount of 1 x 10 ¹² cm ^{-2 to} 5 x 10 ¹³ cm ^-2 . 2. The field-effect transistor according to claim 1. 6. The p-type impurity comprises at least one element of carbon, zinc, magnesium and beryllium, and the n-type impurity comprises at least one element of silicon, sulfur, selenium and tin. The field-effect transistor according to claim 1, wherein: 7. The method according to claim 7, wherein a threshold voltage of the drain voltage applied to the drain electrode is-
The field-effect transistor according to claim 1, wherein the voltage varies from 100 mV to −300 mV. 8. A buffer layer is formed on a substrate made of a compound semiconductor, and a source electrode and a source electrode are formed on the buffer layer via a channel layer.
A method of manufacturing a field-effect transistor for forming a drain electrode and a gate electrode, comprising: forming an impurity layer containing an n-type impurity, a p-type impurity, and oxygen on the substrate; and forming the buffer layer on the impurity layer. A method for manufacturing a field effect transistor. 9. The method according to claim 8, wherein said substrate comprises a semi-insulating GaAs substrate. 10. The semiconductor device according to claim 10, wherein said buffer layer is formed of said semi-insulating GaAs.
a first undoped GaAs buffer layer, an undoped AlGaAs buffer layer, and a second undoped G
The method for manufacturing a field effect transistor according to claim 9, wherein the method is formed in three layers including an aAs buffer layer. 11. The method according to claim 10, wherein the second undoped GaAs buffer layer has a thickness of 10 nm to 100 nm. 12. The semiconductor device according to claim 1, wherein said n-type impurity is 1 × 1 in said impurity layer.
^{0 12 cm -2 ~3 × 10 13} cm - 2 included, the p
1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm
^-2, and the oxygen is contained in an amount of 1 × 10 ¹² cm ^{−2 to} 5 × 1
0 ¹³ cm ^-2 is included, the method of manufacturing the field effect transistor according to any one of claims 8 to 11, characterized in that. 13. The method according to claim 1, wherein at least one element of carbon, zinc, magnesium and beryllium is used as said p-type impurity, and at least one element of silicon, sulfur, selenium and tin is used as said n-type impurity. The method for manufacturing a field-effect transistor according to any one of claims 8 to 12. 14. The method according to claim 14, wherein said n-type impurity and said p-type
2. The impurity layer according to claim 8, wherein the impurity layer is formed by planar doping with a type impurity and the oxygen.
3. The method for manufacturing a field-effect transistor according to claim 1.