JP2001175700A - Pair arrangement rule check method and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of a semiconductor integrated circuit device by automatically making a rule check on elements constituting a pair and reducing characteristic defects of an analog circuit. SOLUTION: The distance between elements constituting a pair generated according to circuit diagram data and pair information is calculated. It is decided whether or not the element distance is larger than a rule value and when so, the names of the elements constituting the pair and the element distance are stored as an element distance rule violation. Then the parallelism of the pair is retrieved from a pair arrangement rule, and rotation parameters of the elements constituting the pair are retrieved from layout data and compared according to the pair arrangement rule to judge whether or not their directions are the same. When the directions are not the same, the name of the elements constituting the pair and the rotation parameters of the elements are stored as an identical directivity violation. After all pairs are checked, those violation data are displayed on the display.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for checking layout rules of a semiconductor device, and more particularly to a technology effective when applied to rule checking of pairs in a semiconductor device constituting an analog circuit.

[0002]

2. Description of the Related Art Performance requirements for an analog circuit in a semiconductor integrated circuit device include reducing offset voltage and gain variation.

According to studies made by the present inventor, when designing such an analog circuit, a specific element in the analog circuit is specified as a pair by a layout tool at the time of layout design, so that characteristics due to variation in element failure and the like are determined. Prevents defects. Here, the term “pair” refers to a pair of elements for which specific accuracy becomes a problem during circuit design.

For example, a bipolar transistor used in a current mirror circuit, an operational amplifier circuit, and the like,
In this case, it is required that the base-emitter voltage V _BE ratio accuracy be several mV or less and that the resistance ratio accuracy be several percent or less.

In order to realize these specific accuracy, it is necessary to arrange the elements to be paired in the same direction and close arrangement in the layout design. Pair arrangement rules such as arrangement of elements forming a pair in the same direction, close arrangement, and the like make uniform the size variation of elements and the influence of heat and noise on the elements from the periphery.

As an example describing in detail the layout design technique of this type of semiconductor device, see the semiconductor handbook editorial committee (ed.) Published by Ohm Co., Ltd. on December 25, 1991, “Semiconductor Handbook ( Second
Version) ”P595 to P608, and this document includes a layout CAD (Computer Aided Des).
i)) is described.

[0007]

However, the present inventor has found that the following problems are encountered in the element pair designation technique using the layout tool as described above.

That is, the pair specified by the layout tool always moves as a pair.
If an ideal layout of a pair cannot be made due to layout restrictions such as a reduction in the area of the semiconductor chip,
The designer releases the designation of the pair and places the elements.

In this case, after the layout design, the layout check of the pair has to be performed by the designer himself or herself, and there is a problem that the man-hour and time are taken. Further, since there is no clear rule in the layout check, there is a problem that the performance of the semiconductor integrated circuit device varies due to the skill of the operator who performs the check.

[0010] It is an object of the present invention to provide a method of automatically checking the rules of elements forming a pair, reducing the characteristic failure in an analog circuit, and improving the yield of a semiconductor integrated circuit device, and a method of checking a pair arrangement rule. It is to provide a storage medium.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the pair placement rule checking method of the present invention includes a step of storing circuit diagram data, pair information, layout data, and pair placement rule check data composed of a pair placement rule; Generating and calculating a distance between elements constituting the pair, a step of determining whether or not the calculated distance between elements of the pair is larger than a prescribed rule value; and If the value is also larger, the step of storing the element distance rule violation data of the pair in the data storage unit, the step of detecting the same directionality in the pair, and the rotation parameter of the element forming the pair, Comparing the rotation parameters to determine whether the directions are considered to be the same; and, if the directions are not the same, determining the direction of the pair. And storing the violation data to the data storage unit, the data storage stored inter-element distance violate portion, and a step of displaying on display means a pair to be the direction identity violations as violations pair.

Further, in the pair arrangement rule checking method according to the present invention, the inter-element distance rule violation data includes a name of an element forming a pair and an inter-element distance, and the same directionality violation data forms a pair. And the rotation parameter of the element.

Further, in the pair arrangement rule checking method of the present invention, the elements of the violating pair are displayed by highlighting, blinking, or instructing by violating display lines.

In the pair arrangement rule checking method according to the present invention, when the displayed pair violates an inter-element distance, an actually measured distance and a rule value are displayed in the vicinity of the pair, and the displayed pair is displayed. In the case of the violation of the direction identity, the symmetry and the rotation status are displayed near the pair.

Further, the storage medium of the present invention generates a pair from previously stored pair information and circuit diagram data, and stores the layout coordinates of the elements constituting the pair as one of the previously stored pair layout rule check data. Calculating from the layout data, and calculating the inter-element distance of the pair;
It is determined whether the calculated inter-element distance of the pair is larger than a rule value defined in a pair arrangement rule stored in advance, and when the inter-element distance is larger than the rule value,
Storing the names of the elements constituting the pair, and the inter-element distances as violations of the inter-element distance rules; and retrieving the same directionality of the elements constituting the pair from a previously stored pair arrangement rule, The rotation parameters of the constituent elements are searched from the layout data, and the rotation parameters are compared based on the pair arrangement rule. If the directions of the pairs are not considered to be the same, the names of the elements forming the pairs as the directionality violation, In addition, a program for executing a step of storing rotation parameters of the element and a step of displaying the stored pair of the element distance violation and the direction identity violation on the display means is recorded.

As described above, the check violation of the pair arrangement rule is automatically detected and displayed on the display means.
Pair arrangement rule checks can be performed without fail, and the yield and reliability of semiconductor devices provided with analog circuits can be improved.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic explanatory view of a design tool system according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b).
FIG. 3 is an explanatory diagram of a pair arrangement rule which is rule information used for element arrangement check according to one embodiment of the present invention. FIG. 3 is a flowchart of element arrangement check according to one embodiment of the present invention. 5B are explanatory diagrams of a check mode for changing a range to be checked in the element arrangement check, and FIGS. 5A to 5C are diagrams of element distances in a pair arrangement rule according to an embodiment of the present invention. FIG. 6 is an explanatory diagram showing a definition example, FIG. 6 is an explanatory diagram showing an example of display in a pair in which an element distance violation has occurred, and FIG. 7 is an explanatory diagram showing an example of display in a pair in which a direction identity violation has occurred. FIG. 8 is an explanatory view showing another example of the display of the pair in which the element distance violation or the direction identity violation has occurred, and FIG. 9 is a table of an error list in the pair in which the violation has occurred in the pair placement rule check. It is an example.

In this embodiment, the design tool system 1 is a design kit for an analog / digital semiconductor integrated circuit device, and includes a circuit editor, a simulator, a layout editor, an automatic wiring tool, and a layout verification tool as editing tools.

This design tool system 1 has the configuration shown in FIG.
As shown in (1), an electronic system PC is provided which performs all design work such as editor work and check work. A checker unit 2 is provided in the electronic system PC. Here, the checker unit 2 is provided in the electronic system PC, but a checker unit PC may be provided separately from the electronic system PC, and the electronic system PC and the checker unit PC may be connected by a connection cable.

One of the checker functions in the checker section 2 is a pair designation tool and a pair designation element arrangement checker. The term “pair” refers to a pair of elements for which specific accuracy is a problem during circuit design. The “pair designation” refers to the permissible element variation accuracy (specific accuracy) of a differential circuit or a current mirror circuit, which is a basic element of an analog circuit. Is to be specified.

The checker unit 2 comprises a circuit data storage unit 3, a pair information storage unit 4, a pair arrangement rule storage unit 5, a layout storage unit 6, a data storage unit 7, and a pair arrangement checker control unit 8.

All operations such as a check operation in the checker unit 2 are performed based on a program stored in a storage device (storage medium) such as a hard disk provided in the electronic system PC.

The circuit data storage unit 3 stores circuit diagram data, and the pair information storage unit 4 stores pair information. The pair arrangement rule storage unit 5 stores a pair arrangement rule, and the layout storage unit 6 stores layout data. The data storage unit 7 stores various data such as a calculation result of the pair arrangement checker control unit 8. Pair placement rule check data is composed of the circuit diagram data, the pair information, the layout data, and the pair placement rule.

The circuit diagram data is, for example, circuit diagram information created by CAD or the like, and the pair information is information on an element designated as a pair. The pair arrangement rule is rule information for arranging elements when a block including an element whose pair is specified is laid out.

This pair arrangement rule is shown in FIG.
As shown in (b), there is an inter-element distance and a direction identity. In the case of the distance between elements, in the element specified as a pair,
This is a rule of arranging a device within a certain distance from a partner device to be paired. By arranging the pair-designated elements close to each other, it is possible to equalize the effects of heat and noise that the elements receive from the surroundings.

The directional identity is a rule that a pair-designated element is arranged in the same direction as a paired element. In this case, the same direction indicates that the rotation states of the elements are the same. If the directions of the elements are different, variations in the element size may occur.

Further, the layout data is layout pattern information designed for layout in various elements such as transistors and resistors, and includes, for example, element names, element types, arrangement coordinates, and parameters (hereinafter, referred to as rotation parameters) representing rotation conditions. Rotation parameter).

The pair placement checker control unit 8 checks the stored circuit diagram data for the placement of the specified element based on the pair information, the pair placement rule, and the layout data.

Next, a method for checking the arrangement of pair-designated elements according to the present embodiment will be described with reference to the flowcharts of FIGS.

First, the user inputs the pair information input by the pair designation program to the pair information storage unit 4 via the external storage device. At the same time, the circuit diagram data is also stored in the circuit data storage 3. The pair placement checker control unit 8 detects elements from the input pair information and circuit diagram data to generate pairs, and creates a list of the pairs (step S10).
1).

Here, in the layout design, the hierarchical structure of the pair may be different between the circuit design and the layout design. In this case, the non-hierarchical expansion in the block hierarchical structure stored in the circuit diagram data is performed. Data conversion is performed using the mode and the hierarchical development mode, and a pair is generated according to the hierarchy in the layout design.

In the non-hierarchical expansion mode, as shown in FIG. 4A, a layer pair in an execution block is targeted. In the hierarchical expansion mode, as shown in FIG.
Pairs in lower blocks are also targeted.

Further, the user stores the pair arrangement rule and the layout data in the pair arrangement rule storage unit 5 and the layout storage unit 6 via the external storage device (steps S102 and S103).

The pair placement checker controller 8 determines in step S
One pair is extracted from the list of pair information created in the process of step 101 (step S104), the arrangement coordinates of the two elements constituting the extracted pair are obtained from the layout data, and the inter-element distance is calculated (step S104). Step S105).

Then, the pair placement checker control unit 8 determines whether or not the inter-element distance calculated based on the pair placement rules stored in the pair placement rule storage unit 5 is larger than the rule value (step S106). .

Here, the definition of the distance between the elements is shown in FIGS.
It is shown in (c). As shown in FIG. 5A, the distance between the elements is “0” when the elements of the pair are arranged adjacent to each other left and right or vertically.

When the elements of the pair are arranged on the left and right, as shown in FIG. 5B, the lower left corner of the element arranged on the left side and the lower right corner of the element arranged on the right side And the distance.

When the elements of the pair are arranged vertically, as shown in FIG. 5 (c), the lower right corner of the element arranged above and the element arranged below the element are arranged. It is the distance to the lower right corner.

If it is determined in step S106 that the inter-element distance is within the rule value, the process proceeds to step S1.
In step 08, when it is determined that the inter-element distance is larger than the rule value, the pair placement checker control unit 8 outputs the inter-element distance rule violation data including the names of the elements forming the pair and the inter-element distance. It is stored in the data storage unit 7 as an element distance rule violation (step S107).

Then, the pair arrangement checker control unit 8 searches the pair arrangement rules stored in the pair arrangement rule storage unit 5 for the same directionality of the pair extracted in the processing of step S104 (step S108), and forms the pair. A rotation parameter of the element to be searched is searched from the layout data (step S109).

The pair arrangement checker controller 8 compares the rotation parameters based on the pair arrangement rule (step S1).
10) It is determined whether the directions are considered to be the same (step S111).

If the directions are the same, step S11
If the direction is not the same, the pair placement checker control unit 8 stores the name of the element forming the pair as the same-direction violation and the direction-identity violation data including the rotation parameter of the element in the data storage unit. 7 (step S112).

Then, for all pairs, step S
It is determined whether or not the processing of steps S104 to S112 has been performed. If the processing has not been performed, the processing of steps S104 to S112 is repeated, and a check is performed for all pairs (step S113).

In the process of step S113, when the processes of steps S104 to S112 are performed on all pairs, the data of the element distance violation and the direction identity violation stored in the data storage unit 7 are respectively stored. The data is transferred and stored in an external storage device or the like (step S114), and the violation data is displayed on a display (step S115).

Here, a display example of the violation data displayed on the display will be described.

For example, in the check result display of the element distance violation, as shown in FIG. 6, on the layout editor, the elements of the pair in which the error occurred are connected by a V-shaped solid line (violation display line) and the like. The measured distance and the rule value are displayed beside.

In the case of a check display result of a direction identity violation, as shown in FIG. 7, similarly, the elements of the pair having an error are connected by a V-shaped solid line or the like, and besides the symmetry, Displays the rotation status.

Further, as shown in FIG. 8, by displaying a pair of elements that violate the distance between elements or violate the direction identity by highlighting or blinking, and selecting the blinking displayed element, An error list as shown in FIG. 9 may be displayed on the display.

Thus, according to the present embodiment, a check violation of the pair arrangement rule is automatically detected, and the result is displayed on the display means, so that the pair arrangement rule check can be performed without fail.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, a check violation of the pair arrangement rule is automatically detected and displayed on the display means, so that the pair arrangement rule check can be performed without fail.

(2) In the present invention, according to the above (1), the yield of semiconductor devices can be improved and the stable circuit operation can be realized by greatly reducing the characteristic failure in the analog circuit.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory diagram of a design tool system according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram showing a pair arrangement rule of an inter-element distance, which is rule information used for element arrangement check according to an embodiment of the present invention, and FIG. FIG. 8 is an explanatory diagram showing a gender pair arrangement rule.

FIG. 3 is a flowchart of an element arrangement check according to an embodiment of the present invention.

FIGS. 4A and 4B are explanatory diagrams of a check mode for changing a range to be checked in an element arrangement check.

FIGS. 5A to 5C are explanatory diagrams showing an example of a definition of a distance between elements in a pair arrangement rule according to an embodiment of the present invention.

FIG. 6 is an explanatory diagram showing an example of display in a pair in which an element distance violation has occurred.

FIG. 7 is an explanatory diagram showing an example of display in a pair in which a direction identity violation has occurred.

FIG. 8 is an explanatory diagram showing another example of display in a pair in which an element distance violation or a direction identity violation has occurred.

FIG. 9 is a display example of an error list of a pair violated in a pair arrangement rule check.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Design tool system 2 Checker part 3 Circuit data storage part 4 Pair information storage part 5 Pair arrangement rule storage part 6 Layout storage part 7 Data storage part 8 Pair arrangement checker control part PC Electronic system

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masanori Fukuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. F-term (reference) in Hitachi Super-LSI Systems, Inc. 5B046 AA08 BA05 CA04 GA01 HA06 HA09 JA03 5F064 BB21 DD12 DD24 DD50 HH08 HH10 HH12 HH13 HH14

Claims (5)

[Claims] A step of storing pair arrangement rule check data including circuit diagram data, pair information, layout data, and a pair arrangement rule; generating a pair from the pair arrangement rule check data; Calculating the distance; determining whether the calculated inter-element distance of the pair is greater than a prescribed rule value; and, if the inter-element distance is greater than the rule value, the element of the pair. Storing the inter-rule rule violation data in a data storage unit; detecting the same directionality in the pair, and the rotation parameter of an element constituting the pair; comparing the detected rotation parameter, Determining whether or not the pair is considered to be the same; and, if the directions are not the same, storing the directionality violation data of the pair in a data storage unit. And a step of displaying a pair, which is stored in the data storage unit and which violates the distance between elements and violates the direction identity, as a violating pair on a display unit. 2. The pair placement rule checking method according to claim 1, wherein the inter-element distance rule violation data includes a name of an element forming the pair and an inter-element distance, and the same directionality violation data includes: A method of checking a pair arrangement rule, wherein the method is a name of an element forming a pair and a rotation parameter of the element. 3. The pair placement rule check method according to claim 1, wherein the elements of the violating pair are displayed by highlighting, blinking, or instructing by a violation display line. Method for checking. 4. The pair arrangement rule checking method according to claim 3, wherein when the displayed pair violates the inter-element distance, an actually measured distance and a rule value are displayed near the pair, and the displayed value is displayed. A pair arrangement rule check method, wherein when a pair violates a direction identity, a symmetry and a rotation state are displayed near the pair. 5. A pair is generated from pair information and circuit diagram data stored in advance, and arrangement coordinates of elements constituting the pair are obtained from layout data stored in advance.
Calculating the inter-element distance of the pair; and determining whether the calculated inter-element distance of the pair is greater than a rule value defined in a previously stored pair arrangement rule. When the value is larger than the rule value, a step of storing the names of the elements constituting the pair and the distance between the elements as a violation of the element distance rule, and a pair in which the same directionality of the elements constituting the pair is stored in advance. Searching from the layout data for the rotation parameters of the elements constituting the pair, comparing the rotation parameters based on the pair allocation rule, and determining the direction if the directions of the pairs are not considered to be the same. The process of storing the names of the elements forming a pair and the rotation parameters of the elements as a gender identity violation, and the stored element distance violation and the direction identity violation are stored. A program for executing a step of displaying a pair.