JP2001175455A - Vector normalization arithmetic unit, vector normalization arithmetic method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a vector normalization arithmetic unit capable of performing a high speed arithmetic operation with a simple configuration. SOLUTION: The vector normalization arithmetic unit 30 is provided with a divider 32 for dividing each component of a vector applied in a floating decimal point type into a code part, exponent part, and mantissa part, an adder 33 for adding spore bits to the most significant bit of the mantissa part, a memory 36 for storing the normalization arithmetic result of the vector, whose component is respectively provided with a preliminarily decided prescribed value, a comparator 34 for comparing the size of the exponent part of each component, an address decoder 35 for shifting the decimal point position of the exponent part, so that the value of the exponent of each component of the vector can be made the same, based on the compared result of the size of the exponent part, and for generating an address on the memory, in which the normalization arithmetic result of the vector corresponding to the value defined with the bits of the exponent part, and a code matching circuit 37 for conducting code matching with the arithmetic result read from the memory by referring to the code part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector normalization operation technique, and more particularly, to an improved technique for realizing high-speed normalization operation processing with a simple configuration.

[0002]

2. Description of the Related Art In the field of computer graphics, there is a case where it is desired to display a constant thickness regardless of the position of a virtual viewpoint, such as a hair or a wire net. A technique using a line polygon to display such an object is known. In this technique, for example, as shown in FIG. 7, two vertices V _P defined in the screen coordinate _system, based on the X and Y components of V _Q, predetermined line width wi
The other four vertices V _{0 to} V ₃ are obtained so as to satisfy dth,
An image is displayed by performing texture mapping or the like on the polygon defined by the four vertices. That is, when a line polygon is used, the visual field conversion from the world coordinate system to the screen coordinate system is performed at two vertices, and then the other four vertices are determined so that the line polygon has a constant thickness.

[0003] The reason for employing such a method is that if the coordinates of the four vertices constituting the line polygon are determined in advance and field-of-view conversion or the like is performed, then each of the four vertices is determined according to the distance between the line polygon and the virtual viewpoint. This is to eliminate the inconvenience that the thickness of the line polygon is not constant because the coordinates of are determined. For example, when the distance between the virtual viewpoint and the line polygon is short, the line polygon becomes thicker than necessary. On the other hand, when the distance between the virtual viewpoint and the line polygon is long, the line polygon becomes thinner than necessary. In some cases, the line disappears. Therefore, such a problem can be solved by adopting the above method.

[0004] In this case, the coordinates of the vertex _{V P (X P,}
Y _P), coordinates _(X Q of vertices _{V Q,} and _{Y Q), a = X P} -X Q ... (1) b = Y P -Y Q ... case of the (2), X of the vertex _{V 0} Component X ₀ and Y component Y ₀ are
It can be described by the following equation. X ₀ = X _Q −a (a ² + b ² ) ⁻¹ / 2 × width / 2 (3) Y ₀ = Y _Q + b (a ² + b ² ) ⁻¹ / 2 × width / 2 (4) , The vertex V _P with respect to the line segment defined by the vertices V _P and V _Q
0, the line segment is defined by a line segment defined by V ₁ and vertex V _2, V ₃ are intended to be orthogonal to each another. The X component and the Y component of the vertices V _{1 to} V ₃ can be similarly obtained.

At this time, a (a ² + b ² ) in the equation (3)
^{The operation for obtaining −1/2} and b (a ² + b ² ) ^−1/2 in the expression (4) can be regarded as the normalization operation of the vector (a, b). Hereinafter, in this specification, a (a ² +
^Obtaining the value of (b ² ) ^{−１ ／ and} the value of b (a ² + b ² ) − ^{と い う} is referred to as a normalization operation of the vector (a, b). In order to perform such a vector normalization operation by hardware, for example, as shown in FIG. 8, a circuit configuration including a multiplier 41, an adder 42, a square root operation unit 43, and a divider 44 is required. In the figure, a multiplier 41 inputs a and b, calculates a ² and b ² ,
2 calculates a ² + b ² based on this calculation result. Next, the square root reciprocal calculator 43 calculates (a ² + b ² )
After calculating the ^-1/2, in a multiplier 44 ^{a (a} 2 +
b ² ) ^{Perform − −} .

[0006]

However, in the above configuration, even if the speed of the hardware is increased, the processing time in the square root reciprocal calculator 43, the multipliers 41 and 44 and the adder 42 becomes enormous. There was a problem. In particular, in order to display line polygons, modeling conversion to the world coordinate system, visual field conversion to a virtual viewpoint, three-dimensional clipping processing, hidden line processing, texture mapping processing, shading processing, display priority processing, etc. Since the conversion operation must be performed within the image update period (for example, 1/60 second), it is necessary to perform the vector normalization operation at a higher speed in order to improve the image quality.

In the case of image processing, similar processing is often performed on a series of data. Therefore, processing units are arranged in series and the processing load on each processing unit is made uniform by processing. In some cases (pipeline processing). However, since the entire processing time is enormous, there is a problem that the number of stages in the pipeline becomes very large, which leads to an increase in cost.

Therefore, the present invention provides a normalization operation unit, a normalization operation method, and a recording medium on which a program for causing a computer to execute the method is provided, which realizes a vector normalization operation at high speed with a simple configuration. The task is to

[0009]

In order to solve the above-mentioned problems, a vector normalizing operation unit of the present invention divides each component of a vector given in a floating-point type into a sign part, an exponent part, and a mantissa part. A divider, an adder for adding a stitch bit to the most significant bit of the mantissa, a memory for storing a normalization operation result of a vector having a predetermined value in each component, and an exponent of each component A comparator for comparing the sizes of
Based on the comparison result of the exponent part, the decimal point position of the mantissa is shifted so that the exponent value of each component of the vector becomes the same, and the normalization of the vector corresponding to the value defined by the bits of the mantissa is performed. An address decoder that generates an address on the memory in which a result of the conversion operation is stored; and a code matching circuit that performs code matching on the operation result read from the memory with reference to the code unit. ing.

According to this configuration, the processing in each hardware is a series of simple processings such as addition and subtraction, comparison, bit shift, and memory reading, so that the circuit configuration is simplified and high-speed operation is possible.

However, in the above configuration, the function of each hardware can be realized by a plurality of hardware of a lower concept, and the plurality of hardware is realized by one hardware of a higher concept. You can also.

In the vector normalization operation method of the present invention, each component of a vector given in a floating-point type is divided into a sign part, an exponent part and a mantissa part, and a stitch bit is added to the most significant bit of the mantissa part. Shift the decimal point of the mantissa so that the exponent values of the components are the same, extract the bits of the mantissa, and store the result of the normalization operation of the vector having a predetermined value in each component. The normalization result of the vector corresponding to the value defined by the bits of the mantissa is read from the memory, and the sign is matched to the calculation result with reference to the sign unit, thereby normalizing the vector.

Further, according to the present invention, it is possible to provide a computer-readable recording medium in which a program for executing the above procedure is recorded. Here, the recording medium is a medium on which an image processing program or the like is recorded by some physical means, and is a computer, particularly,
It refers to hardware capable of achieving desired functions in dedicated hardware (eg, a geometalizer, a rendering processor) and the like. Therefore, any device may be used as long as it is downloaded to the computer by some means and a desired function is realized. For example, ROM, flexible disk, hard disk, CD-ROM, CD-R, DVD-RO
M, DVD-RAM, DVD-R, PD disk, MD
Includes information recording media such as disks and MO disks. This includes the case where data is transferred from the host computer via a wired or wireless communication line (public line, data line, satellite line, etc.). The so-called Internet is also included in the recording medium mentioned here.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, a game device 10 includes a CPU 1
1, system memory 12, bus arbiter 13, geometallizer 14, coordinate operation circuit 15, data selector 16,
Rendering processor 17, frame buffer 18,
A pad interface (pad I / F) 19 and a CD interface (CD I / F) 20 are provided.

The CD-ROM 22 stores a game program and a drawing library for displaying images of objects and the like. The drawing library stores coordinate data (shape data) of various objects.

The CPU 11 reads necessary data from the CD-ROM 22 in response to an input signal from a player input from the control pad 21 via the pad I / F 19, and executes desired arithmetic processing. Further, the coordinate data of the object necessary for drawing is read from the CD-ROM 22 and supplied to the geometalizer 14.

The system memory 12 mainly stores program data for the operating system and the above-mentioned game program, and also functions as a work area for storing static variables, dynamic variables, etc., writes various commands to the geometalizer 14, and performs conversion matrix calculation. The matrix writing at the time is performed by the CPU 11.

The bus arbiter 13 is configured to control the transmission and reception of data by allocating a bus occupation time to each device connected to each other via the bus. The geometalizer 14 is connected to the CPU 11 via the bus arbiter 13.
Is converted to a screen coordinate system viewed from a virtual viewpoint based on a conversion matrix.

The coordinate data of each object is supplied to a rendering processor 17 via a data selector 16. The input A of the data selector 16 receives the data of the four vertices of a normal polygon, and the input B of the data selector 16
The four-vertex data of the line polygon converted from two vertices to four vertices by 5 is input. A selection signal for controlling the operation of the data selector 16 is supplied to the S input. This selection signal includes identification information of a normal polygon and a line polygon. The data selector 16 is composed of a multiplexer, receives a selection signal supplied to the S input, selects four vertex data supplied to the A input if it is a normal polygon, and transfers it to the rendering processor 17. If it is a line polygon, the four vertex data supplied to the B input is selected and transferred to the rendering processor 17.

The rendering processor 17 performs a texture mapping process, a display priority process, a shading process, and the like based on virtual viewpoint position data, light source position data, texture designation data, texture density data, polygon coordinate data, and the like. Is written to the frame buffer 18. Then, the pixel data is read from the frame buffer 18 in synchronization with the image update period, and the pixel data is transferred to the monitor 23. The monitor 23 performs D / A conversion of pixel data, video signal generation processing, and the like, and displays an image of an object or the like.

The above-mentioned CD-ROM 2 as a recording medium
Reference numeral 2 may be other storage means, for example, a hard disk, a cartridge type ROM, a DVD-ROM, an MO, a floppy disk, or the like, or a communication medium such as the Internet or various personal computer communication networks.

Next, the circuit configuration of the coordinate calculation circuit 15 will be described with reference to FIG. The coordinate operation circuit 15 is a circuit that generates four vertex data constituting a line polygon from two vertex data, and includes a subtractor 31, a normalization operation unit 30, a multiplier 38, and an addition / subtraction unit 39. The normalization calculator 30 is a circuit for performing a vector normalization calculation, and includes a divider 32, an adder 33, a comparator 34, an address decoder 35, a ROM 36, and a sign matching circuit 37.

The two vertex data (vertex V) shown in FIG._P, V_Q
Vertex data) to form a line polygon
Data (vertex V₀~ V₃Vertex data)
As an example, the configuration of the coordinate calculation circuit 15 will be described.
Vertex V in subtractor 31_P, V_QIs input.
Then, the subtractor 31 calculates each of the values based on the equations (1) and (2).
Calculate the difference between the X and Y components of the vertex to calculate a and b
Put out. Suppose vertex V _PCoordinate of (6,2), vertex V_Q
Is (2,4), the values of a and b are as follows:
become. a = 6−2 = 4 b = 2−4 = −2 The X component and Y component of each vertex and the data of the above a and b are shown in FIG.
32-bit floating point format as shown in
have. In the figure, the floating point format
Is divided into sign part (s), exponent part (e) and mantissa part (m)
1 bit, 8 bits, 23 bits
Is assigned. X is raised to the Yth power as X ^ Y
Data in the above format
Generally, it can be described as follows. (-1) ^ s × 2 ^ (e-127₍₁₀₎) × 1. m where: ‘1 'in m is‘ kechi in mantissa
Bit '. Stitch bit was omitted
Most significant bit ‘1’. Generally, best after decimal point
The representation of the mantissa is normalized so that the significant digit of the place comes.
1 is always small in this normalized real number.
Comes after a few points. Therefore, in a normalized real number,
So that 1 appears immediately before the decimal point, and
Can be represented by a mantissa. Do this
And the first bit of the mantissa is always 1 unless the numerical value is 0.
You. Therefore, the mantissa part in the above decimal format
m is the original 2 bits, omitting the first bit, which is always 1.
The eye value is placed at the first bit of the actual bit string.
In the present embodiment, as will be described later,
Add a stitch bit to the mantissa to perform the shift operation
Perform the operation.

The subscript (10) indicates that the number is 10
This indicates that the number is in a hexadecimal notation. Also, the 8-bit exponent can represent 256 different values, but -12
In the case of so-called clogging expression in which 8 is added or subtracted, the range of expressible numerical values is from -128 to +127.

The divider 32 converts each of the above a and b into
Divided into a sign part, an exponent part, and a mantissa part; sign part of s and b b. s is transferred to the sign matching circuit 37.
Similarly, the exponent part of a. exponent part of e and b b. e to the comparator 34 and the mantissa part a. mantissa part of m and b b.
m is transferred to the adder 33. At this time, a. When s and the like are expressed in binary numbers, they are as follows. a. s = 0 b. s = 1 a. e = 1000 0001 b. e = 1000 0000 a. m = 000 0000 0000 0000 0000 0000 0000 b. m = 000 0000 0000 0000 0000 0000 However, a. m and b. Since “m” is the notation of the mantissa in a state where the bit is dropped, “1” is added to the most significant bit in the adder 33. As a result, a. m and b. m is given by the following equation. a. m = 1000 0000 0000 0000 0000 0000 b. m = 1000 0000 0000 0000 0000 0000 Comparator 34 has a. e and b. Compare the value of e and find a and b
Is supplied to the address decoder 35 (comparison information) indicating which digit is larger (or smaller) by which digit. In the above example, a. The value of e is 129 in decimal notation, b. Since the value of e is 128 in decimal notation, it can be seen that a is larger by one digit.

The address decoder 35 shifts the decimal point position of the mantissa part of a or b based on the comparison information. For example, if a is larger by N digits, b. Each bit of m is shifted N bits to the right by the cyst register, and '0' is inserted into the upper N bits. On the other hand, a. e and b. If the values of e are the same, a. m and b. The shift operation of each bit included in m is not performed. In the above example, a
Is larger by one digit, b. Each bit of m is shifted one bit to the right by a cyst register, and '0' is inserted in the most significant bit. As a result, a. m and b. m is as follows. a. m = 1000 0000 0000 0000 0000 0000 b. m = 0100 0000 0000 0000 0000 0000 where a. m and b. The upper 4 bits of m are extracted and expressed in decimal notation as follows. a. m = 8 b. m = 4 As shown in FIG. 4, in the ROM 36, the normalization operation result of the vector (x, y) having x and y as components, which can take integer values of 0 to 15, that is, x (x ² + y ² ) ^-1/2 value (n
ml x) and y (x ² + y ² ) ^−1/2 value (nml
y) is registered in advance. The reason why the values of x and y are set in the above range is that the range of values defined by a 4-bit binary number is 1
This is because it corresponds to a range of 0 to 15 in a 0-base number. x and y
FIG. 5 shows an address table of the ROM 36 corresponding to each value of FIG.
Shown in As shown in the figure, when x = i, y = j, n
ml The address where the operation result of x is stored can be represented by the following expression. 16 × i + j (5) From equation (5), nml when x = 8 and y = 4 The address of x is 132. From the above, the address to be obtained on the ROM 36 is a. m and b. It is uniquely defined by the combination of the upper 4 bits of each mantissa of m. The address decoder 35 includes: a. m and b. The address on the ROM 36 is obtained from the value of m, and this is output to the ROM 36. Then, from the ROM 36, nml x and nml The value of y is read.

Incidentally, nml when x = i, y = j The value of y is nml when x = j and y = i in the table shown in FIG. equal to the value of x. Therefore, x = i, y
= Nml when j The address of y can be obtained by exchanging the values of i and j in equation (5).
From the above, nml x value and nml The value of y is as follows. nml x = 0.89 nml y = 0.45 The code matching circuit 37 is supplied from the divider 32 with a. s
And b. Based on the value of s, nml x value and nml
Sign matching is performed on the value of y, and n a and n b
Generate n a and n b can be represented by the following equation. n a = {(-1) ^ a. s｝ × nml x ... (6) n b = {(-1) ^ b. s｝ × nml y (7) In the above example, a. s = 0, b. Since s = 1, n
a and n The value of b is as follows. n a = {(-1) ^ 0} × 0.89 = 0.89 n b = {(− 1) ^ 1} × 0.45 = −0.45 a and n The value of b is multiplied by の of the width width of the line polygon to obtain w a and w Obtain b. w a = n a × width / 2 (8) w b = n b × width / 2 (9) When the line width is 1, w a and w The value of b is as follows. w a = 0.89 × 1/2 = 0.45 w b = -0.45 × 1/2 = -0.23 adder-subtracter 39 is above value and 2 vertex data (vertex _V P, V
_Q vertex data) is added and subtracted to generate four vertex data (vertex data of vertices V _{0 to} V ₃ ) constituting the line polygon. For example, X component X ₀ and Y component Y of vertex V _0
0 can be described by the following equation. _{X 0} = X Q -w _{a ... (10) Y 0 =} Y Q + w b (11) In the above example, the values of X ₀ and Y ₀ are as follows. X ₀ = 2−0.45 = 1.55 Y ₀ = 4 + (− 0.23) = 3.77 Equation (10) corresponds to equation (3), and equation (11) corresponds to equation (4). I do. The X component and the Y component of the vertices V _{1 to} V ₃ can be similarly obtained. (Modification) The arithmetic processing in the coordinate arithmetic circuit 15 can be realized by software other than the above hardware. FIG. 6 shows a flowchart in this case. Each procedure shown in the figure may be configured to be performed by the geometalizer 14 or the rendering processor 17, or may be configured to be performed by the CPU 11.

Firstly, two vertices _V P supplied from geometalizer 14, the vertex data of _{V Q,} (1) and equation (2) a, a b obtained based on equation (step S1).
Then, a and b defined in the floating-point format as shown in FIG. 3 are decomposed into a sign part, an exponent part, and a mantissa, and a bit “1” is added to the most significant bit of the mantissa (step S2). ).

The exponents of a and b are compared, and each bit of one of the mantissas is shifted right by the difference in the number of digits between them (step S3). For example, when a is larger by N digits, each bit of the mantissa part of b is shifted N bits to the right, and '0' is inserted into the vacated upper N bits. On the other hand, if the exponent part of a and the exponent part of b are the same size, the shift operation of each bit included in the mantissa is not performed.

Upper 4 bits of each of the mantissa parts of a and b
Extract x and y. As shown in FIG. 4, x (x²+ Y
²)^-1/2Value (nml x) and y (x²+ Y²)
^{−1 / 2}Value (nml On the ROM where y) is stored
Is generated with reference to equation (5) (step S5).
4). Nml corresponding to the address x value and nml
The value of y is read from the ROM (step S5).

Based on equations (6) and (7), a and b
With reference to the sign of x value and nml add a sign to the value of y and n a and n b is generated (step S6). In correspondence with the line width width of the line polygon, w is determined by referring to the equations (8) and (9). a and w b
Is generated (step S7).

Two vertices V_P, V_QX component of the vertex data of
W for each of the Y components a and w b is added or subtracted, and 4
Vertex V₀~ V₃Is generated (step S
8). For example, vertex V₀X component of₀And Y component Y
₀Is determined by the equations (10) and (11). More than
By processing step, line polygon from 2 vertex data
Is generated.

As described above, according to the present embodiment,
, The values of the exponents of a and b are aligned, and a. m and b.
nm defined by the upper 4 bits of each mantissa of m
l x and nml Register the value of y in ROM 36 beforehand.
Complex complex calculations can be realized at high speed with a simple configuration
can do. In addition, processing in each hardware
Means addition, subtraction, comparison, bit shift, memory read, etc.
Because it is a series of simple processing, if the circuit configuration becomes simple
In both cases, high-speed operation becomes possible.

In the above example, a. m and b. Although the upper 4 bits are extracted from each of m, when extracting the upper N bits, the normalization operation result of a vector having x and y components each having an integer value of 0 or more and 2 ^N -1 or less is stored in the ROM 36. What is necessary is just to memorize beforehand. According to such a configuration, the storage capacity of the memory can be remarkably reduced as compared with the case where the normalization operation result of a vector having a real value in each component is stored in advance. Further, the above configuration is suitable for a vector normalization operation that does not require precision.

In the above description, the case where the two-dimensional vector (a, b) is normalized has been described as an example. However, the present invention is directed to the normalization of the N-dimensional vector (a ₁ , a ₂ ,..., A _N ). It can also be applied to arithmetic. In addition, the vector normalization operation unit and the vector normalization operation method according to the present invention can be applied to a method of obtaining each vertex data of a line polygon, and a method of shading a surface of an object. The present invention can also be applied to obtaining a cosine value of an angle formed by a normal vector.

The present invention can be applied not only to game devices but also to various image processing devices requiring computer graphics processing, such as virtual reality systems and various simulators.

[0038]

According to the present invention, it is possible to provide a vector normalization calculator and a vector normalization calculation method capable of performing a vector normalization calculation at a high speed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a game device.

FIG. 2 is a circuit configuration diagram of a coordinate calculation circuit.

FIG. 3 is an explanatory diagram of a floating-point format.

FIG. 4 is a table in which a normalization operation result having an integer value as a vector component is registered.

FIG. 5 is a correspondence table between x and y values and addresses.

FIG. 6 is a flowchart of a vector normalization calculation method.

FIG. 7 is an explanatory diagram of a line polygon.

FIG. 8 is a circuit configuration diagram of a conventional vector normalization arithmetic unit.

[Explanation of symbols]

14 ... geometallizer, 15 ... coordinate operation circuit, 16 ... data selector, 17 ... rendering processor, 30 ...
Vector normalization calculator, 31 ... subtractor, 32 ... comparator,
33 ... address decoder, 34 ... ROM, 35 ... sign matching circuit, 36 ... multiplier, 37 ... adder / subtractor

Claims (6)

[Claims] A divider that divides each component of a vector given as a floating-point type into a sign part, an exponent part, and a mantissa part;
An adder that adds a sting bit to the most significant bit of the mantissa, a memory that stores a normalization operation result of a vector having a predetermined value in each component, and a size of an exponent part of each component. Based on the comparison result of the comparator and the magnitude of the exponent part, the decimal point position of the mantissa is shifted so that the exponent value of each component of the vector becomes the same, and the value defined by the mantissa bits An address decoder for generating an address on the memory in which a result of normalization operation of a vector corresponding to the vector is stored, and sign matching is performed on the operation result read from the memory with reference to the encoding unit. A vector normalization arithmetic unit including a sign matching circuit. 2. The bits of the mantissa are upper N bits of the mantissa when expressed in a binary number, and the predetermined value is 0.
2. The vector normalization arithmetic unit according to claim 1, wherein the vector normalization arithmetic unit has an integer value of 2 ^N -1 or less. 3. An image processing apparatus comprising the vector normalization arithmetic unit according to claim 1. 4. Each component of a vector given as a floating-point type is divided into a sign part, an exponent part, and a mantissa part, and a bit is added to the most significant bit of the mantissa so that the exponent value of each component is the same. The mantissa part bit is extracted after shifting the decimal point position of the mantissa part so that the mantissa part bit is extracted from a memory that stores a normalization operation result of a vector having a predetermined value in each component. A vector normalization operation method for reading a normalization operation result of a vector corresponding to a defined value and normalizing the vector by referring to the sign unit and performing sign matching on the operation result. 5. The mantissa bit is the upper N bits of the mantissa when expressed in binary, and the predetermined value is 0.
The vector normalization operation method according to claim 4, wherein each of the integer values is not less than ^2N- 1 and not more than ^2N- 1. 6. A computer-readable recording medium on which a program for causing a computer to execute the vector normalization operation method according to claim 4 or 5 is recorded.