JP2001174527A - Device and method for diagnosing trouble with logical circuit, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately predict a trouble with a given logic circuit. SOLUTION: Using a status transition diagram obtained by regarding a given logic circuit as a status transition machine, a test pattern generator 4 generates a test pattern for diagnosing resistor level trouble for testing all transitions from a status to a status. Using the test pattern generated by the test pattern generator 4, a resistor level trouble diagnosing device 5 performs the trouble diagnosis of a resistor level so as to generate the information for performing a gate level trouble diagnosis. Using this information, the gate level trouble diagnosing device 6 performs the gate level trouble diagnosis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit failure diagnosis device, a logic circuit failure diagnosis method, and a recording medium on which a logic circuit failure diagnosis program is recorded, and more particularly to a diagnosis device, a diagnosis method, and a diagnosis program for diagnosing a logic circuit failure. The present invention relates to a recording medium on which is recorded.

[0002]

2. Description of the Related Art A conventional invention of this kind is disclosed in Japanese Patent Laid-Open Publication No.
No. 005. In the test pattern generation method described in the publication, as shown in FIG. 15, first, in step 10, a state transition from an initial state of a state transition to an erroneous destination state is performed using a state transition description. Is connected to a sequence for distinguishing between a normal transition state and an incorrect transition destination state, and a pattern sequence for detecting a specific transition fault is generated. Next, in step 20, an extended pattern sequence for detecting another transition fault while keeping the value output from the storage element unit to the combinational circuit unit fixed for each pattern corresponding to each state transitioned by the pattern sequence is generated. I do. Then, in step 30, the pattern is synchronized with the clock, sequentially applied to the combinational circuit section as an external input, the clock is applied, the external output is observed, and then the extended patterns are added one after another while the clock is fixed, and the external output is applied. Observe. By generating test patterns as described above, the fault detection rate is increased,
This is to speed up the test pattern generation processing and shorten the test time.

A conventional technique described in Japanese Patent Application Laid-Open No. H8-15388 will be described with reference to FIG. In the figure, first, in a process 102, a logic simulation is performed on an input sequence created by an LSI designer for logic verification, and a history of the circuit state of the circuit under test is stored.

Next, in step 103, a state transition graph is generated from the result of the logic simulation executed in step 102, that is, the relationship between the input sequence and the history of the circuit state of the circuit under test. Further, in the process 109, it is determined whether or not the state of the time frame at the current time exists in the state transition graph. Then, in process 110, a path from the initial state of the state transition graph to the circuit state of the time frame at the current time is obtained, and the sum of the input series in the path is obtained to the state. Generate a sum of sequences as a state initialization sequence.

By generating test sequences in this way, a test sequence method for a combinational circuit that can obtain a short test sequence at high speed can be realized.

[0006]

In each of the prior arts described above, a failure simulation is performed to determine whether or not a failure exists. Therefore, there is a disadvantage that the target of the failure diagnosis is limited to the failure in which the simulation is performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a logic circuit fault diagnosis apparatus and a logic circuit whose fault diagnosis is not limited to faults obtained by simulation. It is an object of the present invention to provide a recording medium storing a circuit failure diagnosis method and a logic circuit failure diagnosis program.

[0008]

According to the present invention, there is provided a logic circuit fault diagnosis apparatus for reading logic circuit design data described at an operation description level, and describing a state transition machine for the read logic circuit design data. Means for creating a state transition diagram, means for creating a logic circuit test pattern for specifying a fault location with a register as a candidate for a failure based on the created state transition diagram, and the created logic circuit test pattern Means for testing a logic circuit to extract a test pattern in which a failure is detected, and extracting a test pattern that causes the logic circuit to operate erroneously by performing a gate-level failure diagnosis on the extracted test pattern. Means for performing a gate-level failure diagnosis for estimating an internal operation of the logic circuit in a test pattern in which an erroneous operation has been performed. And wherein the door.

A logic circuit fault diagnosis method according to the present invention includes the steps of reading logic circuit design data described at an operation description level, and creating a state transition diagram as a description of a state transition machine for the read logic circuit design data. Creating a logic circuit test pattern for specifying a fault location with a register as a candidate for a failure based on the created state transition diagram, and testing the logic circuit with the created logic circuit test pattern. Extracting a test pattern in which a fault is detected by performing the test, and performing a gate-level fault diagnosis on the extracted test pattern to extract a test pattern that causes the logic circuit to operate erroneously, and perform those erroneous operations. Means for performing a gate-level failure diagnosis for estimating an internal operation of the logic circuit in a test pattern. And wherein the door.

[0010] The recording medium storing the logic circuit failure diagnosis program according to the present invention includes a computer for reading logic circuit design data described at an operation description level, and a state transition machine of the state transition machine for the read logic circuit design data. Means for creating a state transition diagram as a description, means for creating a logic circuit test pattern for specifying a fault location with a register as a failure candidate based on the created state transition diagram, and the created logic circuit test pattern. Means for testing a logic circuit and extracting a test pattern in which a failure is detected;
By performing a gate-level failure diagnosis on the extracted test pattern, a test pattern that causes the logic circuit to operate erroneously is extracted, and a gate that estimates the internal operation of the logic circuit in the test pattern that performed the erroneous operation is extracted. A program for functioning as a means for performing a level failure diagnosis is recorded.

Another logic circuit fault diagnostic apparatus according to the present invention is a means for reading logic circuit design data described at an operation description level, and a state transition diagram as a description of a state transition machine for the read logic circuit design data. Means for creating a logic circuit test pattern for identifying a fault location with a register as a candidate for a failure based on the created state transition diagram, and a logic circuit based on the created logic circuit test pattern. The present invention is characterized in that it includes means for performing a test to limit a failure location determination target area in the gate level fault inference of the logic circuit, and means for performing gate level fault inference on the limited area.

In another logic circuit fault diagnosis method according to the present invention, a step of reading logic circuit design data described at an operation description level, and using the read logic circuit design data as a state transition machine description as a state transition diagram And a step of creating a logic circuit test pattern for specifying a failure point with the register as a candidate for a failure based on the created state transition diagram, and a logic circuit based on the created logic circuit test pattern. The method includes a step of performing a test to limit a target area for determining a fault location in the gate-level fault inference of the logic circuit, and a means for performing a gate-level fault inference on the limited area.

According to another aspect of the present invention, there is provided a recording medium storing a logic circuit failure diagnosis program, comprising: a computer for reading logic circuit design data described at an operation description level;
Means for creating a state transition diagram as a state transition machine for the read logic circuit design data, and based on the created state transition diagram, create a logic circuit test pattern for specifying a fault location with a register as a failure candidate Means for testing a logic circuit with the created logic circuit test pattern to limit a fault location determination target area in gate level fault inference of the logic circuit, means for performing gate level fault inference on the limited area, A program for functioning as a program is recorded.

In short, in the present invention, a test pattern for register level fault diagnosis for testing all transitions from state to state is generated using a state transition diagram obtained by regarding a given logic circuit as a state transition machine. I do. Then, by using this generated test pattern to perform a failure diagnosis at the register level, information for performing a gate-level failure diagnosis is generated. The gate-level failure diagnosis is performed using this information. Thus, by generating the test pattern without performing the failure simulation, the failure diagnosis target is not limited to the simulated failure.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of a logic circuit fault diagnosis apparatus according to the present invention. In the figure, the diagnostic apparatus according to the present embodiment is an LSI (Large Scal
e Integrated Circuit) Design CAD (Computer Aided D)
esign) a data reader 1 for reading data, an FSM creator 2 that configures a state transition machine from function description data among data read by the data reader 1, and a state transition machine that is configured by the FSM creator 2. A state specifying vector creator 3 for creating an input vector and an output vector to the state transition machine for specifying each state, and an input / output vector for specifying each state created by the state specifying vector creator 3 are used for the state transition machine. A test pattern creator 4 for creating a test pattern for diagnosing a failure, a register-level failure diagnoser 5 for executing a test pattern created by the test pattern creator 4 to diagnose a register-level failure, and a register-level failure A gate-level failure diagnostic device 6 that receives a diagnostic result performed by the diagnostic device 5 and performs a gate-level failure diagnosis, and outputs the diagnostic result to an output device. It is configured to include a cross-sectional result output unit 7. Here, FSM (Finite State)
“Machine” is a finite state transition machine, and represents a logic machine (circuit) by a relationship between an internal state and an input and an output.

FIG. 2 shows an example of the configuration of the data reader 1 in FIG. Referring to FIG. 1, a function description data reading unit 101 in a data reader 1 writes function description data describing a function of a specified logic circuit.
It is read from the function description storage device 100. The function description data storage unit 102 receives the function description data read by the function description data reading unit 101, and
Write to 01.

FIG. 3 shows a configuration example of the FSM generator 2 in FIG. Referring to FIG.
Of the function description storage buffer 1
The function description of the logic circuit stored in 001 is received, a register is extracted from the received function description of the logic circuit, and the extracted register information is passed to the state node deriving unit 202. The state node deriving unit 202 receives the register information received from the register extracting unit 201, checks possible values for each register, and determines all possible combinations of values of all registers according to the format shown in FIG. It is stored in the state node storage memory 1002. FIG. 4 shows a format including possible value fields for registers (registers) 1 to n.

Referring back to FIG. 3, the function description simulating unit 20
3 derives a state transition by a procedure described later based on the state node information stored in the state node storage memory 1002, and stores the state transition in the state transition storage buffer 1003a. The FSM state transition diagram configuration unit 204 includes a state transition storage buffer 1003
Referring to a, a state transition diagram is constructed. Then, the FSM state transition diagram configuration unit 204 stores the configured state transition diagram in the state transition diagram storage memory 1003.

Here, the function description simulation section 203 will be described in detail with reference to FIG. Referring to FIG. 5, the function description simulating unit 203 reads the function description of the logic circuit from the function description storage buffer 1001 (step S131).

Next, the function description simulation unit 203
The first state stored in the state node storage memory 1002 is received (step S132). Next, the logic circuit simulation unit 203 stores the finite state machine in the node storage memory 1.
The value of each register is determined to make the same state as the state read from 002 (step S133). Next, the logic circuit simulating unit 203 sequentially extracts one input vector from the input vector storage buffer storing all the logic vectors that can be input signals to the logic circuit (step S134), and extracts the input vector extracted by the logic circuit. Input (step S135).

Next, the logic circuit simulation unit 203
A function description simulation is performed (step S136), and an output value and a simulation value are grasped (step S1).
37). Then, the value of each register of the logic circuit obtained after the input vector input is obtained, and the state of the logic circuit is obtained in the format shown in FIG.
Find the output of the logic circuit.

Next, the logic circuit simulation section 203
The original state, the input vector, the output vector, and the state after the execution of the input are stored in the state transition storage buffer 1003a in the format shown in FIG. 6 (step S1).
38). Here, referring to FIG. 6, the storage format of the state transition storage buffer 1003a includes fields of “state continuous number”, “input vector”, “output vector”, and “sequence number of state after transition”.

Returning to FIG. 5, if there is an input vector that has not been simulated for the state currently being read from the state node storage memory 1002, the next input signal is read from the state node storage memory 1002 and processed. Is repeated (step S138 → S134). In addition, if simulation has been performed for all input vectors for the state currently being read from the state node storage memory 1002, it is checked whether or not there is a non-simulated node in the state node storage memory 1002. I do. If there is a node that has not been simulated in the state node storage memory 1002, the next node is selected and the process is repeated (step S138 → S132). If the simulation has been completed for all the state nodes, the function description simulating unit 203 ends the process (step S139).

Next, FIG. 7 shows a configuration example of the state specifying vector generator 3 in FIG. Referring to FIG. 7, the target state selecting unit 30 in the state specifying vector creator 3
1 receives the state nodes in order from the state node storage memory 1002. Target state selection unit 301 that has received the state node
Converts the received state node into the state specifying vector extraction unit 30.
Hand over to 2. The state specifying vector extracting unit 302 that has received the state node specifies an input vector for confirming the state of the state transition machine according to the procedure shown in FIGS.

Next, the operation of the state specifying vector extraction unit 302 will be described with reference to FIGS. First,
In FIG. 8, the state transition diagram storage memory 1003 is sequentially searched using the received state node as a key (step S11).
1) If there is no corresponding record, the process ends (step S112 → S118). On the other hand, if there is a corresponding record, it is received (step S113), and the input vector, the output vector, and the number of vectors of the received record are set to “1” and stored in the state specifying vector candidate storage memory 1004 (step S114).

Next, the state transition diagram storage memory 1003 is sequentially searched using the input vector and the output vector of the record received in step S113 as keys (step S1).
15). If there is no corresponding record, the process returns to step S111 and repeats the process (step S115 → S116 → S1)
11 ...). On the other hand, if there is a corresponding record, the "continuation number of the state after transition" of the corresponding record is received (step S1).
16). Referring to FIG. 9, records are sequentially searched in the state transition diagram storage memory 1003 using the keys as a key (step S1).
21), receiving the searched record (step S12)
3) The input vector and the output vector are stored in the state specifying vector candidate storage memory 1004 (step S12).
4).

Using the input vector and the output vector of the record received in step S123 as keys, the state transition diagram storage memory is sequentially searched (step S125). If there is such a record, the process returns to step S121 to repeat the process (step S125 → S126 → S121...). On the other hand, if there is no corresponding record, it is determined that the candidate of the state specifying vector is determined, and the state specifying vector candidate storage memory 100
4 are stored as candidates for the state specifying vector (step S12).
7), the process returns to step S111 in FIG. 8 and repeats the process (step S127 → S111...).

Next, an example of the configuration of the test pattern generator 4 in FIG. 1 will be described with reference to FIG. Referring to FIG. 10, test state selecting section 401 sequentially receives state nodes from state node storage memory 1002. The test state selection unit 401 that has received the state node passes the received state node to the test generation unit 402. Upon receiving the state node, the test generation unit 402 changes the state transition diagram storage memory 100
3 to determine an input for a state transition from the reset state defined in the logic circuit to the received state node.

The state transition from the reset state to the received state node will be described below. The test generation unit 402 that has received the state node stores the state node value as the value of the continuation number of the state after the transition.
The record of 003 is searched.

Next, the state continuation number is extracted from all the retrieved records, and a record having the value as the continuation number of the state after the transition is searched. This search is repeated, and if the already searched state node is searched again, the process is terminated there. If the received state node is searched without terminating the processing, the records searched from the reset state to the state node that has been received are set as candidates for state transition from the reset state to the received state node. When all the searches are completed, the record group having the smallest number of records among the record groups which are candidates for the state transition from the reset state to the received state node is set as the state transition from the reset state to the received state node.

Next, the test generation unit 402 inputs a state transition from the determined reset state to the received state node, and inputs a vector obtained by searching the state specifying vector candidate storage memory 1004 using the received state node as a key. And the output are stored in the test vector storage buffer 4001.

Next, the test generation unit 402 receives a state transition from the determined reset state to the state node received and a record having the received state node as a state continuation number, and receives the pair from the determined reset state. The state transition to the state node, and then the record having the next received state node as the state continuation number are stored in the test vector storage buffer 4001 in order.

In this case, the state transition from the determined reset state to the received state node, and the next record having the received state node as a state continuation number are stored in the order shown in FIG. Referring to FIG. 7, the format includes fields of “input vector”, “output vector”, and “detection vector flag”. Note that the field “detection vector flag” in FIG. 11 is turned off in the record of the state transition from the reset state to the received state node, and turned on in the record having the received state node as the state continuation number.

When all the state nodes received by the test generation unit 402 have been stored in all the test vector storage buffers 4001, the test vector storage buffer 40
01 is stored in the test vector storage device 1006
And the processing of the test state selection unit 401 is repeated. If there is no unprocessed state node in the state node storage memory 1002, the test pattern creator 4 ends the processing.

Next, an example of the configuration of the register level fault diagnostic device 5 in FIG. 1 will be described with reference to FIG. FIG.
In the above, the test execution unit 501 in the register-level fault diagnostic device 5 inputs the test vector for logic circuit fault diagnosis stored in the test vector storage device 1006 to the logic circuit, and the result of inputting the test vector for logic circuit fault diagnosis. In order to obtain the output of the logic circuit obtained as
The logic circuit control device 500 such as an SI tester is operated.
If an output different from the vector described in the test vector for logic circuit failure diagnosis stored in the test vector storage device 1006 is sent from the logic circuit, the value of the output field of the test vector and the logic obtained from the logic circuit control device 500 are output. The output of the circuit is passed to the test result determination unit 502.

The test vector extraction unit 502 to which the value of the output field of the test vector and the output of the logic circuit obtained from the logic circuit control device 500 are passed, if the detection vector flag of the error test vector is on, The vector and the vector sequence immediately before the vector are traced back while the detected vector flag is off, and are passed to the gate-level fault diagnostic device 6 in FIG.

Next, the gate-level failure diagnostic device 6 shown in FIG.
Will be described with reference to FIG. The gate-level fault diagnostic device 6 executes the test vector received from the register-level fault diagnostic device 5 and receives the result,
Perform gate-level fault diagnosis.

As shown in FIG. 13, the gate-level fault diagnostic device 6 includes a netlist data reading unit 601 for reading netlist data, a test result reading unit 602 for reading test results, and the above-described vector. It is configured to include a failure trace execution unit 603 for executing a sequence trace and a failure location estimation unit 604 for estimating a failure location.
With this configuration, the gate-level failure diagnostic device 6 performs a gate-level failure diagnosis on the test pattern. The diagnosis result by the gate-level failure diagnostic device 6 is as follows:
It is passed to the diagnostic result output unit 7 in FIG. The diagnostic result output device 7 passes the result to an output device such as a display.

The gate-level failure diagnostic device 6 may execute a gate-level failure diagnosis as described in Japanese Patent Application Laid-Open No. H11-160400.

As described above, by performing the diagnostic processing shown in FIGS. 8 and 9, in the present apparatus, a test pattern in which a failure is detected is not diagnosed at the gate level without simulating the failure pattern. Is implemented.

By preparing a recording medium on which a program for realizing the processes shown in FIGS. 8 and 9 described above is recorded and controlling each unit shown in FIG. 1 using the recording medium, the same diagnostic processing as described above can be performed. Clearly what can be done. The recording medium includes a semiconductor memory not shown in FIG.
Various recording media other than the magnetic disk device can be used. As a result of adding this recording medium, the configuration of FIG.
As shown in FIG. That is, as shown in FIG. 14, the data reader 1, the FSM creator 2, the state specifying vector creator 3, the test pattern creator 4, the register-level fault diagnostics 5, the gate-level fault diagnostics 6, and the diagnosis The result output device 7 is controlled by a program recorded on the recording medium 8.

If the computer is controlled by the program recorded on the recording medium, it is obvious that the diagnostic processing can be performed in the same manner as described above. As this recording medium, various recording media other than the semiconductor memory and the magnetic disk device can be used.

Next, another embodiment of the logic circuit failure diagnosis apparatus according to the present invention will be described with reference to the drawings.

The diagnostic device of the present embodiment performs the same operation as the device of the above-described embodiment. However, in the device of the present embodiment, unlike the above-described failure diagnosis device, the register-level failure diagnostic device 5 performs a failure diagnosis at the register level of the logic circuit by the following operation.

That is, the register level fault diagnostic device 5
Receives a test vector from the test vector storage device 1006 and stores the test vector in a logic circuit control device 500 such as an LSI tester.
Pass the input of the received test vector to. Further, the register-level fault diagnostic device 5 uses the logic circuit
An output of a logic circuit obtained as a result of operating the SI is received. The register-level fault diagnostic device 5 executes the following when the output of the received logic circuit and the output of the test vector received from the test vector storage device are different.

The register-level fault diagnosing device 5 obtains a register value from the logic circuit control device 500 for a test vector in which the output of the received logic circuit and the output of the test vector received from the test vector storage device 1006 are different. To obtain the values of all the registers of the logic circuit in the format shown in FIG. Register level fault diagnostic device 5 that has obtained the register value
The state node storage memory 1003 further uses a sequential number of the state after the transition of the test vector as a key for a test vector having a different output from the received logic circuit and an output of the test vector received from the test vector storage device.
To obtain the value of each register.

Next, the register-level fault diagnostic device 5 retrieves the state node storage memory 1003 by using the received values of all the registers of the logic circuit and the serial number of the state after the transition of the test vector as a key. The value of each register is passed to the gate level fault diagnostic device 6.

Next, the gate-level fault diagnosing device 6 uses the values of all the registers of the logic circuit received from the register-level fault diagnosing device 5 and the sequential number of the state after the transition of the test vector as a key to store the state node memory A gate-level failure diagnosis in the combinational logic circuit is performed using the values of the registers obtained by searching 1003. In other words, by the diagnosis of the register-level fault diagnostic device 5, the target area of the fault location determination in the gate-level fault inference of the logic circuit is limited, and the gate-level fault diagnostic device 6 performs the gate-level fault inference on the limited area. become.

The gate-level fault diagnostic unit 6 executes the test vector received from the register-level fault diagnostic unit 5, receives the result, and performs a gate-level fault diagnosis. The gate-level failure diagnostic device 6 performs a diagnostic process as shown in FIG. The result of this diagnosis is
It is passed to the diagnostic result output device 7. The diagnostic result output device 7 passes the result to an output device such as a display.

The gate-level failure diagnostic device 6 may execute a gate-level failure diagnosis as described in, for example, Japanese Patent Application Laid-Open No. 11-160400.

By performing the diagnostic processing as described above,
In this system, a logic circuit failure diagnosis method for limiting the failure area determination target region of the logic circuit and performing a gate-level failure diagnosis on the limited region is realized.

It is to be noted that, as described above, a recording medium for recording a program for realizing a process for performing a gate-level failure diagnosis on the limited region as a target for the failure portion determination target region, It is apparent that the same diagnostic processing as described above can be performed by controlling each unit in FIG. 1 using this. This recording medium includes a semiconductor memory and a magnetic disk device not shown in FIG.
Various recording media can be used. As a result of adding this recording medium, the configuration of FIG. 1 is as shown in FIG. That is, as shown in FIG. 14, the data reader 1, the FSM creator 2, the state specifying vector creator 3, the test pattern creator 4, the register-level fault diagnostics 5, the gate-level fault diagnostics 6, and the diagnosis Result output device 7
Is controlled by a program recorded in the recording medium 8.

It is obvious that the diagnostic processing can be performed in the same manner as described above if the computer is controlled by the program recorded on the recording medium. As this recording medium, various recording media other than the semiconductor memory and the magnetic disk device can be used.

[0055]

As described above, according to the present invention, by generating a test pattern without performing a failure simulation, the object of the failure diagnosis is not limited to the simulated failure. Further, by determining whether or not the given place is within the area by a mathematically simple operation, there is an effect that the wiring connection information can be immediately obtained. Furthermore, by testing the logic circuit to limit the target area for determining the fault location in the gate-level fault inference, and performing gate-level fault inference on the limited area, the fault of the given logic circuit can be detected faster and more accurately. This has the effect of being able to estimate well.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic circuit fault diagnosis device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a data reading unit.

FIG. 3 is a block diagram illustrating a configuration example of an FSM creating device.

FIG. 4 is a diagram showing a format of data stored in a state node storage memory.

FIG. 5 is a flowchart showing the operation of a function description simulation unit.

FIG. 6 is a diagram showing a format of data stored in a state transition diagram storage memory.

FIG. 7 is a block diagram illustrating a configuration example of a state specifying vector generator.

FIG. 8 is a part of a flowchart showing a state specifying vector detection procedure.

FIG. 9 is a part of a flowchart showing a state specifying vector detection procedure.

FIG. 10 is a block diagram illustrating a configuration example of a test pattern generator.

FIG. 11 is a diagram showing a format of a test vector storage device record.

FIG. 12 is a block diagram illustrating a configuration example of a register-level fault diagnostic device.

FIG. 13 is a block diagram illustrating a configuration example of a gate-level failure diagnostic device.

FIG. 14 is a block diagram showing a configuration of a logic circuit fault diagnosis device according to another embodiment of the present invention.

FIG. 15 is a diagram showing an example of a conventional logic circuit failure diagnosis device.

FIG. 16 is a diagram showing another example of a conventional logic circuit failure diagnosis device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data reader 2 FSM creator 3 state specifying vector creator 4 test pattern creator 5 register-level fault diagnoser 6 gate-level fault diagnoser 7 diagnostic result output 8 recording medium 100 function storage 101 function description data reader 102 Function description data storage unit 201 Register extraction unit 202 State node derivation unit 203 State description simulation unit 204 FSM state transition diagram construction unit 301 Target state selection unit 302 State identification vector extraction unit 401 Test state selection unit 402 Test generation unit 500 Logic Circuit control device 501 Test execution unit 502 Test result determination unit 601 Netlist data reading unit 602 Test result reading unit 603 Fault trace execution unit 604 Fault location estimation unit 1001 Function description data storage buffer 1002 State node description Storage memory 1003 state transition diagram storage memory 1003a state transition storage buffer 1004 state specific vector candidate storage memory 1006 test vector storage device 4001 test vector storage buffer

Claims (6)

[Claims] 1. Means for reading logic circuit design data described at an operation description level, means for creating a state transition diagram as a description of a state transition machine for the read logic circuit design data, and the created state Means for creating a logic circuit test pattern for specifying a failure location with a register as a candidate for a failure based on the transition diagram, and a test pattern for detecting a failure by testing a logic circuit using the created logic circuit test pattern Means for extracting a test pattern for erroneously operating the logic circuit by performing a gate-level fault diagnosis on the extracted test pattern, and extracting the test pattern for the logic circuit with the erroneously operated test pattern. Means for performing a gate-level failure diagnosis for estimating an internal operation. 2. A step of reading logic circuit design data described at an operation description level, a step of creating a state transition diagram as a description of a state transition machine for the read logic circuit design data, and a step of creating the created state A step of creating a logic circuit test pattern for specifying a failure location with the register as a candidate for failure based on the transition diagram; and a test pattern for detecting a failure by testing the logic circuit with the created logic circuit test pattern. Extracting
By performing a gate-level failure diagnosis on the extracted test pattern, a test pattern that causes the logic circuit to operate erroneously is extracted, and a gate that estimates the internal operation of the logic circuit in the test pattern that performed the erroneous operation is extracted. Means for performing a level failure diagnosis. 3. A computer for reading logic circuit design data described at an operation description level, means for creating a state transition diagram as a description of a state transition machine for the read logic circuit design data, Means for creating a logic circuit test pattern for specifying a fault location with a register as a failure candidate based on the state transition diagram, and a test pattern for detecting a fault by testing a logic circuit using the created logic circuit test pattern Means for extracting a test pattern for erroneously operating the logic circuit by performing a gate-level failure diagnosis on the extracted test pattern, and extracting the test pattern inside the logic circuit with the erroneously operated test pattern. It is characterized by recording a program for functioning as a means for performing gate-level failure diagnosis for estimating operation. Recording medium 4. A means for reading logic circuit design data described at an operation description level, means for creating a state transition diagram as a description of a state transition machine for the read logic circuit design data, Means for creating a logic circuit test pattern for specifying a failure location with a register as a failure candidate based on the transition diagram; and testing the logic circuit with the created logic circuit test pattern to check the gate level failure of the logic circuit. A logic circuit fault diagnosis apparatus, comprising: means for limiting a fault location determination target area in inference; and means for performing gate level fault inference on the limited area. 5. A step of reading logic circuit design data described at an operation description level, a step of creating a state transition diagram using the read logic circuit design data as a description of a state transition machine, and a step of creating the created state A step of creating a logic circuit test pattern for identifying a failure location with the register as a candidate for a failure based on the transition diagram; and testing the logic circuit with the created logic circuit test pattern to infer a gate level failure of the logic circuit And a means for inferring a gate-level fault in the limited area as a target. 6. A computer for reading logic circuit design data described at an operation description level, a means for creating a state transition diagram as a state transition machine for the read logic circuit design data, and the created state transition Means for creating a logic circuit test pattern for specifying a failure location with a register as a candidate for a failure based on the diagram, and testing the logic circuit with the created logic circuit test pattern to detect a fault in the logic circuit gate-level fault inference. A recording medium having recorded thereon a program for functioning as a means for limiting an area to be subjected to location determination, and a means for performing a gate-level fault inference on the limited area.