JP2001174523A - Trouble analysis device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a highly accurate trouble analysis for a DUT not operated stably even if a same test pattern is input. SOLUTION: This trouble analysis device comprises a detection part 5 of an integrated circuit for extracting DUT part information 12 from the device under test (DUT) information 1, a classifying and controlling part 6 for classifying the status information 2 showing the state of the integrated circuit when the DUT information is obtained based on specified classification conditions 3 and outputting classification information 11, a classifying part 7 for classifying the DUT part information 12 based on the classification information 11, and a construction part 8 for averaging, for each classification information 11, the DUT part information 12 classified based on the classification information 11 and re-arranging the order of the DUT part information 12 based on the timing of acquisition of the DUT part information 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis device for an integrated circuit, and more particularly to a failure analysis device capable of correctly performing a failure analysis of an unstable integrated circuit that does not repeat the same operation even when the same test pattern is input. About.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (LSIs) have become increasingly sophisticated, highly integrated, and large-scale. For this reason, large-scale integrated circuits that do not operate normally have been produced. Normally, failure analysis is performed on the inside of a device of such a large-scale integrated circuit that does not operate normally using an electron beam tester (EB tester), an emission microscope, or the like.

FIG. 6 is a schematic configuration diagram of a conventional EB tester. As shown in the figure, the EB tester has an electron gun 62,
It comprises a stage 63, a detector 64, a display device 66, and an LSI tester 68. LSI tester 68 to LSI6
5, a test pattern is input, and LSI 65 to LSI
The test result is output to the tester 68. Then, an electron beam is emitted from the electron gun 62 to the LSI 65 on the stage 63, and the emitted secondary electrons are detected by the detector 64. The detected secondary electrons are analyzed, image processed, and
The voltage waveform 68 of the internal wiring of I65 is displayed on the display device 69.

In such a failure analyzer such as an EB tester, the same test pattern is repeatedly input to the LSI 65, and the same test pattern is repeatedly irradiated with an electron beam.
The secondary electrons are analyzed to form a voltage waveform. Such a voltage waveform is configured by performing integration and averaging on each voltage waveform obtained every time secondary electrons are detected.

FIG. 7 is a diagram showing a relationship between a waveform measurement timing, a waveform obtained by each measurement, and an averaging result obtained by averaging a plurality of waveforms. In the figure, the repetition period R
C indicates a cycle of repeating the input of the same test pattern,
The waveform measurement period is a part of the repetition period RC,
This shows the period during which waveform measurement is performed for each input of the same test pattern. The first to third acquired waveform data indicate the first divided period, the second divided period, and the third divided period, respectively, among the divided periods obtained by dividing the waveform measurement period into three equal parts. In the example shown in this figure, the first, fourth,.
The (3n + 1) th acquired waveform data is waveform data obtained by measuring the first divided period (n).
Is 0 or a natural number). Also, the second, fifth, ...,
The (3n + 2) -th acquired waveform data is waveform data obtained by measuring the second divided period. The third, sixth,..., And 3n-th acquired waveform data are all waveform data obtained by measuring the third divided period.

As described above, the first acquisition waveform data and the fourth acquisition data are both waveform data obtained by measuring the first divided period. However, as shown in FIG. 7, the first acquisition waveform data and the fourth acquisition data are not the same. Further, both the second acquired waveform data and the fifth acquired data are waveform data obtained by measuring the second divided period. However, as shown in FIG. 7, the second acquisition waveform data and the fifth acquisition data are not the same.

Even if the same test pattern is input and waveform data is acquired at the same timing, the same waveform may not always be acquired because the device operation may be different.

[0008]

However, conventionally, the same test pattern is input, and the waveforms acquired at the same timing are integrated and averaged to obtain the waveform for each divided period.
By connecting the waveforms obtained in this way, FIG.
A waveform like the averaging result shown in FIG.

That is, although the device operation is different between the first acquired waveform data and the fourth acquired waveform data shown in FIG. 7, similarly, the second acquired waveform data and the fifth acquired waveform data have the same characteristics. Even though the device operations are different, the data is averaged without considering such a difference in device operation, so that a failure may not be analyzed correctly.

The present invention has been made to solve these problems, and an object of the present invention is to provide an apparatus which can perform correct failure analysis by classifying acquired data according to device operation. .

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is an integrated circuit failure analysis apparatus for extracting partial under test (DUT) information from integrated circuit device under test (DUT) information. A detection unit, a classification control unit that classifies state information indicating a state of the integrated circuit when the DUT information is obtained based on a predetermined classification condition, and outputs classification information;
A classification unit that classifies the DUT partial information based on the classification information, an average of the DUT partial information classified based on the classification information for each classification information, and an order of the DUT partial information based on a timing at which the DUT partial information is acquired Are arranged to construct a DUT measurement result.

Here, the classification condition includes a test path
It may be fail information, fail address, fail pin and fail pin status values, or a combination thereof. Here, the fail pin status values include high, low,
Includes indefinite or high impedance.

According to the present invention, the classification information is obtained by classifying the state information based on the classification condition, the DUT partial information is classified based on the classification information, and the DUT partial information having the same classification information is averaged. Therefore, even if a DUT whose output result is not stable even if the same test pattern is repeatedly input, only a specific state operation of two or more DUT states can be selectively observed, or a plurality of state operations can be performed. Can be observed separately, and highly accurate failure analysis can be performed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 4 show a first embodiment of the present invention. FIG. 1 is a diagram showing a configuration of a failure analysis device. FIG. 2 is a flowchart showing a flow of processing in the failure analysis device.
Is a diagram showing a relationship between a repetition cycle, a waveform measurement period, a sampling time, an input signal, and an output signal, and FIG. 4 is a diagram showing a relationship between waveform data obtained by each measurement and an averaging result of each state. .

First, FIG. 1 will be outlined. As shown in FIG. 1, the failure analysis device according to the present embodiment includes a detection unit 5,
Classification control unit 6, classification unit 7, construction unit 8, storage unit 9
And a display unit 10.

The detector 5 receives device under test (DUT) information 1 and outputs partial DUT information 12. The state information 2 and the classification condition 3 are input to the classification control unit 6, and the classification information 11 is output. The classification control unit 6 calculates the DUT partial information 1 based on the state information 2 and the classification condition 3.
The classification information 11 for classifying 2 is output. Detector 5
Outputs DUT partial information 12 from DUT information 1.
The classification unit 7 converts the DUT partial information 12 into the corresponding classification information 1
Classify according to 1. The construction unit 8 includes the DUT partial information 1
2 are grouped by the same classification, and one DUT measurement result 1
Build as 3. The storage unit 9 stores the constructed DUT measurement results 13 for each classification. The display unit 10 includes the storage unit 9
Is displayed as the DUT measurement result display 4 that can be visually recognized. The DUT information 1, the status information 2, the classification condition 3, the classification information 11, the DUT partial information 12, and the DUT measurement result 13 will be described after overviewing FIGS.

Next, FIG. 2 will be outlined. As shown in FIG. 2, the failure analysis apparatus according to the present embodiment first reads the classification condition 3 (S101), then loads the DUT information 1 (S102), further captures the state information 2, and outputs the classification information 11. (S103). And classification information 11
The DUT partial information 12 is classified according to (S104), and the classified DUT partial information 12 is accumulated for each classification information 11, constructed as a DUT measurement result 13, and stored (S1).
05). Then, it is determined whether or not to continue the measurement (S1).
06) If the measurement is to be continued, the process returns to step S102; otherwise, the constructed DUT measurement result 13 is output (S107).

Next, FIG. 3 will be outlined. In FIG. 3,
A voltage waveform is measured as DUT information.

Each of the repetition periods RC1, RC2, RC3, etc. is a period for repeatedly inputting the same test pattern. Also, a part of the repetition period is set as a waveform measurement period. Further, the waveform measurement target period is divided into three equal parts, and each waveform data is sampled. The first sampling time is set to ST1, and the second sampling time is set to ST.
The second and third sampling times are set to ST3. That is, the waveform measurement target period in each repetition period is common, but the sampling times are ST1, ST2, and ST3.

P, Q, R, and S indicate input pins. Then, the first input signal, the second input signal, the third input signal,..., The nth input signal in the repetition cycle CR1 are referred to as IS11, IS12, IS13,.
・ It will be IS1n. The first input signal, the second input signal, the third input signal,..., The n-th input signal in the repetition cycle CR2 are referred to as IS21 and I21, respectively.
S22, IS23,..., IS2n.

W, X, Y and Z indicate output pins. Then, the input signals IS11, IS12, IS13,.
The output signals corresponding to S1n are output to OS11 and OS11, respectively.
12, OS13,... OS1n. The output signals corresponding to the input signals IS21, IS22, IS23,.
23,... OS2n.

In the example shown in FIG. 3, a case where the input signal and the output signal are the same is regarded as a path, and a case where the input signal and the output signal are different is regarded as a fail. Therefore, the output pin W of the output signal OS11 in the repetition cycle RC1, the output pin X of the output signal OS23 of the repetition cycle RC2, and the output pin X of the output signal OS43 in the repetition cycle RC4 fail. In the repetition period RC3, both the output pin W of the output signal OS31 and the output pin X of the output signal OS33 fail.

Next, FIG. 4 will be outlined. First time, second time,
The third and fourth acquired waveform data are (repetition period RC1, sampling time ST1), (repetition period RC2, sampling time ST2), (repetition period RC3, sampling time ST3), and (repetition period R, respectively).
C4, data obtained at the sampling time ST1).

Next, the first embodiment will be specifically described with reference to FIGS.

First, the same test pattern is repeatedly input to the DUT (device under test, device under test) by the LSI tester, and secondary electron detection by the EB tester is started. Then, the classification control unit 6 sets the classification condition 3
Is read (S101), the detection unit 5 captures the DUT information 1 (S102), the classification control unit 6 captures the state information 2, and outputs the classification information 11 (S103).

DUT information 1 is information obtained by analyzing the inside of an integrated circuit which is a DUT. More specifically, there are a voltage waveform, a potential distribution image obtained by an electron beam (EB) tester, a light emission image obtained by an emission microscope, a heat generation image, and the like. FIG. 4 shows a case where the DUT information 1 is a voltage waveform.

The state information 2 is information that defines the state of the DUT. More specifically, the information includes information obtained by investigating the electrical characteristics of the integrated circuit to be tested.
This is information obtained from an output signal for a tester pattern input from the tester. The output signals OS11 and OS1 in FIG.
, OS 21, 22, 23,..., A fail address indicating which output signal contains an error, a fail pin indicating which pin has an error, etc. Becomes the state information 2.

The classification condition 3 is a condition for classifying a device state. Specifically, there are a fail address, a first fail address, a fail pin of an output signal for a test pattern, a combination thereof, and the like. The first fail address is a fail address in which an error first occurs in one repetition period.

For example, during one repetition period, the first output signal having an error is the first output signal O
S11, OS21, OS31... Or OSm1 (m is a natural number) is defined as the first fail address a, and the first output signal having an error is the third output signal OS13, OS23, OS33.
Is the first fail address b, and the first fail address a and the first fail address b are set as the classification conditions.

The classification information 11 is information indicating which classification condition 3 the status information 2 is classified as.

For example, when the first fail address a is set to the state a, the first fail address b is set to the state b, and other states are set to the state c, the repetition period RC1
Since the first output signal in which an error has occurred is the first output signal OS11 (specifically, the W pin), the state a
are categorized.

The repetition period RC2 or RC4 is
Since the first output signal in which an error has occurred is the third output signal OS23 or OS43 (specifically, the X pin), it is classified as state b.

On the other hand, also in the repetition period RC3, the X pin of the third output signal OS33 is failed, but the first output signal OS31 (specifically, the W pin) is failed. being classified.

That is, the classification information 11 includes the repetition period R
C1 and RC3 enter state a, and the repetition periods RC2 and R
C4 is in state b.

The DUT partial information 12 indicates that the failure analysis device
This is information that can be obtained at a time from the UT information.
In other words, if the failure analyzer acquires only one-third of the entire waveform at a time, one-third is a part of the DUT information obtained from the DUT, which is called DUT partial information.

1 obtained during the sampling time ST1
Second acquisition waveform data, second acquisition waveform data acquired within sampling time ST2, sampling time ST3
The third acquired waveform data and the like acquired within correspond to the DUT partial information.

The classification unit 7 performs DUT according to the classification information 11.
The partial information 12 is classified (S104).

More specifically, the first acquisition waveform data acquired at the repetition period RC1 and the sampling time ST1 is classified as the first fail address a.

Repetition period RC2, sampling time S
The second acquisition waveform data acquired at T2 is classified as the first fail address b.

Repetition period RC3, sampling time S
The third acquisition waveform data acquired at T3 is classified as the first fail address a.

Repetition period RC4, sampling time S
The fourth acquisition waveform data acquired at T1 is classified as the first fail address b.

The classified DUT partial information 12 is accumulated for each classification information 11 by the construction unit 8 and constructed as a DUT measurement result 13, and the DUT measurement result 13 is stored in the storage unit 9 (S105).

It is determined whether or not to continue the measurement based on whether or not each of the DUT partial information 12 having the same classification information 11 has reached a predetermined number (S106). The output DUT measurement result 13 is output (S10
7), end.

More specifically, the first acquired waveform data, the third acquired waveform data, and other data corresponding to the first fail address a are accumulated as common data. These stored data are further classified for each sampling time.

Similarly, the second acquisition waveform data, the fourth acquisition waveform data, and other first fail address b
Are stored as common data. These stored data are further classified for each sampling time.

That is, the number of waveform data at (first fail address a, sampling time ST1), (first fail address a, sampling time ST2)
, The number of waveform data at (first fail address a, sampling time ST1), the number of waveform data at (first fail address b, sampling time ST1), the number of waveform data at (fast fail address b, sampling time ST2), When the number of waveform data at (first fail address b, sampling time ST3) reaches a predetermined number, the measurement is stopped.

Then, the waveform data of (first fail address a, sampling time ST1), the waveform data of (fast fail address a, sampling time ST2), the waveform data of (fast fail address a, sampling time ST3), and the (fast fail address) The waveform data at the address b, the sampling time ST1), the waveform data at the (first fail address b, the sampling time ST2), and the waveform data at the (first fail address b, the sampling time ST3) are integrated and averaged.

Further, the averaged waveform data of (first fail address a, sampling time ST1)
(First fail address a, sampling time S
The averaged waveform data of (T2) and the averaged waveform data of (first fail address a, sampling time ST3) are connected to form the first fail address a.
The averaging result (shown in FIG. 4) of (state a) is obtained.

Similarly, the averaged waveform data of (first fail address b, sampling time ST1)
(First fail address b, sampling time S
The averaged waveform data of (T2) and the averaged waveform data of (first fail address b, sampling time ST3) are connected to form the first fail address b
The averaging result (shown in FIG. 4) of (state b) is obtained.

In the first embodiment, each waveform data is classified according to the first fail address and averaged, so that a DUT whose output result is not stable even if the same test pattern is repeatedly input is obtained. By performing classification according to the failure state, a highly accurate failure analysis can be performed.

Next, a second embodiment will be described with reference to FIG. The second embodiment is different from the first embodiment in that E
The B tester is replaced with an emission microscope. That is, the DUT information is a voltage waveform in the first embodiment, but becomes a light emission image in the second embodiment.

As shown in the figure, the acquired data when the DUT is in the state a, that is, the first acquired image data, the third acquired image data, and the like are classified according to the classification information and averaged as in the first embodiment. . The averaged result is the averaged result (emission image) of the state a.

The data obtained when the DUT is in state b, that is, the second acquired image data, the fourth acquired image data, and the like are classified according to the classification information, and the averaged result is the averaged result (light emission) in state b. Image).

In the second embodiment, the DU is also used.
By classifying each light emission image according to the T information and averaging, even for a DUT in which the light emission image is not stable even if the same test pattern is repeatedly input, the light emission image is classified according to the DUT state, thereby achieving accuracy. High failure analysis.

In the above embodiment, the DUT partial information 12 is classified into two or three states. However, the DUT partial information 12 can be classified into four or more states.

[0057]

As described above, according to the present invention,
Even if the output result is not stable even if the same test pattern is repeatedly input, the DUT information is classified according to the DUT state such as the fail state, so that only a specific state operation among two or more DUT states is performed. Can be selectively observed, or a plurality of state operations can be separately observed, and highly accurate failure analysis can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a failure analysis device according to the present invention.

FIG. 2 is a flowchart showing a processing flow in the failure analysis device of the present invention.

FIG. 3 is a diagram illustrating a relationship between a repetition period, a waveform measurement period, a sampling time, an input signal, and an output signal in the first embodiment.

FIG. 4 is a diagram illustrating a relationship between waveform data acquired by each measurement and an averaging result of each state in the first embodiment.

FIG. 5 is a diagram illustrating a relationship between a light emission image obtained by each measurement and an averaging result of each state in the second embodiment.

FIG. 6 is a diagram showing a configuration of a conventional EB tester.

FIG. 7 is a diagram showing a relationship between waveform data obtained by each measurement using a conventional apparatus and an averaging result of each state.

[Description of Signs] 1 DUT information 2 Status information 3 Classification condition 4 DUT measurement result display 5 Detection unit 6 Classification control unit 7 Classification unit 8 Construction unit 9 Storage unit 10 Display unit 11 Classification information 12 DUT partial information 13 DUT measurement result

Continuing from the front page (72) Inventor Moriya Kimata 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside (72) Inventor Yutaka Kamiyama 25-1, Ekimae Honmachi, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Toshiba Microelectronics Co., Ltd. In-house (72) Inventor Masato Shito 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture F-term (reference) 2G011 AA01 AD02 AE01 2G032 AB20 AE08 AE09 AE10 AF08 AG02 4M106 AA04 AA08 AC09 BA02 CA02 CA08 CA70 DE01 DE20 DJ02 DJ17 DJ20 DJ21 DJ23 DJ40

Claims (2)

[Claims] An apparatus for analyzing a failure of an integrated circuit, comprising: a device under test (DUT) for the integrated circuit.
A detection unit that extracts DUT partial information from information; a classification control unit that classifies state information indicating a state of the integrated circuit when the DUT information is obtained based on a predetermined classification condition and outputs classification information; A classification unit that classifies the DUT partial information based on the classification information; and averaging the DUT partial information classified based on the classification information for each classification information, and based on a timing at which the DUT partial information is acquired. A failure analysis device comprising a construction unit for constructing a DUT measurement result by rearranging the order of the DUT partial information. 2. The failure analysis apparatus according to claim 1, wherein the classification condition is pass / fail information of a test, a fail address, a state value of a fail pin and a fail pin, or a combination thereof.