JP2001168721A - Analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog/digital converter high in operating speed, high in precision and simple in configuration as much as possible since a quantization circuit corresponding to a bit number and a multi-valent digital/analog converter are required for making multiple bits and thus not only the scale of the circuit configuration is enlarged but also it is required to perform feedback timely from the respective quantization circuits at the time of acceleration in a conventional delta sigma analog/digital converter. SOLUTION: A multi-valent quantization circuit using a resonance tunnel diode is applied to the quantization circuit. Thus the quantization circuit part of the conventional delta sigma analog/digital converter is simplified, the multi- valent digital/analog converter is unnecessitated and the operating speed is easily accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter for converting an analog signal into a digital signal, and more particularly to an oversampling type delta-sigma analog-to-digital converter.

[0002]

2. Description of the Related Art A conventional delta-sigma (over-sampling) analog-to-digital converter is configured using a multi-bit quantization circuit in order to secure stability when higher order is performed. Often. This multi-bit delta-sigma analog-to-digital converter is shown in FIG.
As shown in FIG. 7, the digital signal processor comprises a multi-bit digital / analog converter (D / A converter) 8 in addition to a subtractor 3, an RC integrator 2, and a plurality of quantization circuits (1 to n). This method enables high resolution and high accuracy by converting the input signal bandwidth at a sufficiently high speed and reducing the number of bits by decimation using a digital filter, even if the quantization circuit has a low resolution. .

On the other hand, a flash type analog / digital converter having a configuration in which a plurality of elements having negative resistance characteristics shown in FIG. 8A are connected in series is known. Hereinafter, this operation will be described. For ease of explanation, an example of a ternary quantization circuit will be described, and the configuration and operation principle will be described. As shown in FIG. 8A, the configuration is assumed to be composed of four resonant tunneling diodes A, B, C and D and a field effect transistor operating in a depletion mode.
The operation of this circuit is as follows.
B, C, and D have current / voltage characteristics as shown in FIG. When the current exceeds a certain peak current value Vp, the resistance changes from the ON state with a small resistance to the OFF state with a large resistance.
Switch to state. Therefore, as shown in FIG. 8A, when a plurality of negative resistance elements are connected in series to keep Vss constant and increase the amplitude of Vclock, the resonant tunneling diodes with the smaller peak currents are turned off sequentially. Switch to Here, it is set so that only two of the four resonant tunneling diodes having smaller peak currents are sequentially switched, and Vcl
ock is oscillated until the maximum value of the amplitude turns off all the four resonant tunneling diodes as shown in FIG. 8B. At this time, by changing the value of Vin in FIG. 8A, the effective peak currents of the C and D2 resonant tunneling diodes can be modulated. This state is shown in FIG. Thus, assuming that only two RTD small peak current is switched, the Vin <V _TS C, D is, V _TS <
When Vin < _VTL , B and D are switched, and when _VTL <Vin, A and B are switched to an OFF state. At this time, FIG.
The output voltage Vout in (a) is changed by the switched resonant tunneling diode, and the output voltage changes to three levels as shown in the lower part of FIG. As a result, it can be used as a quantization circuit that outputs three types of discrete values with respect to the input (Literature: Takao Wabo, Toshihiro Ito, Ultrafast Resonant Tunneling Multilevel Circuit-New Possibilities of Quantum Effect Devices-, IEICE Transactions, VOL.J82-C-II, NO.
August, pp. 421-431, 1999)
Will be.

In the case of a flash type analog-to-digital converter, although high-speed operation is basically ensured due to parallel processing, comparators are required for the number of quantization steps. However, there is a problem that a tunnel diode having a required peak current value must be prepared. Although the peak current value of the tunnel diode can be controlled by the junction area of the diode, preparing a large number of tunnel diodes having different peak current values poses a problem in productivity.

As described above, when this conventional quantization circuit itself is constituted by an existing high-speed element such as HEMT, for example,
As shown in FIG. 9, the circuit scale of the quantization circuit per one step is relatively large. For this reason, there is an example in which a plurality of negative resistance elements such as resonance tunnel diodes are used in combination as shown in FIG. 10 to reduce the circuit scale.

[0006]

According to the prior art,
As described above, in a multi-bit delta-sigma analog-to-digital converter, not only a plurality of complicated circuit quantization circuits are required, but also a multi-bit digital-to-analog converter is required. And the delay time becomes long.
Therefore, in order to ensure accuracy and high-speed operation, it is necessary to feed back each bit with good timing, which has been a technical difficulty. The present invention provides a multi-bit delta-sigma analog-to-digital converter that alleviates such difficulties, does not impair the conversion speed, and minimizes the number of resonant tunneling diodes used as negative resistance elements. It is intended to do so.

[0007]

To achieve the above object, the present invention discloses the following means. That is, in the first aspect of the present invention, the analog-quantization circuit in the delta-sigma analog-to-digital converter is an analog multi-level quantization circuit, and the multi-level digital output of the analog multi-level quantization circuit is directly input. A configuration is disclosed in which a circuit is fed back to a side to form a subtraction circuit from an analog input.

According to a second aspect of the present invention, a circuit corresponding to the multi-level quantization circuit according to the first aspect includes n negative resistance elements, A, B,. Are connected in series, and transistors are connected in parallel to the n negative resistance elements C, D,. An input voltage is applied to the input terminal of this transistor,
.. And the above-mentioned n negative resistance elements C, D,.
This discloses a circuit configured to output (n + 1) types of voltages corresponding to 1) types of signals. Here, for example, a resonance tunnel diode or the like is used as the negative resistance element, and a field effect transistor is used as the transistor in the depletion mode.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration according to a first embodiment of the present invention, and shows a configuration of a delta-sigma type analog-to-digital converter using a multi-level quantization circuit. This circuit includes a multi-level quantization circuit 1 having a function of outputting discrete signals of several sizes when a continuous analog signal is input, an RC integrator 2, and a subtracter for subtracting an output signal from an input signal. 3 is used. Here, as shown in FIG. 7, one or a plurality of binary-level quantizers are conventionally connected in parallel as quantizers, and the outputs of these quantizers are output to a multi-bit digital-to-analog converter. Whereas the configuration for supplying and feeding back to the subtractor on the input side has been used, the present invention uses the multi-level quantization circuit 1 to provide the multi-level quantization conventionally required as shown in FIG. Eliminates the need for digital-to-analog converters. Further, in the present invention, the multi-level quantization circuit is obtained by using the analog-to-digital conversion circuit utilizing the negative resistance characteristic of the resonant tunneling diode described in the section of [Prior Art] as the multi-level quantization circuit 1. The structure is also simplified. The operation principle of the circuit shown in FIG. 1 is that a difference between a digital output as an output of the multi-level quantization circuit 1 and an input signal Vin as an analog quantity is obtained by a subtractor 3, and the result is integrated by an RC integrator 2. The feedback is performed so that the result of the integration is minimized, and the error between the digital output and the input signal is minimized. The specific operation of this circuit will be described below.

In the first embodiment, an input signal Vin shown in FIG. 1 is input to an RC integrator 2 through a subtractor 3, and its output is converted from an analog signal to a digital signal by a multi-level quantization circuit 1 to obtain several types of signals. It is assumed that the digital output Vout has a discrete value. The output is fed back to the subtractor 3 together with the input signal Vin. Its output is the aforementioned RC integrator 2
Has been entered. For this reason, since the output data is related not only to the input value but also to the previous data, the order of the output data is also significant.

As described above, the multi-level quantization circuit 1 used in the delta-sigma analog-to-digital converter using multi-level signals in the first embodiment of the present invention is shown in FIG. The multi-level quantization circuit 1 has a configuration shown in a circuit diagram, and is configured using the above-described resonant tunneling diodes A, B, C, and D. As an example,
The output voltage V of the ternary quantization circuit used in this device
out is set to be a value shown in Table 1 according to the input voltage Vin. Since the output of the ternary quantization circuit used here is inverted, an adder 4 is used instead of the subtractor 3 as shown in FIG. Here, when using a ternary quantization circuit whose output is not inverted, the ternary quantization circuit may be configured by using the subtractor 3.

[0013]

[Table 1]

FIG. 3 shows a second embodiment of the present invention. FIG. 3 shows the RC integrator 2 in the delta-sigma type analog-to-digital converter using a multi-level signal in the first embodiment described above as a band-pass filter 9 and a quantization circuit. Is replaced with a ternary quantization circuit 10, and a band-pass delta-sigma analog
2 shows a configuration of a digital conversion device. FIG. 4 is a circuit diagram of the band-pass filter 9 used in this device, which is composed of a resistor R, a capacitor C, and an inductor L. By adopting the band-pass delta-sigma method, analog-to-digital conversion is performed only in the band around the input signal, so that the noise level can be reduced, thereby effectively increasing the conversion speed. And the resolution is improved.

FIG. 5 shows a third embodiment of the present invention. In the first embodiment of the present invention, a delta-sigma analog / digital converter using a multilevel signal is used.
FIG. 3 is a block diagram when a multi-value decimation filter 5 is added to the digital conversion device. Even if the quantization circuit has a low resolution, the conversion is performed at a sufficiently high speed with respect to the input signal band, and the digital signal is decimated, so that the resolution and the accuracy are improved. Here, the multi-value output is directly decimated.

FIG. 6 shows a fourth embodiment of the present invention. This is also a delta-sigma analog / digital converter using a multi-level signal in the first embodiment.
FIG. 2 is a block diagram of a digital conversion apparatus in which a multilevel / binary conversion apparatus 7 for converting a multilevel signal into a binary signal and a binary decimation filter 6 are added. Here, the decimation is performed after converting the multi-value output into the binary output.

[0017]

The use of the multi-level quantization circuit using the resonant tunneling diode has an effect that the quantization circuit portion is greatly simplified as compared with the circuit according to the prior art (see FIG. 9). In addition, since the output of the multi-level quantization circuit is equivalent to the output after digital-to-analog conversion, the multi-bit digital-to-analog converter that was required by the conventional multi-bit delta-sigma analog-to-digital converter is unnecessary. become. Therefore, there is an effect that the circuit scale as a whole is reduced, and problems such as deterioration in accuracy and increase in delay time are improved.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a multi-bit delta-sigma analog-to-digital converter according to a first embodiment.

FIG. 2 is a circuit diagram of a multi-level quantization circuit portion of the multi-bit delta-sigma analog-to-digital converter according to the first embodiment.

FIG. 3 is a circuit block diagram of a band-bus delta-sigma analog-to-digital converter according to a third embodiment;

FIG. 4 is a circuit diagram of a band-pass filter of a band-pass delta-sigma analog-to-digital converter according to a third embodiment.

FIG. 5 is a circuit block diagram of a multi-bit delta-sigma analog-to-digital converter with multi-level decimation according to a fourth embodiment.

FIG. 6 is a circuit block diagram of a multi-level / binary converter and a multi-bit delta-sigma analog-to-digital converter with binary decimation according to a fifth embodiment.

FIG. 7 is a circuit block diagram of a conventional multi-bit delta-sigma analog-to-digital converter.

FIG. 7 is a specific circuit diagram of a quantization circuit used in a conventional multi-bit delta-sigma analog-to-digital converter.

FIGS. 8A and 8B show an example of a conventionally known multi-level quantization circuit using a resonant tunnel diode, (a) a circuit diagram, (b) a current-voltage characteristic illustrating a switching operation by a negative resistance characteristic in a tunnel diode, (C) A waveform diagram showing a clock voltage waveform, and (d) an operation explanatory diagram of a ternary quantization circuit.

FIG. 9 is a circuit diagram of a conventionally known binary quantization circuit.

FIG. 10 is a diagram showing a comparison of the circuit scale between a quantization circuit part in a multi-bit delta-sigma analog-to-digital converter according to the prior art and a multi-value quantization circuit using a resonant tunneling diode; a) In case of binary, (b) 3
In the case of values, (c) a comparison diagram in the case of four values.

[Explanation of symbols]

1: Multi-level quantization circuit 2: RC integrator 3: Subtractor 4: Adder 5: Multi-level decimation filter 6: Binary decimation filter 7: Multi-level / binary conversion device A, B, C, D: Resonance Tunnel diode

[Procedure amendment]

[Submission Date] December 13, 1999 (1999.12.
13)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a multi-bit delta-sigma analog-to-digital converter according to a first embodiment.

FIG. 2 is a circuit diagram of a multi-level quantization circuit portion of the multi-bit delta-sigma analog-to-digital converter according to the first embodiment.

FIG. 3 is a circuit block diagram of a bandpass delta sigma analog-to-digital converter according to a third embodiment;

FIG. 4 is a circuit diagram of a band-pass filter of a band-pass delta-sigma analog-to-digital converter according to a third embodiment.

FIG. 5 is a circuit block diagram of a multi-bit delta-sigma analog-to-digital converter with multi-level decimation according to a fourth embodiment.

FIG. 6 is a circuit block diagram of a multi-level / binary converter and a multi-bit delta-sigma analog-to-digital converter with binary decimation according to a fifth embodiment.

FIG. 7 is a circuit block diagram of a conventional multi-bit delta-sigma analog-to-digital converter.

FIGS. 8A and 8B show an example of a conventionally known multi-level quantization circuit using a resonant tunnel diode, (a) a circuit diagram, (b) a current-voltage characteristic illustrating a switching operation by a negative resistance characteristic in a tunnel diode, (C) A waveform diagram showing a clock voltage waveform, and (d) an operation explanatory diagram of a ternary quantization circuit.

FIG. 9 is a circuit diagram of a conventionally known binary quantization circuit.

FIG. 10 is a diagram showing a comparison of the circuit scale between a quantization circuit part in a multi-bit delta-sigma analog-to-digital converter according to the prior art and a multi-value quantization circuit using a resonant tunneling diode; a) In case of binary, (b) 3
In the case of values, (c) a comparison diagram in the case of four values.

[Description of Signs] 1: Multi-level quantization circuit 2: RC integrator 3: Subtractor 4: Adder 5: Multi-level decimation filter 6: Binary decimation filter 7: Multi-level / binary conversion device A, B, C, D: Resonant tunnel diode

Claims (2)

[Claims] 1. An analog-to-digital converter having a circuit for quantizing an analog input signal in a delta-sigma system, wherein said quantization circuit is a multi-level quantization circuit. An analog-to-digital converter, wherein an output is directly fed back to a circuit for subtracting the analog input signal. 2. A circuit corresponding to the multi-level quantization circuit according to claim 1, wherein n negative resistance elements A, B,... And n other negative resistance elements C, D,. Are connected in series, and n
A transistor is connected in parallel to the negative resistance elements C, D,..., And an input voltage is applied to an input terminal of the transistor.
An output is taken out from a connection point between the n negative resistance elements A, B,... And the n negative resistance elements C, D,.
An analog-to-digital converter using a circuit configured to output n + 1 types of voltage levels as types of signals.