JP2001168186A - Semiconductor integrated circuit device, method for separating element thereof and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for separating elements of a semiconductor integrated circuit device capable of miniaturizing non-volatile memory and high breakdown voltage transistor without degradation in the performance of the non-volatile memory and a transistor for a logic circuit, without losing an existing design concept of the transistor for the logic circuit, and without missing the manufacturing margin. SOLUTION: The elements are separated in a semiconductor integrated circuit device where plural kinds of semiconductor elements different in level of applied voltage are mixedly mounted. High breakdown voltage semiconductor elements with comparatively high voltage level are separated with each other by means of an oxide film formed without using thermal oxidation method and a thermal oxidation film formed to a predetermined depth on the oxide film. Low breakdown voltage semiconductors with comparatively low voltage level are separated with each other by means of the thermal oxidation film. A polysilicone film is buried, and the thermal oxidation film is disposed thereon to a predetermined depth. A predetermined voltage is applied to the polysilicone film, and the semiconductor elements are separated with each other by means of the thermal oxidation film and the polysilicone film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element isolation method for isolating elements mounted on a semiconductor integrated circuit device, and more particularly to an element to which a high voltage is applied such as a nonvolatile memory and a logic circuit. The present invention relates to an element isolation method for a semiconductor integrated circuit device in which an element to which a normal voltage is applied is mixed.

[0002]

2. Description of the Related Art Recent semiconductor integrated circuit devices include a CPU,
Rather than having functions of a logic circuit, a storage device, and the like each as a single unit, an SOC (System On Chip) that configures one system by mounting them on one chip has been developed.

[0003] As a storage device mounted on such a semiconductor integrated circuit, for example, a flash EEPROM which is non-volatile and easily integrated is used.

A flash EEPROM which is a nonvolatile semiconductor memory device capable of electrically writing / erasing information.
Are, for example, a plurality of cell transistors having a floating gate electrode and a control gate electrode in a memory cell portion for recording information, and a control transistor such as a high breakdown voltage transistor and a select transistor for controlling / selecting the cell transistor. Are known.

When writing or erasing information, a voltage of 10 V to
Since some devices apply a relatively high voltage of 20 V, such a structure requires a field oxide film formed in an element isolation region for isolating elements to have a thickness of 4000 to 5000 angstroms.

On the other hand, a transistor for a logic circuit used in a semiconductor integrated circuit device in recent years tends to have a lower breakdown voltage with miniaturization, and the power supply voltage has been reduced. Is 1000-2000
Angstrom (Power supply voltage is 2.5 to 5.0V)
Should be fine.

As described above, in a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixed, conventionally, a method of uniformly forming the thickness of a field oxide film even if the withstand voltage is different (hereinafter, referred to as a method). In order to make the field oxide film a film thickness suitable for each element, an oxide film of a predetermined thickness is formed only in a region where a high withstand voltage is required, and a logic circuit is formed. A method has been adopted in which a field oxide film in a region where a high withstand voltage is required is made thicker by further performing a thermal oxidation treatment together with a region to be formed (hereinafter, a second conventional example).

A procedure for manufacturing a semiconductor integrated circuit device according to the first conventional example and the second conventional example will be described. Hereinafter, a region where a nonvolatile memory is formed is referred to as a non-volatile memory region, a region where a transistor requiring high withstand voltage is formed is referred to as a high withstand voltage transistor region, and a region where a transistor for a logic circuit is formed is a logical region. It is called a circuit area.

First, a procedure for manufacturing a semiconductor integrated circuit device by the element isolation method of the first conventional example will be described with reference to FIG. FIG. 5 is a view showing the element isolation method of the semiconductor integrated circuit device of the first conventional example, and is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

In FIG. 5, in the first conventional example, first, S
A silicon oxide film (SiO ₂ ) 402 having a thickness of about 200 Å is formed on an i-substrate 401, and a silicon nitride film (S) having a thickness of about 1500 Å is formed thereon.
i ₃ N ₄ ) 403 is formed (FIG. 5A). Subsequently, the silicon nitride film 403 is formed using photolithography technology.
A photoresist 407 is formed thereon, and the photoresist 407 is patterned to form an element isolation region (FIG. 5B).

Next, the silicon nitride film 403 and the silicon oxide film 402 at the openings of the photoresist 407 are removed by plasma etching, and the vicinity of the surface of the Si substrate 401 is removed by etching to a thickness of about several hundred angstroms. (FIG. 5 (c)).

Subsequently, the photoresist 407 formed in the step shown in FIG. 5B is removed, and a field oxide film 408 made of a thermal oxide film is formed in the element isolation region by a thermal oxidation method (FIG. 5D). ). Here, the thermal oxide film is formed thicker (about 3000 Å) than the finally required film thickness (1000 to 2000 Å) in consideration of the reduction of the film thickness in a later step. Finally, the silicon nitride film 403 and the silicon oxide film 402 on the Si substrate 401 are respectively removed by the wet etching method (FIG. 5E), and each element of the nonvolatile memory area, the high breakdown voltage transistor area, and the logic circuit area is removed. A field oxide film 408 having the same thickness is formed in each of the isolation regions.

After the element isolation by the field oxide film 408 is completed, the tunneling oxide film 409 for the cell transistor and the floating gate electrode 41 are provided in the nonvolatile memory area.
ONO (Oxide Nitride Oxid) which is an insulating film for insulating the floating gate electrode 410 from the control gate electrode.
e) A film 411 is formed, a gate oxide film 413 of each transistor is formed in the high breakdown voltage transistor region and the logic circuit region, and a control gate electrode 412 of the cell transistor and a gate electrode 414 of the transistor are formed (FIG. f)). Thereafter, impurity diffusion layers (not shown) serving as a source and a drain of each transistor are respectively formed, and the process is continued to a wiring process.

In the first conventional example, since the thickness of the field oxide film 408 is uniformly formed in accordance with the element isolation performance of the logic circuit region, the region requiring a high withstand voltage (the nonvolatile memory region) , High breakdown voltage transistor region), the element isolation width (the width of the field oxide film 408) is increased in order to ensure element isolation performance.

Next, a procedure for manufacturing a semiconductor integrated circuit device by the element isolation method of the second conventional example will be described with reference to FIG. FIG. 6 is a diagram showing a device isolation method of a semiconductor integrated circuit device of a second conventional example, and is a sectional side view showing a manufacturing process of the semiconductor integrated circuit device.

In FIG. 6, in the second conventional example, first,
As in the conventional example, a silicon oxide film 502 having a thickness of about 200 Å is formed on a Si substrate 501, and a silicon nitride film 503 having a thickness of about 1500 Å is formed thereon (FIG. 6A). .

Next, a first photoresist 505 is formed on the silicon nitride film 503 by using a photolithography technique.
Is formed, and patterning of the first photoresist 505 is performed to form an element isolation region of the nonvolatile memory region and the high breakdown voltage transistor region (FIG. 6B).

Subsequently, the silicon nitride film 503 and the silicon oxide film 502 in the opening of the first photoresist 505 in the nonvolatile memory region and the high-breakdown-voltage transistor region are removed by a plasma etching method.
The vicinity of the surface of the substrate 501 is removed by etching with a thickness of about several hundred angstroms (FIG. 6C).

Subsequently, the first photoresist 505 formed in the step shown in FIG. 6B is removed, and several thousand thicknesses are formed in the nonvolatile memory region and the element isolation region of the high breakdown voltage transistor region by a thermal oxidation method. A first thermal oxide film 506 having a thickness of about Å is formed (FIG. 6D). Note that the thickness of the first thermal oxide film 506 formed at this time is 40 inclusive of the thickness of the second thermal oxide film formed in the subsequent thermal oxidation process.
It should be between 0.00 and 5000 angstroms.

Next, a second photoresist 507 is formed on the silicon nitride film 503 by using a photolithography technique.
Is formed, and the second photoresist 507 is patterned to form an element isolation region in a logic circuit region (FIG. 6E).

Subsequently, the silicon nitride film 503 and the silicon oxide film 502 in the openings of the second photoresist 507 in the logic circuit region are removed by plasma etching, and the vicinity of the surface of the Si substrate 501 is reduced to about several hundred angstroms. (FIG. 6)
(F)).

Subsequently, the second photoresist 507 formed in the step shown in FIG. 6E is removed, and a second thermal oxide film 508 (logic) having a thickness of about 3000 Å is formed in the element isolation region of the logic circuit region. The thermal oxidation process is performed so that a field oxide film of the circuit region is formed. At this time, the element isolation regions of the non-volatile memory region and the high-breakdown-voltage transistor region are also thermally oxidized at the same time.
6 is 3500 Å and the thickness of the second thermal oxide film 508 is 3000 Å, the rate of formation of the oxidized film becomes gradually slower. As a result, the first thermal oxide film 506 and the second A field oxide film of 4000 to 5000 angstroms including the thermal oxide film 508 is formed (FIG. 6G). Finally, the silicon nitride film 503 and the silicon oxide film 502 are respectively removed by a wet etching method (FIG. 6H).

Through the above steps, a field oxide film having a desired thickness consisting of the first thermal oxide film 506 and the second thermal oxide film 508 is formed in the non-volatile memory region and the high breakdown voltage transistor region. A second thermal oxide film 5 in the region
08 is formed.

After the element isolation by the field oxide film is completed, a tunneling oxide film 509, a floating gate electrode 510, and an ONO film 511 for a cell transistor are formed in the non-volatile memory area, respectively. Then, a gate oxide film 513 of each transistor is formed, and a control gate electrode 512 of the cell transistor and a gate electrode 514 of the transistor are formed (FIG. 6 (i)). Thereafter, impurity diffusion layers (not shown) serving as a source and a drain of each transistor are respectively formed, and the process is continued to a wiring process.

[0025]

Among the element isolation methods of the conventional semiconductor integrated circuit device as described above, the element isolation method of the first prior art uses the thickness of the field oxide film as described above in the logic circuit. If formed uniformly in accordance with the element isolation performance of the region, it is necessary to increase the element isolation width of the non-volatile memory region and the high withstand voltage transistor region. There is a problem that the degree of integration is reduced.

Conversely, if the field oxide film is uniformly thickened in accordance with the element isolation performance of the non-volatile memory region and the high breakdown voltage transistor region, the field oxide film is formed by bird's beak in the logic circuit region miniaturized by high integration. Are connected, so that a transistor cannot be formed. In this case, the element isolation width must be increased in order to enable formation of the transistor, so that the occupied area of the logic circuit region increases and the degree of integration decreases. Further, when expanding the element isolation layer, it is necessary to change the manufacturing process of the logic circuit from the existing process and reconstruct it, so that it is impossible to utilize the design resources so far. Further, the chip area also increases.

It is also conceivable to reduce the voltage applied to the non-volatile memory or the high-breakdown-voltage transistor to eliminate the need for high-breakdown-voltage performance, thereby making the field oxide film in the non-volatile memory region or the high-breakdown-voltage transistor region thinner. However, in this method, the time for writing and erasing information to and from the memory cell increases, so that the performance of the nonvolatile memory is inevitably deteriorated.

On the other hand, in the element isolation method of the second conventional example, 1
Since two underlayers are formed on one Si substrate, the misalignment of the exposure mask becomes large.
There is a problem that a manufacturing margin (alignment margin) at the time of forming a contact for connecting a wiring pattern and an electrode of a transistor becomes extremely small.

That is, according to the element isolation method of the first conventional example, the field oxide films of the nonvolatile memory region, the high breakdown voltage transistor region, and the logic circuit region can be formed at a time, and as shown in FIG. At the position 408, the floating gate electrode 410 of the memory cell, the control gate electrode 412, the gate electrode 414 of the transistor for the logic circuit, and the contact 416 are each formed within a uniform error. The arrows in the figure indicate errors in the formation position of each component due to misalignment. Therefore, the contact 416 and the floating gate electrode 410 of the memory cell, the control gate electrode 412, or the gate electrode 414 of the transistor for the logic circuit are not formed even with a normal manufacturing margin. The upper electrode 41 which is a wiring formed on the interlayer insulating film 415
7 and the contact 416 are also reliably connected.

However, according to the element isolation method of the second conventional example, as shown in FIG. 8, the position of a field oxide film (second thermal oxide film 508) in a nonvolatile memory region or a high breakdown voltage transistor region is logically adjusted. A field oxide film in a circuit region is formed with a predetermined positional error, and a gate electrode 514 and a contact 516 of a transistor for a logic circuit are formed with a predetermined positional error with respect to the field oxide film in the logical circuit region. You. Therefore, in a normal manufacturing margin, the floating gate electrode 510 or the control gate electrode 512 of the memory cell and the contact 516 may be formed so as to overlap with each other (the cross section in FIG. 8). Further, when the contacts in the two regions are separately formed in order to avoid the contact between the control gate electrode 512 and the contact 516, the interlayer insulating film 51 is formed.
There is a possibility that a connection failure between the upper electrode 517, which is a wiring formed on the wiring 5, and the contact 516 may occur, thereby increasing a product failure rate during manufacturing.

If the field oxide film is formed thick by the thermal oxidation method, the field oxide films are connected to each other by bird's beaks as described above. It is necessary to spread more. Therefore, the dimensions of cell transistors and high-voltage transistors are reduced, and next-generation semiconductor integrated circuit devices that require higher integration are required.
It is difficult to adopt such an element isolation method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and does not cause a decrease in the performance of a nonvolatile memory or a logic circuit transistor. It is an object of the present invention to provide an element isolation method of a semiconductor integrated circuit device capable of miniaturizing a nonvolatile memory and a high breakdown voltage transistor without deteriorating a manufacturing margin while maintaining the design method.

[0033]

In order to achieve the above object, the present invention provides an element isolation method for a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixed. An oxide film formed without using a thermal oxidation method and a predetermined thickness on and around the oxide film with a predetermined thickness using a thermal oxidation method. Separated by the formed thermal oxide film, the applied voltage is relatively low between the low breakdown voltage semiconductor elements,
This is a method of separating by the thermal oxide film.

At this time, the high withstand voltage semiconductor element may include a memory cell transistor of a flash EEPROM which is a nonvolatile memory.

Also, in the element isolation method of a semiconductor integrated circuit device for isolating semiconductor elements with a predetermined dielectric strength, a polysilicon film serving as an electrode is buried in advance, and Is provided with an isolation trench in which a thermal oxide film of a predetermined thickness is formed by using a thermal oxidation method, a predetermined voltage is applied to the polysilicon film, and the thermal oxide film and the This is a method of separating with a polysilicon film.

At this time, the semiconductor element may be a high withstand voltage semiconductor element to which a relatively high applied voltage is applied.
It may include a PROM memory cell transistor.

On the other hand, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixedly mounted, and a high withstand voltage semiconductor element having a relatively high applied voltage is mounted. The applied voltage is compared with an isolation trench formed at a predetermined depth in an element isolation region of the region, and an oxide film formed without using a thermal oxidation method in the isolation trench and embedded with a predetermined thickness. And a thermal oxide film formed on the oxide film and around the oxide film at a predetermined thickness using a thermal oxidation method. .

At this time, the high breakdown voltage semiconductor element may include a memory cell transistor of a flash EEPROM which is a nonvolatile memory.

A semiconductor integrated circuit device having an element isolation region for isolating between semiconductor elements with a predetermined withstand voltage, comprising: an isolation trench formed at a predetermined depth in the element isolation region; A polysilicon film which is an electrode embedded in the isolation trench with a predetermined thickness, and a thermal oxide film formed with a predetermined thickness on the polysilicon film by using a thermal oxidation method. Configuration.

At this time, the semiconductor element may be a high withstand voltage semiconductor element to which a relatively high applied voltage is applied, and the high withstand voltage semiconductor element may include a flash EE which is a nonvolatile memory.
It may include a PROM memory cell transistor.

Further, the method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixedly mounted. An isolation trench having a predetermined depth is formed in an element isolation region where a semiconductor element is mounted, and an oxide film formed without using a thermal oxidation method is buried in the isolation trench, and the applied voltage is relatively low. A method in which a thermal oxide film having a predetermined thickness is formed by using a thermal oxidation method around an element isolation region where a breakdown voltage semiconductor element is mounted and the isolation trench, and a plurality of types of semiconductors having different applied voltages. A method of manufacturing a semiconductor integrated circuit device in which elements are mixed, wherein an isolation trench having a predetermined depth is formed in an element isolation region where a high withstand voltage semiconductor element having a relatively high applied voltage is mounted. An oxide film formed without using a thermal oxidation method is buried in the isolation trench to a predetermined thickness, and an element isolation region of a region where a low withstand voltage semiconductor element having a relatively low applied voltage is mounted and the oxide film. In this method, a thermal oxide film having a predetermined thickness is formed on and around the upper surface by using a thermal oxidation method.

At this time, the high withstand voltage semiconductor element may include a memory cell transistor of a flash EEPROM which is a nonvolatile memory.

Also, a method of manufacturing a semiconductor integrated circuit device having an element isolation region for isolating semiconductor elements with a predetermined dielectric strength voltage, wherein an isolation trench having a predetermined depth is formed in the element isolation region. Forming a polysilicon film in the isolation trench, leaving a polysilicon film of a predetermined thickness in the isolation trench, and thermally oxidizing the polysilicon film on the polysilicon film by a thermal oxidation method. This is a method of forming a film.

At this time, the semiconductor element may be a high withstand voltage semiconductor element to which a relatively high applied voltage is applied, and the high withstand voltage semiconductor element may include a flash EE which is a nonvolatile memory.
It may include a PROM memory cell transistor.

In the element isolation method for a semiconductor integrated circuit device as described above, an oxide film formed without using a thermal oxidation method between a high withstand voltage semiconductor element having a relatively high applied voltage and a predetermined thickness on the oxide film. By separating the low-breakdown-voltage semiconductor elements to which the applied voltage is relatively low by the thermal oxide film, the isolation performance of the element isolation region of the high-breakdown-voltage semiconductor element can be maintained. . In particular, since the thickness of the thermal oxide film formed by the thermal oxidation method can be made the same as that of the low-breakdown-voltage semiconductor element, the size of the bird's beak can be suppressed to the same level as that of the low-breakdown-voltage semiconductor element. Can be made equivalent to a low breakdown voltage semiconductor element.

Further, since the thermal oxide film in the element isolation region of the low breakdown voltage semiconductor element can be made to have an existing thickness, an increase in the chip area due to a change in the element isolation step or an increase in the element isolation width can be prevented. .

Further, since the positions of the plurality of element isolation regions are determined by the same thermal oxidation treatment as the patterning using the same exposure mask, the misalignment of the exposure mask due to the increase in the number of bases does not increase.

On the other hand, an isolation trench in which a polysilicon film serving as an electrode is buried and a thermal oxide film having a predetermined thickness is formed on the polysilicon film is provided, and a predetermined voltage is applied to the polysilicon film. By separating the semiconductor elements with the thermal oxide film and the polysilicon film, the isolation breakdown voltage between the semiconductor elements can be significantly increased as compared with the case where only the oxide film is provided.

[0049]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(First Embodiment) First, a first embodiment of an element isolation method for a semiconductor integrated circuit device according to the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a first embodiment of the element isolation method of a semiconductor integrated circuit device according to the present invention, and is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

As shown in FIG. 1, in the first embodiment, a silicon oxide film 2 (SiO ₂ ) having a thickness of about 200 angstroms is formed on a Si substrate 1 as in the prior art. A silicon nitride film 3 (Si ₃ N ₄ ) having a thickness of about 1500 Å is formed thereon. Subsequently, a photoresist (not shown) is formed on the silicon nitride film 3 using a photolithography technique, and the photoresist is patterned to form a later-described isolation trench in a nonvolatile memory region and a high breakdown voltage transistor region.

Then, the silicon nitride film 3 and the silicon oxide film 2 in the photoresist openings in the nonvolatile memory region and the high breakdown voltage transistor region are formed by the plasma etching method.
Are removed, and the Si substrate 1 is etched to form an isolation trench 4 having a depth of about 5,000 angstroms in the element isolation region of the nonvolatile memory region and the high breakdown voltage transistor region, and formed on the silicon nitride film 3. The photoresist is removed (FIG. 1A).

Next, the bottom surface and the inner wall side surface of the isolation trench 4 are respectively thermally oxidized to form an inner wall thermal oxide film 4a having a thickness of 200 to 300 angstroms, and the Si substrate 1 is formed by plasma CVD (Chemical Vapor Deposition). A plasma oxide film 5 is deposited thereon so that the plasma oxide film 5 is embedded in the isolation trench 4 (FIG. 1).
(B)). Note that the oxide film embedded in the isolation trench 4 does not necessarily need to be formed by the plasma CVD method.
For example, it may be formed by a CVD method.

Subsequently, the plasma oxide film 5 deposited on the silicon nitride film 3 is removed by a plasma etching method, so that the patterned silicon nitride film 3 is exposed. Further, of the plasma oxide film 5 embedded in the isolation trench 4 by the wet etching method,
About 000 angstroms are removed by etching (FIG. 1C). At this time, wet etching is performed so that the level difference between the plasma oxide film 5 left in the isolation trench 4 and the surface of the Si substrate 1 is smaller than the amount of the thermal oxide film 8 formed in the subsequent process biting into the Si substrate 1. Adjust the time to do.

Next, a polysilicon film 6 is deposited on the Si substrate 1 by the CVD method, and the polysilicon film 6 is buried in the isolation trench 4 (FIG. 1D). Further, while leaving the polysilicon film 6 in the isolation trench 4,
Etch back so that the silicon nitride film 3 is exposed (FIG. 1E).

Subsequently, a photoresist 7 is formed on the silicon nitride film 3 by using a photolithography technique, and a photo-resist 7 is formed to form a non-volatile memory region, a high breakdown voltage transistor region, and an element isolation region of a logic circuit region. The resist 7 is patterned. In the nonvolatile memory region and the high breakdown voltage transistor region, the opening of the photoresist 7 is patterned so as to be about 0.1 μm larger than the outer periphery of the opening of the isolation trench 4 (FIG. 1F). Further, the silicon nitride film 3 and the silicon oxide film 2 in the opening of the photoresist 7 are removed respectively,
The vicinity of the surface of the polysilicon film 6 embedded in the i-substrate 1 and the isolation trench 4 is removed by etching to a thickness of several hundred angstroms (FIG. 1 (g)).

Next, the photoresist 7 on the silicon nitride film 3 is removed, and the Si substrate 1 and the polysilicon film 6 at the openings of the silicon nitride film 3 are oxidized by a thermal oxidation method, respectively. An oxide film 8 is formed (FIG. 1H). At this time, the polysilicon film is not left in the isolation trench 4. Finally, the silicon nitride film 3 and the silicon oxide film 2 on the Si substrate 1 are removed by wet etching (FIG. 1 (i)).

Through the above steps, a field oxide film having a desired thickness comprising the plasma oxide film 5 and the thermal oxide film 8 embedded in the isolation trench 4 is formed in the nonvolatile memory region and the high breakdown voltage transistor region. A field oxide film composed of a thermal oxide film 8 is formed in the logic circuit region.

After the element isolation by the field oxide film is completed, the tunneling oxide film 9 for the cell transistor, the floating gate electrode 10, and the ONO
A film 11 is formed, a gate oxide film 13 of each transistor is formed in the high breakdown voltage transistor region and the logic circuit region, and a control gate electrode 12 of the cell transistor is formed.
And a gate electrode 14 of the transistor (FIG. 1)
(J)). Thereafter, impurity diffusion layers (not shown) serving as a source and a drain of each transistor are respectively formed, and the process is continued to a wiring process.

Therefore, by manufacturing the semiconductor integrated circuit device according to the steps of the present embodiment, it is possible to form element isolation regions each having a desired thickness in the nonvolatile memory region and the high breakdown voltage transistor region. Therefore, element isolation performance can be maintained even in a region where high withstand voltage is required. In particular, since the thickness of the oxide film formed by the thermal oxidation process in the nonvolatile memory region and the high breakdown voltage transistor region can be made the same as that of the logic circuit region, the size of the bird's beak is suppressed to be equal to that of the logic circuit region. It is possible to make the element isolation width equal to the logic circuit area. That is, miniaturization of the nonvolatile memory and the high breakdown voltage transistor becomes possible.

Further, since the oxide film in the element isolation region of the transistor for the logic circuit can be made to have an existing thickness,
An increase in the chip area due to a change in the element isolation step or an increase in the element isolation width is prevented.

Further, the positions of the element isolation regions in the nonvolatile memory region, the high breakdown voltage transistor region, and the logic circuit region are determined by the same thermal oxidation and patterning with the same exposure mask. The increase in misalignment of the mask for use is eliminated, and a decrease in the manufacturing margin is prevented.

(Second Embodiment) When a flash EEPROM as a nonvolatile memory is mounted in a semiconductor integrated circuit device, as shown in the first embodiment, a floating gate electrode of a cell transistor and an impurity It is desirable to provide a thermal oxide film formed by thermal oxidation in the element isolation region in contact with the diffusion layer. This is because the thermal oxide film formed by the thermal oxidation process has a denser composition than the plasma oxide film formed by the plasma CVD, and prevents the leakage of the electrons accumulated in the floating gate electrode more reliably. This is because it is possible to prevent a decrease in information retention performance.

However, when only a high-voltage transistor and a logic circuit are mounted on a semiconductor integrated circuit device, or when the reliability of the nonvolatile memory is not so important, as in the first embodiment, It is not necessary to form the element isolation region of the region and the high breakdown voltage transistor region with two types of oxide films by different manufacturing methods.

In the present embodiment, a method for element isolation of a semiconductor integrated circuit device in such a case will be described with reference to FIG. FIG. 2 is a diagram showing a second embodiment of the element isolation method for a semiconductor integrated circuit device according to the present invention, and is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

As shown in FIG. 2, the device isolation method according to the second embodiment first employs the same method as in the first embodiment.
A silicon oxide film 102 having a thickness of about 200 angstroms is formed on a substrate 101, and a silicon nitride film 103 having a thickness of about 1500 angstroms is formed thereon.
Subsequently, a photoresist (not shown) is formed on the silicon nitride film 103 using a photolithography technique, and the photoresist is patterned in order to form a later-described isolation trench in a nonvolatile memory region and a high breakdown voltage transistor region.

Subsequently, the silicon nitride film 103 and the silicon oxide film 102 at the photoresist openings in the non-volatile memory region and the high-breakdown-voltage transistor region are removed by a plasma etching method. An isolation trench 104 having a depth of about 5000 angstroms is formed in the element isolation region of the memory region and the high breakdown voltage transistor region, and the photoresist formed on the silicon nitride film 103 is removed (FIG. 2).
(A)).

Next, the bottom surface and the inner wall side surface of the isolation trench 104 are each thermally oxidized to form an inner wall thermal oxide film 104a having a thickness of 200 to 300 angstroms.
A plasma oxide film 105 is deposited on the Si substrate 101 by a plasma CVD method so that the plasma oxide film 105 is embedded in the isolation trench 104 (FIG. 2).
(B)). The oxide film embedded in the isolation trench 104 does not necessarily need to be formed by plasma CVD, and may be formed by, for example, a CVD method.

Subsequently, the plasma oxide film 105 deposited on the silicon nitride film 103 is dry-etched, wet-etched, or CMP (Chemical Mechanical).
CalPolishing) and wet etching are used to expose the patterned silicon nitride film 103.

Next, a photoresist 107 is formed on the silicon nitride film 103 by using a photolithography technique, and the photoresist 107 is formed in order to form a non-volatile memory region, a high breakdown voltage transistor region, and an element isolation region of a logic circuit region. Patterning 107 is performed. In the nonvolatile memory region and the high breakdown voltage transistor region, the opening of the photoresist 107 is patterned so as to be larger than the outer periphery of the opening of the isolation trench 104 by about 0.1 μm (FIG. 2D).

Subsequently, the silicon nitride film 103 and the silicon oxide film 102 at the opening of the photoresist 107 are removed, respectively, and the vicinity of the surface of the Si substrate 101 and the plasma oxide film 105 buried in the isolation trench 104 is expressed by Formula 1
Etching is removed to a thickness of 00 angstroms (FIG. 2 (e)).
7 is removed and the Si substrate 10 in the opening of the silicon nitride film 103 is formed by thermal oxidation so that a thermal oxide film 108 having a thickness of about 3000 Å is formed in the logic circuit region.
1 is oxidized (FIG. 2 (f)). At this time, in the nonvolatile memory region and the high breakdown voltage transistor region, the thermal oxide film 10 is formed around the opening of the isolation trench 104 as shown in FIG.
8 are formed. Finally, the silicon nitride film 103 and the silicon oxide film 2 on the Si substrate 101 are removed by wet etching (FIG. 2G).

Through the above steps, a field of a desired thickness comprising the plasma oxide film 105 buried in the isolation trench 104 and the thermal oxide film 108 formed around the opening in the nonvolatile memory region and the high breakdown voltage transistor region. An oxide film is formed, and a thermal oxide film 108 is formed in the logic circuit region.
Is formed.

After the element isolation by the field oxide film is completed, a tunneling oxide film 109 for cell transistors, a floating gate electrode 110, and an ONO film 111 are formed in the non-volatile memory region, respectively. Then, a gate oxide film 113 of each transistor is formed, and a control gate electrode 112 of the cell transistor and a gate electrode 114 of the transistor are formed (FIG. 2 (h)). Thereafter, impurity diffusion layers (not shown) serving as a source and a drain of each transistor are respectively formed, and the process is continued to a wiring process.

Therefore, by forming the semiconductor integrated circuit device according to the process of the present embodiment, similarly to the first embodiment, the non-volatile memory region and the high-breakdown-voltage transistor region are each formed of an oxide film having a desired thickness. Therefore, the element isolation performance can be maintained even in a region where a high withstand voltage is required.

When a logic circuit is mixedly mounted, the oxide film in the element isolation region of the transistor for the logic circuit can be made to have an existing thickness, so that the element isolation process is changed and the element isolation width is increased. This prevents the chip area from increasing.

Further, the positions of the element isolation regions in the nonvolatile memory region, the high breakdown voltage transistor region, and the logic circuit region are determined by patterning using the same exposure mask and the same thermal oxidation process. The increase in misalignment of the mask for use is eliminated, and a decrease in the manufacturing margin is prevented.

In the manufacturing method shown in FIG. 2, an isolation trench is first formed in the non-volatile memory area and the high breakdown voltage transistor area, and then a thermal oxide film is formed by a thermal oxidation method to form an element isolation area. However, as shown in FIG. 3, a thermal oxide film may be formed first, and then an isolation trench may be formed.

Hereinafter, a modification of this embodiment will be described with reference to FIG.

FIG. 3 is a diagram showing a modification of the second embodiment of the element isolation method for a semiconductor integrated circuit device according to the present invention.
FIG. 4 is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

Referring to FIG. 3, first, a first silicon oxide film 202 having a thickness of about 200 angstroms is formed on a Si substrate 201, and a first silicon nitride film 203 having a thickness of about 1500 angstroms is formed thereon. The film is formed (FIG. 3A). Subsequently, the first photoresist 20 is formed on the silicon nitride film 203 by using a photolithography technique.
7 is formed, and the first photoresist 207 is patterned to form a non-volatile memory region, a high breakdown voltage transistor region, and an element isolation region of a logic circuit region (FIG. 3B).

Next, the first silicon nitride film 2 at the opening of the first photoresist 207 is formed by plasma etching.
03 and the first silicon oxide film 202 are respectively removed, and the vicinity of the surface of the Si substrate 201 is further removed by etching to a thickness of about several hundred angstroms (FIG. 3).
(C)).

Subsequently, the first photoresist 207 on the first silicon nitride film 203 is removed, and a thermal oxide film 208 is formed in each element isolation region by a thermal oxidation method (FIG. 3).
(D)). Here, the thermal oxide film 208 is formed to be thicker (about 3000 Å) than the finally required film thickness (1000 to 2000 Å) in consideration of the decrease in film thickness in a later step.

Next, after the first silicon nitride film 203 and the first silicon oxide film 202 on the Si substrate 201 are removed by wet etching (FIG.
(E)), a second silicon oxide film 216 having a thickness of about 200 angstroms and a second silicon nitride film 217 having a thickness of about 1500 angstroms are formed again (FIG. 3F).

Subsequently, a second photoresist 215 is formed on the second silicon nitride film 217 by using the photolithography technique, and an isolation trench described later is formed in the nonvolatile memory region and the high breakdown voltage transistor region. The second photoresist 215 is patterned (FIG. 3G).

Subsequently, the second silicon nitride film 21 in the opening of the second photoresist 215 in the nonvolatile memory region and the high breakdown voltage transistor region is formed by the plasma etching method.
7 and the second silicon oxide film 216 are respectively removed,
Further, the Si substrate 201 is etched to form an isolation trench 204 having a depth of about 5,000 angstroms in the element isolation region of the nonvolatile memory region and the high breakdown voltage transistor region.
(FIG. 3H), and a second silicon nitride film 217 is formed.
The second photoresist 215 formed thereon is removed (FIG. 3I).

Next, the bottom surface and the inner wall side surface of the isolation trench 204 are each thermally oxidized to form an inner wall thermal oxide film 204a having a thickness of 200 to 300 angstroms.
A plasma oxide film 205 is deposited on the Si substrate 201 by a plasma CVD method so that the plasma oxide film 205 is embedded in the isolation trench 204 (FIG. 3).
(J)). The oxide film embedded in the isolation trench 204 does not necessarily need to be formed by plasma CVD, and may be formed by, for example, a CVD method.

Subsequently, the plasma oxide film 205 deposited on the second silicon nitride film 217 is flattened by a dry etching method and a wet etching method, or a CMP method and a wet etching method, and the patterned second silicon nitride film 217 is formed. The film 217 is exposed (FIG. 3
(K)). Finally, the second silicon nitride film 217 and the second silicon oxide film 216 on the Si substrate 201 are removed by wet etching (FIG. 3).
(L)).

Through the above steps, a field of a desired thickness comprising the plasma oxide film 205 buried in the isolation trench 204 and the thermal oxide film 208 formed around the opening in the nonvolatile memory region and the high breakdown voltage transistor region. An oxide film is formed, and a thermal oxide film 208 is formed in the logic circuit region.
Is formed.

After the element isolation by the field oxide film is completed, a tunneling oxide film 209 for a cell transistor, a floating gate electrode 210, and an ONO film 211 are formed in the non-volatile memory area, respectively. Then, a gate oxide film 213 of each transistor is formed, and a control gate electrode 212 of the cell transistor and a gate electrode 214 of the transistor are formed (FIG. 3 (m)). Thereafter, impurity diffusion layers (not shown) serving as a source and a drain of each transistor are respectively formed, and the process is continued to a wiring process.

(Third Embodiment) Next, a third embodiment of the element isolation method for a semiconductor integrated circuit device according to the present invention will be described with reference to FIG. FIG. 4 is a diagram showing a third embodiment of the element isolation method for a semiconductor integrated circuit device according to the present invention, and is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

The element isolation method of the semiconductor integrated circuit device according to the present embodiment is a method suitable for use in element isolation of a non-volatile memory area and a high-voltage transistor area which require a high breakdown voltage, and is provided in the element isolation area. In this method, a polysilicon film serving as an electrode is buried in an isolation trench, and a predetermined potential is applied to the polysilicon film to improve element isolation performance. Note that the element isolation method of this embodiment may be used in a logic circuit region to which a normal power supply voltage is applied.

Referring to FIG. 4, in the third embodiment, first, a silicon oxide film (SiO ₂ ) 302 having a thickness of about 200 Å is formed on a Si substrate 301, and a photolithography technique is used thereon. A first photoresist 307 is formed, and the first photoresist 307 is patterned to form a later-described isolation trench in the nonvolatile memory region and the high breakdown voltage transistor region. Subsequently, the silicon oxide film 302 at the opening of the first photoresist 307 is removed by a plasma etching method, and the Si substrate 301 is etched to a depth of 500 in the nonvolatile memory region and the high breakdown voltage transistor region.
An isolation trench 304 of about 0 Å is formed (FIG. 4A).

Next, the first photoresist 307 is removed, and an inner wall thermal oxide film 304a having a thickness of 200 to 300 Å is formed on the bottom surface and the inner wall side surface of the isolation trench 304 by thermal oxidation (FIG. 4B). )). Furthermore, CV
A polysilicon film 306 is deposited on the Si substrate 301 by the method D, and the polysilicon film 30 is
6 is embedded (FIG. 4C). Subsequently, while leaving the polysilicon film 306 in the isolation trench 304,
Etchback is performed so that the silicon oxide film 302 is exposed (FIG. 4D).

Next, a silicon oxide film 302 is further formed so as to cover the polysilicon film 306 buried in the isolation trench 304, and the silicon nitride film 30 is formed thereon.
3 is formed (FIG. 4E).

Subsequently, the second photoresist 31 is formed on the silicon nitride film 303 by using the photolithography technique.
5 is formed, and patterning of the second photoresist 315 is performed to form element isolation regions of the nonvolatile memory region and the high breakdown voltage transistor region. At this time, a contact formation site (hereinafter, a region including the contact formation site) for connecting the polysilicon film 306 buried in the isolation trench 304 and the upper wiring formed on the interlayer insulating film in a later step is formed. The contact region is also covered with the second photoresist 315. In the nonvolatile memory region and the high breakdown voltage transistor region, the opening of the second photoresist 315 is patterned so as to be larger than the outer periphery of the opening of the isolation trench 304 by about 0.1 μm (FIG. 4F). .

Next, the silicon nitride film 303 and the silicon oxide film 302 at the opening of the second photoresist 315 are removed, and the vicinity of the surface of the polysilicon film 306 buried in the isolation trench 304 is several hundred angstroms. (FIG. 4)
(G)).

Subsequently, the second photoresist 315 is removed, and the S at the opening of the silicon nitride film 303 is removed by thermal oxidation.
The i-substrate 301 and the polysilicon film 306 are each thermally oxidized to form a thermal oxide film 308 having a thickness of about 3000 Å (FIG. 4H). Further, the silicon nitride film 3 on the Si substrate 301 is wet-etched.
03 and the silicon oxide film 302 are respectively removed (FIG. 4I).

Through the above steps, the isolation trench 304 is formed in the nonvolatile memory region or the high breakdown voltage transistor region.
Polysilicon film 306 and thermal oxide film 3 embedded inside
08 is formed.

After the element isolation by the field oxide film is completed, a tunneling oxide film 309 for the cell transistor, a floating gate electrode 310, and an ONO film 311 are formed in the nonvolatile memory area, respectively, and the high breakdown voltage transistor area and the logic circuit area are formed. Then, a gate oxide film 313 of each transistor is formed, and a control gate electrode 312 of the cell transistor and a gate electrode 314 of the transistor are formed (FIG. 4 (j)).

Subsequently, an impurity diffusion layer 319 serving as a source and a drain of each transistor is formed, and an interlayer insulating film 316 is formed so as to cover them, and the impurity diffusion layer 319 or the isolation trench 304 of each transistor is formed. A contact 317 for communicating the surface of the polysilicon film 306 buried with the surface of the interlayer insulating film 316 is formed, and finally, an upper electrode 318 is formed (FIG. 4).
(K)).

Although FIG. 4 shows only the procedure for manufacturing the nonvolatile memory region and the contact region where the contact is formed, the high breakdown voltage transistor region can be formed in the same manner as the nonvolatile memory region.

FIG. 4 shows an example in which the thermal oxide film 308 is formed on the polysilicon film 306. However, the thermal oxide film is not limited to the thermal oxide film. Plasma oxide film).

As in this embodiment, a polysilicon film 306 is buried in an isolation trench 304 provided in an element isolation region, and a ground potential or a negative voltage is applied to the polysilicon film 306 as an electrode (P well). In the case where an N-channel transistor with a high breakdown voltage is formed therein), the isolation breakdown voltage between the elements can be significantly increased as compared with the case where only an oxide film is provided. When a high-breakdown-voltage P-channel transistor is formed in the N-well, a positive voltage may be applied to the polysilicon film 306 embedded in the isolation trench 304.

In general, in a method of obtaining a desired isolation breakdown voltage by the thickness of an oxide film formed in an element isolation region, it is necessary to deepen an isolation trench as a voltage applied to a semiconductor element increases. Since the opening width of the isolation trench is determined by the burying property of the oxide film and increases in proportion to the depth of the isolation trench, the isolation width must be increased in order to increase the isolation withstand voltage. Decrease.

As in the present embodiment, the isolation trench 304
In the structure in which the polysilicon film 306 is embedded in the inside, the polysilicon film 30
A desired separation withstand voltage can be obtained only by adjusting the voltage applied to 6.

Therefore, even if the oxide film formed in the element isolation region is made thinner, a predetermined element isolation performance can be obtained. Therefore, the thickness of the thermal oxide film in the nonvolatile memory region and the element isolation region in the high breakdown voltage transistor region can be improved. Can be the same as the logic circuit area.

Therefore, as in the first embodiment, the size of the bird's beak can be suppressed to be equal to that of the logic circuit area, and the element isolation width can be equal to that of the logic circuit area. That is, miniaturization of the nonvolatile memory and the high breakdown voltage transistor becomes possible.

Further, when a logic circuit is mixedly mounted, the oxide film in the element isolation region of the transistor for the logic circuit can be made to have an existing thickness, so that the element isolation step is changed and the element isolation width is increased. This prevents the chip area from increasing.

Furthermore, the positions of the element isolation regions in the nonvolatile memory region, the high breakdown voltage transistor region, and the logic circuit region are determined by the same thermal oxidation and patterning with the same exposure mask. The increase in misalignment of the mask for use is eliminated, and a decrease in the manufacturing margin is prevented.

[0110]

Since the present invention is configured as described above, the following effects can be obtained.

A high voltage semiconductor element having a relatively high applied voltage is separated by an oxide film formed without using a thermal oxidation method and a thermal oxide film formed on the oxide film with a predetermined thickness. By isolating the low-breakdown-voltage semiconductor elements having a relatively low breakdown voltage using a thermal oxide film, the isolation performance of the element isolation region of the high-breakdown-voltage semiconductor element can be maintained. In particular, since the thickness of the thermal oxide film formed by the thermal oxidation method can be made the same as that of the low-breakdown-voltage semiconductor element, the size of the bird's beak can be suppressed to the same level as that of the low-breakdown-voltage semiconductor element. Can be made equivalent to a low breakdown voltage semiconductor element.

Since the thermal oxide film in the element isolation region of the low-breakdown-voltage semiconductor element can be made to have an existing thickness, an increase in the chip area due to a change in the element isolation step and an increase in the element isolation width can be prevented. .

Further, since the position of each element isolation region is determined by the same thermal oxidation treatment as the patterning with the same exposure mask, the misalignment of the exposure mask due to the increase in the number of bases does not increase, and the manufacturing margin decreases. Is prevented.

On the other hand, an isolation trench in which a polysilicon film to be an electrode is buried and a thermal oxide film having a predetermined thickness is formed on the polysilicon film is provided, and a predetermined voltage is applied to the polysilicon film. By separating the semiconductor elements with the thermal oxide film and the polysilicon film, the isolation breakdown voltage between the semiconductor elements can be significantly increased as compared with the case where only the oxide film is provided. Therefore, a predetermined element isolation performance can be obtained even when the oxide film formed in the element isolation region is made thin.

[Brief description of the drawings]

FIG. 1 is a view showing a first embodiment of an element isolation method for a semiconductor integrated circuit device according to the present invention, and is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

FIG. 2 is a diagram showing a second embodiment of the element isolation method of the semiconductor integrated circuit device according to the present invention, and is a cross-sectional side view showing a manufacturing process of the semiconductor integrated circuit device.

FIG. 3 is a view showing a modification of the second embodiment of the element isolation method of the semiconductor integrated circuit device according to the present invention, and is a side sectional view showing a manufacturing process of the semiconductor integrated circuit device.

FIG. 4 is a view showing a third embodiment of the element isolation method of the semiconductor integrated circuit device according to the present invention, and is a cross-sectional side view showing a manufacturing process of the semiconductor integrated circuit device.

FIG. 5 is a side sectional view showing a method of isolating a semiconductor integrated circuit device according to a first conventional example, showing a manufacturing process of the semiconductor integrated circuit device;

FIG. 6 is a side sectional view showing a method of isolating a semiconductor integrated circuit device according to a second conventional example, showing a manufacturing process of the semiconductor integrated circuit device.

FIG. 7 is a diagram illustrating a problem of the element isolation method of the semiconductor integrated circuit of the conventional example, and is an enlarged side sectional view of a main part of the semiconductor integrated circuit device of the first conventional example.

FIG. 8 is a diagram illustrating a problem of the element isolation method of the semiconductor integrated circuit of the conventional example, and is an enlarged side sectional view of a main part of the semiconductor integrated circuit device of the second conventional example.

[Explanation of symbols]

 1, 101, 201, 301 Si substrate 2, 102, 302 Silicon oxide film 3, 103, 303 Silicon nitride film 4, 104, 204, 304 Isolation trench 5, 105, 205 Plasma oxide film 6, 306 Polysilicon film 7, 107 Photoresist 8, 108, 208, 308 Thermal oxide film 9, 109, 209, 309 Tunneling oxide film 10, 110, 210, 310 Floating gate electrode 11, 111, 211, 311 ONO film 12, 112, 212, 312 Control Gate electrode 13, 113, 213 Gate oxide film 14, 114, 214 Gate electrode 202 First silicon oxide film 203 First silicon oxide film 207, 307 First photoresist 215, 315 Second photoresist 216 Second Silicon oxide film 217 second silicon Oxide film 316 interlayer insulating film 317 contact 318 upper electrode 319 impurity diffusion layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8247 29/788 29/792 F term (Reference) 5F001 AA25 AA43 AB02 AC01 AD60 AD62 AE08 AG02 5F032 AA13 AA34 AA44 AA45 AA47 AA63 AA70 AA75 BA01 BA02 BA03 BB01 CA23 CA24 CA25 DA02 DA04 DA23 DA24 DA33 DA34 DA53 DA78 5F038 DF04 DF05 EZ16 5F083 EP02 EP22 EP55 EP56 ER22 GA01 GA09 GA24 GA27 GA30 JA04 JA32 NA03 PR01 Z03 PR03 BA07 BA28 BB02 BC01 BD35 BD37 BE07 BH03

Claims (16)

[Claims] 1. An element isolation method for a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixedly mounted, wherein a high-voltage semiconductor element having a relatively high applied voltage is separated without using a thermal oxidation method. Between the low-breakdown-voltage semiconductor element having a relatively low applied voltage and a thermal oxide film formed on the oxide film at a predetermined thickness on and around the oxide film using a thermal oxidation method. Is separated by the thermal oxide film. 2. The element isolation method for a semiconductor integrated circuit device according to claim 1, wherein said high breakdown voltage semiconductor element includes a memory cell transistor of a flash EEPROM as a nonvolatile memory. Method. 3. An element isolation method for a semiconductor integrated circuit device for isolating semiconductor elements with a predetermined dielectric strength voltage, wherein a polysilicon film serving as an electrode is embedded in advance, and An isolation trench in which a thermal oxide film having a predetermined thickness is formed by using a thermal oxidation method, a predetermined voltage is applied to the polysilicon film, and the thermal oxide film is formed between the semiconductor elements. An element isolation method for a semiconductor integrated circuit device, which is separated by a polysilicon film. 4. The element isolation method for a semiconductor integrated circuit device according to claim 3, wherein the semiconductor element is a high breakdown voltage semiconductor element to which a relatively high applied voltage is applied. 5. The element isolation method for a semiconductor integrated circuit device according to claim 4, wherein said high breakdown voltage semiconductor element includes a memory cell transistor of a flash EEPROM as a nonvolatile memory. Method. 6. A semiconductor integrated circuit device on which a plurality of types of semiconductor elements having different applied voltages are mixedly mounted, wherein a predetermined depth is formed in an element isolation region of a region where a high breakdown voltage semiconductor element having a relatively high applied voltage is mounted. An oxide film formed in the isolation trench without using a thermal oxidation method and embedded with a predetermined thickness, and a low-breakdown-voltage semiconductor element to which the applied voltage is relatively low is mounted. On and around the element isolation region and the oxide film,
A semiconductor integrated circuit device having a thermal oxide film formed to a predetermined thickness by a thermal oxidation method. 7. The semiconductor integrated circuit device according to claim 6, wherein said high breakdown voltage semiconductor element includes a memory cell transistor of a flash EEPROM which is a nonvolatile memory. 8. A semiconductor integrated circuit device having an element isolation region for isolating semiconductor elements with a predetermined withstand voltage, comprising: an isolation trench formed at a predetermined depth in the element isolation region; A polysilicon film, which is an electrode, embedded in the isolation trench at a predetermined thickness, and a thermal oxide film formed at a predetermined thickness on the polysilicon film by using a thermal oxidation method. Semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 8, wherein said semiconductor element is a high withstand voltage semiconductor element to which a relatively high applied voltage is applied. 10. The semiconductor integrated circuit device according to claim 9, wherein said high breakdown voltage semiconductor element includes a memory cell transistor of a flash EEPROM which is a nonvolatile memory. 11. A method for manufacturing a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixedly mounted, wherein a high withstand voltage semiconductor element having a relatively high applied voltage is mounted in an element isolation region. An isolation trench having a predetermined depth is formed, and an oxide film formed without using a thermal oxidation method is buried in the isolation trench. And around the isolation trench,
A method for manufacturing a semiconductor integrated circuit device in which a thermal oxide film having a predetermined thickness is formed by using a thermal oxidation method. 12. A method of manufacturing a semiconductor integrated circuit device in which a plurality of types of semiconductor elements having different applied voltages are mixedly mounted, wherein a high withstand voltage semiconductor element having a relatively high applied voltage is mounted in an element isolation region. An isolation trench having a predetermined depth is formed, an oxide film formed without using a thermal oxidation method is buried in the isolation trench with a predetermined thickness, and a low breakdown voltage semiconductor element having a relatively low applied voltage is mounted. On and around the element isolation region and the oxide film of the region,
A method for manufacturing a semiconductor integrated circuit device, wherein a thermal oxide film having a predetermined thickness is formed by using a thermal oxidation method. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein the high breakdown voltage semiconductor element includes a memory cell transistor of a flash EEPROM which is a nonvolatile memory. Method. 14. A method of manufacturing a semiconductor integrated circuit device having an element isolation region for isolating between semiconductor elements with a predetermined dielectric strength, comprising: forming an isolation trench having a predetermined depth in the element isolation region. Forming a polysilicon film in the isolation trench, leaving a polysilicon film of a predetermined thickness in the isolation trench, and thermally oxidizing the polysilicon film on the polysilicon film by a thermal oxidation method. A method for manufacturing a semiconductor integrated circuit device for forming a film. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein the semiconductor element is a high-voltage semiconductor element having a relatively high applied voltage. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the high breakdown voltage semiconductor element includes a memory cell transistor of a flash EEPROM which is a nonvolatile memory.