JP2001167929A - Laminated chip parts and manufacturing method of the same - Google Patents

Laminated chip parts and manufacturing method of the same

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Publication number
JP2001167929A
JP2001167929A JP34862199A JP34862199A JP2001167929A JP 2001167929 A JP2001167929 A JP 2001167929A JP 34862199 A JP34862199 A JP 34862199A JP 34862199 A JP34862199 A JP 34862199A JP 2001167929 A JP2001167929 A JP 2001167929A
Authority
JP
Japan
Prior art keywords
chip
shaped
laminated
external electrode
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34862199A
Other languages
Japanese (ja)
Inventor
Keiichi Morikane
圭一 森兼
Fujitaro Kamikane
藤太郎 上兼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP34862199A priority Critical patent/JP2001167929A/en
Publication of JP2001167929A publication Critical patent/JP2001167929A/en
Pending legal-status Critical Current

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  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide laminated chip parts with high dimensional accuracy that are suitable for high productivity and can cope with bulk chip mounting, and the manufacturing method of the same. SOLUTION: In laminated chip parts equipped with a chip-shaped laminate 12 having a coil-like internal conductor 10 formed by multilayered conductive patterns and a laminated chip part having an external electrode connected electrically to the end of the coil-like internal conductor 10, external electrodes 14 are so formed as to cover the circumferences of small-sized layers 12a provided in both ends of the chip-shaped laminate 12.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば積層高周波
インダクタや積層フェライトビーズ等の積層チップ部品
及びその製造方法に係り、特に角形のバルク対応のチッ
プ実装機を用いて表面実装が可能な積層チップ部品及び
その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer chip component such as a multilayer high-frequency inductor and a multilayer ferrite bead and a method of manufacturing the same, and more particularly to a multilayer chip that can be surface-mounted using a square bulk-compatible chip mounter. The present invention relates to a component and a method for manufacturing the same.

【0002】[0002]

【従来の技術】多数のチップ部品をカートリッジに収納
し、このチップ部品を一個ずつプリント基板等に表面実
装する、いわゆるバルク対応のチップ実装機が普及しつ
つある。このようなチップ実装に好適で、例えばインダ
クタンス素子として機能する積層チップ部品としては、
磁性体セラミックス等からなるグリーンシートの内部に
導体パターンを形成し、この導体パターンの一端を上方
に位置するグリーンシートの導体パターンの端部に、他
端を下方に位置するグリーンシートの導体パターンの端
部にそれぞれ電気的に導通させつつ多層に積層すること
で、導体パターンでコイル状内部導体を形成し、更に該
コイル状内部導体の端部に外部電極を電気的に接続した
ものが一般に知られている。
2. Description of the Related Art A so-called bulk-compatible chip mounter in which a large number of chip parts are housed in a cartridge and these chip parts are surface-mounted one by one on a printed circuit board or the like is becoming widespread. Suitable for such a chip mounting, for example, as a laminated chip component functioning as an inductance element,
A conductor pattern is formed inside a green sheet made of magnetic ceramics or the like, and one end of this conductor pattern is connected to the end of the conductor pattern of the green sheet positioned above, and the other end of the conductor pattern of the green sheet positioned below. It is generally known that a coil-shaped internal conductor is formed by a conductor pattern by laminating a plurality of layers while electrically conducting each end, and an external electrode is electrically connected to an end of the coiled internal conductor. Have been.

【0003】この種の積層チップ部品は、図6(a)に
示すように、グリーンシートを多段に積層して、内部に
多数のコイル状内部導体10を有するグリーン積層体1
1を形成し、図6(b)に示すように、このグリーン積
層体11を前記コイル状内部導体10をそれぞれ1個ず
つ有する各チップ状積層体12毎に切断線30,31に
沿って分割(バレルカット)し、しかる後、脱バインダ
(バインダバーンアウト)、焼成及びバレル研摩を行
う。そして、図6(c)に示すように、チップ状積層体
12を専用の外部電極塗布機13の所定の位置に整列さ
せ、この状態で、チップ状積層体12の端部の5面(端
面及び4側面)に導体層を塗布して乾燥させる工程を各
端面毎に2度繰り返し、更に焼付けを行って、図6
(d)に示すように、チップ状積層体12の両端部に前
記コイル状内部導体10と電気的に接続した外部電極1
4を形成することによって、一般に製造されていた。
As shown in FIG. 6 (a), this type of laminated chip component has a green laminated body 1 in which green sheets are laminated in multiple stages and a large number of coiled internal conductors 10 are provided inside.
6, the green laminate 11 is divided along cutting lines 30 and 31 for each chip-like laminate 12 having one coil-shaped internal conductor 10 as shown in FIG. (Barrel cut), and thereafter, binder removal (binder burnout), firing, and barrel polishing are performed. Then, as shown in FIG. 6C, the chip-shaped laminate 12 is aligned at a predetermined position of a dedicated external electrode coating machine 13, and in this state, the five surfaces (end surfaces) of the end of the chip-shaped laminate 12 are arranged. And the step of applying and drying the conductor layer on each of the four side surfaces is repeated twice for each end surface, and further baked to obtain FIG.
As shown in (d), the external electrodes 1 electrically connected to the coiled internal conductors 10 at both ends of the chip-shaped laminate 12.
4 was generally produced.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述し
た積層チップ部品においては、外部電極14に寸法精度
にバラツキが生じ易く、特に、近年の小型化高周波化の
要求により、積層チップの寸法サイズの主流が、100
5(1.0×0.5mm)に移行し、0603(0.6
×0.3mm)サイズの製品化が進む中で、外部電極を
寸法精度良く成形することがかなり困難で、これがチッ
プ部品製造の際の大きなネックとなっているのが現状で
あった。
However, in the above-described laminated chip component, the dimensional accuracy of the external electrode 14 is apt to vary, and in particular, due to the recent demand for miniaturization and high frequency, the dimensional size of the laminated chip has become mainstream. But 100
5 (1.0 × 0.5 mm) and 0603 (0.6
In the course of commercialization of (.times.0.3 mm) size, it is quite difficult to form external electrodes with high dimensional accuracy, and this has become a major bottleneck in the production of chip components.

【0005】しかも、バレルカット後に電極付けを行っ
ているため、この電極付け工程が専用の電極塗布機を使
用した整列等の手間のかかる作業を伴う工程となって、
生産性が悪いといった問題があった。
In addition, since the electrodes are attached after the barrel cut, this electrode attaching step is a step that involves time-consuming operations such as alignment using a dedicated electrode coating machine.
There was a problem that productivity was poor.

【0006】本発明は上述した事情に鑑みて為されたも
ので、生産性が良く、バルク対応のチップ実装に好適
で、寸法精度の高い積層チップ部品及びその製造方法を
提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a multilayer chip component having good productivity, suitable for chip mounting in bulk, and having high dimensional accuracy, and a method of manufacturing the same. I do.

【0007】[0007]

【課題を解決するための手段】請求項1に記載の発明
は、多段に積層した導体パターンで形成されたコイル状
内部導体を有するチップ状積層体と、前記コイル状内部
導体の端部に電気的に接続した外部電極を備えた積層チ
ップ部品において、前記外部電極は、前記チップ状積層
体の両端部に設けた小形部の周囲を覆うように形成され
ていることを特徴とする積層チップ部品である。
According to a first aspect of the present invention, there is provided a chip-shaped laminated body having a coil-shaped internal conductor formed of a multi-layered conductor pattern, and an electric terminal provided at an end of the coil-shaped internal conductor. Wherein the external electrodes are formed so as to cover small parts provided at both ends of the chip-shaped laminated body. It is.

【0008】このように構成した本発明によれば、外部
電極がその厚さ分だけ積層チップ部品の端部側面から外
方に出っ張ってしまうことを防止して、その分、寸法精
度を良くすることができる。
According to the present invention having such a configuration, the external electrodes are prevented from protruding outward from the end side surfaces of the laminated chip component by the thickness thereof, and the dimensional accuracy is improved accordingly. be able to.

【0009】請求項2に記載の発明は、前記チップ状積
層体の端面に位置する外部電極には、中空部が設けられ
ていることを特徴とする請求項1記載の積層チップ部品
である。これにより、外部電極に起因する損失(渦電流
及び浮遊容量)をより小さくして、チップ部品の小型化
に伴う浮遊容量等の製品特性への影響を軽減することが
できる。なお、外部電極に中空部が設けられる場合、そ
の中空部からバインダが出て行くことが可能なため、脱
バインダ前の積層シート(グリーン積層体)に外部電極
を形成するようにすることもできる。
According to a second aspect of the present invention, there is provided the multilayer chip component according to the first aspect, wherein a hollow portion is provided in the external electrode located at an end face of the chip-shaped multilayer body. As a result, the loss (eddy current and stray capacitance) caused by the external electrode can be further reduced, and the influence on the product characteristics such as the stray capacitance due to the miniaturization of the chip component can be reduced. When a hollow portion is provided in the external electrode, the binder can come out of the hollow portion, so that the external electrode can be formed on the laminated sheet (green laminate) before the binder is removed. .

【0010】請求項3に記載の発明は、内部に多段に積
層した導体パターンで形成された多数のコイル状内部導
体を有するグリーン積層体を形成し、該グリーン積層体
の上下両面の前記コイル状内部導体を個々に分離する切
断線に沿った位置に格子状の溝を形成して脱バインダを
行い、前記脱バインダ後の未焼成積層体の上下両面に外
部電極を構成する導体層を一面に設けた後、前記溝に沿
った切断及び焼成を行うことを特徴とする積層チップ部
品の製造方法である。
According to a third aspect of the present invention, there is provided a green laminate having a large number of coil-shaped internal conductors formed by a multi-layered conductor pattern therein, and the coil-form on both upper and lower surfaces of the green laminate. A grid-shaped groove is formed at a position along a cutting line that separates the internal conductors to remove the binder, and the conductor layers constituting the external electrodes are formed on both upper and lower surfaces of the unfired laminate after the removal of the binder. After the provision, the cutting and baking along the groove are performed, and the method for manufacturing a laminated chip component is provided.

【0011】これにより、未焼成積層体の一面に外部電
極を構成する導体層を形成することで、外部電極のバラ
ツキを抑えてこの寸法精度を高め、しかも導体層を形成
した後に切断(チッピング)を行うことで、専用の電極
塗布機を使用した整列等の手間のかかる作業をなくし、
かつチップ端部の5面一度に導体層を形成することがで
きる。
Thus, by forming a conductor layer constituting an external electrode on one surface of the unfired laminated body, variation in the external electrode is suppressed, the dimensional accuracy is improved, and cutting (chipping) is performed after the conductor layer is formed. By doing, eliminate the troublesome work such as alignment using a dedicated electrode coating machine,
In addition, the conductor layer can be formed at once on the five surfaces of the chip end.

【0012】請求項4に記載の発明は、内部に多段に積
層した導体パターンで形成された多数のコイル状内部導
体を有するグリーン積層体を形成し、該グリーン積層体
の上下両面に格子状の切込みを入れたシートを上下から
挟み込むように積層して前記コイル状内部導体を個々に
分離する切断線に沿った位置に前記切込みによる溝を形
成して脱バインダを行い、前記脱バインダ後の未焼成積
層体の上下両面に外部電極を構成する導体層を一面に設
けた後、前記溝に沿った切断及び焼成を行うことを特徴
とする積層チップ部品の製造方法である。
According to a fourth aspect of the present invention, there is provided a green laminate having a large number of coil-shaped internal conductors formed therein with a multi-layered conductor pattern, and a grid-like structure is formed on both upper and lower surfaces of the green laminate. The cut sheet is laminated so as to be sandwiched from above and below, and the groove is formed by the cut at a position along a cutting line that separates the coil-shaped internal conductors individually, and the binder is removed. A method for manufacturing a laminated chip component, comprising: providing a conductor layer constituting an external electrode on one surface of upper and lower surfaces of a fired laminated body; and cutting and firing along the groove.

【0013】これにより、例えば加工精度が高いレーザ
等を使って切込みを入れたシートで切断線に沿った位置
に溝を形成することで、この溝の加工精度を高めてチッ
プ自体の小型化に対処することができる。
By forming a groove at a position along a cutting line with a sheet having a notch by using a laser or the like having a high processing accuracy, the processing accuracy of the groove is increased and the chip itself can be reduced in size. I can deal with it.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態につい
て添付図面を参照しながら説明する。図1は、本発明の
実施の形態の積層高周波インダクタに適用した積層チッ
プ部品を示す斜視図で、この積層チップ部品は、内部に
コイル状内部導体10を形成した正四角柱状のチップ状
積層体12と、このチップ状積層体12の両端部に形成
した外部電極14とから構成され、前記コイル状内部導
体10と外部電極14とは電気的に接続されている。
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a perspective view showing a laminated chip component applied to a laminated high-frequency inductor according to an embodiment of the present invention. The laminated chip component is a square prism-shaped chip-shaped laminate having a coiled internal conductor 10 formed therein. 12 and external electrodes 14 formed at both ends of the chip-shaped laminated body 12, and the coil-shaped internal conductor 10 and the external electrodes 14 are electrically connected.

【0015】前記チップ状積層体12の端部には、外部
電極14の厚みに見合った厚さだけ内方に引き込んだ小
径部12aが設けられ、前記外部電極14は、この小径
部12aの全域、即ち4側面と端面の5面を一体に覆っ
ている。これによって、チップ部品の側面が面一となっ
て、ここに外部電極14による出っ張りが生じないよう
になっている。
At the end of the chip-shaped laminate 12, there is provided a small-diameter portion 12a which is drawn inward by a thickness corresponding to the thickness of the external electrode 14, and the external electrode 14 covers the entire area of the small-diameter portion 12a. That is, the four side surfaces and the five end surfaces are integrally covered. As a result, the side surfaces of the chip component are flush with each other, and no protrusion by the external electrode 14 is generated here.

【0016】このように、外部電極14がその厚さ分だ
け積層チップ部品の端部側面から外方に出っ張ってしま
うことを防止することで、積層チップ部品の寸法精度を
良くすることができる。
In this way, by preventing the external electrodes 14 from protruding outward from the end side surfaces of the laminated chip component by the thickness thereof, the dimensional accuracy of the laminated chip component can be improved.

【0017】ここに、前記コイル状内部導体10は、図
2に示すように、例えばコ字状の3/4周または対角線
状に角部から中央に向かって延びる導体パターン21を
形成した、例えば磁性体セラミックス等からなるグリー
ンシート20を複数枚用意して、一方向(図示では、上
から見て右方向)に巻回すように、上下に位置するグリ
ーンシート20の導体パターン21の端部同士をスルー
ホール22を介して交互に電気的に導通させつつ、グリ
ーンシート20を順次積層することによって形成されて
いる。そして、このコイル状内部導体10と外部電極1
4とは、上下両面に位置するグリーンシート20aに設
けたスルーホール22aを介して電気的に接続される。
Here, as shown in FIG. 2, the coil-shaped inner conductor 10 is formed with a conductor pattern 21 extending from the corner to the center in, for example, a U-shaped 3/4 circumference or diagonally. A plurality of green sheets 20 made of magnetic ceramics or the like are prepared, and the ends of the conductor patterns 21 of the green sheets 20 positioned above and below are wound so as to be wound in one direction (in the drawing, the right direction when viewed from above). Are alternately electrically conducted through the through holes 22 while the green sheets 20 are sequentially laminated. The coiled inner conductor 10 and the outer electrode 1
4 is electrically connected to the green sheets 20a located on both upper and lower surfaces through through holes 22a provided in the green sheets 20a.

【0018】図3は、本発明のそれぞれ異なる他の実施
の形態の積層チップ部品を示すもので、図3(a)は、
チップ状積層体12の端面を位置する外部電極14に円
形の中空部14aを、図3(b)は、正方形状の中空部
14bをそれぞれ設け、この中空部14a,14bを介
してチップ状積層体12の端面を外部に露出させたもの
である。この中空部14a,14bは、例えばレーザに
よる穴開けや、下記のように、導体ペーストを塗布して
導体膜を形成する際に、この導体ペーストをパターン印
刷することによって形成される。
FIG. 3 shows a laminated chip component according to another embodiment of the present invention, and FIG.
A circular hollow portion 14a is provided in the external electrode 14 located at the end face of the chip-shaped laminated body 12, and in FIG. 3B, a square hollow portion 14b is provided, and the chip-shaped laminated portion is provided through the hollow portions 14a and 14b. The end face of the body 12 is exposed to the outside. The hollow portions 14a and 14b are formed by pattern printing of a conductive paste when forming a conductive film by, for example, drilling a hole with a laser or applying a conductive paste as described below.

【0019】このように、中空部14a,14bを介し
てチップ状積層体12の端面がその全面に亘って外部電
極14で覆われることを阻止することで、外部電極14
に起因する損失(渦電流及び浮遊容量)がより小さくな
る。従って、チップ部品の小型化に伴って、外部電極1
4とコイル状内部導体10とに生じる浮遊容量がチップ
部品の特性に影響するのを極力防止して、高周波特性が
改善される。また、このように、外部電極14に中空部
14a,14bを設けると、この中空部14a,14b
からバインダが出て行くため、脱バインダ前の積層シー
ト(グリーン積層体)に外部電極を形成することが可能
となる。
As described above, by preventing the end surface of the chip-shaped laminated body 12 from being covered with the external electrode 14 over the entire surface through the hollow portions 14a and 14b, the external electrode 14
(Eddy currents and stray capacitances) due to the above. Therefore, with the miniaturization of chip components, external electrodes 1
4 and the coil-shaped internal conductor 10 are prevented from affecting the characteristics of the chip component as much as possible, and the high-frequency characteristics are improved. When the hollow portions 14a and 14b are provided in the external electrode 14, the hollow portions 14a and 14b
As a result, the external electrode can be formed on the laminated sheet (green laminate) before the binder is removed.

【0020】次に、本発明の実施の形態の図1に示す積
層チップ部品の製造方法を図4を参照して説明する。先
ず、図4(a)に示すように、外部電極形成面が上下面
となる多数のコイル状内部導体10を有するグリーン積
層体11を形成する。このグリーン積層体11は、切断
線30,31に沿って格子状に切断すると焼成前のチッ
プ状積層体12に分離される該チップ状積層体12の集
合体であり、所定の形状の導体パターン及び/又はスル
ーホールを形成したグリーンシートを積層し圧着するこ
とによって形成される。
Next, a method of manufacturing the laminated chip component shown in FIG. 1 according to the embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 4A, a green laminate 11 having a large number of coil-shaped internal conductors 10 whose external electrode formation surfaces are upper and lower surfaces is formed. The green laminated body 11 is an aggregate of the chip laminated bodies 12 that are cut into a chip laminated body 12 before firing when cut in a lattice shape along the cutting lines 30 and 31, and has a predetermined shape of a conductor pattern. And / or by laminating and crimping green sheets having formed through holes.

【0021】なお、このグリーン積層体11の上下両面
を研磨することにより、コイル状内部導体10の端面を
グリーン積層体11の表面に出して、外部電極14との
密着性及び導通を確かなものとするとともに、下記の導
体層40をより均一な膜厚で印刷することができる。
The upper and lower surfaces of the green laminate 11 are polished so that the end face of the coil-shaped internal conductor 10 is exposed to the surface of the green laminate 11 to ensure adhesion and conduction with the external electrodes 14. In addition, the following conductor layer 40 can be printed with a more uniform film thickness.

【0022】次に、図4(b)に示すように、前記切断
線30,31に沿って、グリーン積層体11の上下面
に、例えばダイシングによって所定の深さの格子状の溝
32,33を形成する。そして、必要に応じて、研磨用
治具やサンドブラストによって、溝32,33の入口の
角張った角部の面取りを施す。このように面取りを施す
ことで、下記のペースト塗布の際に、このペーストの付
きを良くして、信頼性を向上させることができる。
Next, as shown in FIG. 4B, along the cutting lines 30 and 31, the lattice-shaped grooves 32 and 33 of a predetermined depth are formed on the upper and lower surfaces of the green laminate 11 by dicing, for example. To form Then, if necessary, the square corners of the entrances of the grooves 32 and 33 are chamfered by a polishing jig or sand blast. By performing the chamfering in this way, it is possible to improve the sticking of the paste and improve the reliability at the time of applying the paste described below.

【0023】そして、グリーン積層体11の内部に含ま
れているバインダを飛ばす(脱バインダ)。この時、グ
リーン積層体11の上下面には、格子状の溝32,33
がその全面に亘って形成されているため、この溝32,
33を介してグリーン積層体11の内部からバインダを
容易に抜くことができる。
Then, the binder contained in the green laminate 11 is blown off (removal of the binder). At this time, the upper and lower surfaces of the green laminate 11 are provided with lattice-shaped grooves 32, 33, respectively.
Are formed over the entire surface thereof, so that the grooves 32,
The binder can be easily removed from the inside of the green laminated body 11 via 33.

【0024】この状態で、図4(c)に示すように、例
えばAgペーストやAg−Pdペースト等の導体ペース
トをメタルスクリーン印刷やメタルマスク印刷等でべた
塗りして乾燥させる工程を上下面とも行い、脱バインダ
後の未焼成積層体11aの上下両面に外部電極14を構
成する導体層40を形成する。このように、未焼成積層
体11aの一面に外部電極14を構成する導体層40を
形成することで、外部電極14のバラツキを抑えてこの
寸法精度を高めることができる。ここで、脱バインダ後
の未焼成積層体11aは、強度的に非常に脆くなってい
るため、完全に焼結しない程度の温度で焼成した後に、
導体ペーストの塗布を行うようにしても良い。
In this state, as shown in FIG. 4C, a step of solid-coating a conductor paste such as an Ag paste or an Ag-Pd paste by metal screen printing, metal mask printing, or the like, and drying is performed on both the upper and lower surfaces. Then, the conductor layers 40 constituting the external electrodes 14 are formed on the upper and lower surfaces of the unfired laminated body 11a after the binder removal. As described above, by forming the conductor layer 40 constituting the external electrode 14 on one surface of the unfired laminated body 11a, it is possible to suppress the variation of the external electrode 14 and increase the dimensional accuracy. Here, since the unfired laminate 11a after the binder removal is very brittle in strength, it is fired at a temperature that does not completely sinter,
You may make it apply | coat the conductor paste.

【0025】次に、所定の温度で乾燥及び電極の焼付け
を行った後、図4(d)に示すように、前記溝32,3
3に沿って、未焼成積層体11aを切断して焼成前の各
チップ状積層体12毎に分割(バレルカット)し、しか
る後、例えば800〜950℃で未焼成積層体11aを
焼成する。このバレルカットは、乾燥後で電極の焼付け
前に行っても、電極と未焼成積層体11aの一体焼成後
に行っても良い。
Next, after drying and baking of the electrodes at a predetermined temperature, the grooves 32, 3 are formed as shown in FIG.
Along 3, the unfired laminated body 11 a is cut and divided (barrel cut) into each chip-shaped laminated body 12 before firing, and thereafter, the unfired laminated body 11 a is fired at, for example, 800 to 950 ° C. This barrel cutting may be performed after drying and before baking the electrodes, or may be performed after the electrodes and the unfired laminate 11a are integrally fired.

【0026】なお、乾燥後で焼成前にバレルカットを行
うことで、刃の摩耗を少なくできるが、乾燥だけではチ
ップ状積層体12と外部電極14との接着力が弱く、ダ
イシングの衝撃で剥離する恐れがある。また、バレルカ
ット後に電極の焼付けを行うと、工程の増加に繋がる。
その点、電極焼付け後にバレルカットを行うと、刃の摩
耗は早まるものの、信頼性及び生産性が高い。
By performing barrel cutting after drying and before firing, abrasion of the blade can be reduced. However, if only drying is performed, the adhesive force between the chip-shaped laminate 12 and the external electrode 14 is weak, and the chip is peeled off by the impact of dicing. Might be. Further, if the electrodes are baked after the barrel cut, the number of steps is increased.
In this regard, when barrel cutting is performed after the electrode is baked, the wear of the blade is accelerated, but the reliability and productivity are high.

【0027】このように、外部電極14を構成する導体
層40を形成した後に、溝32,33に沿って切断(チ
ッピング)することで、専用の電極塗布機を使用した整
列等の手間のかかる作業をなくし、しかも、チップ端部
の5面(端面及び4側面)一度に導体層40を形成する
ことができる。
As described above, after the conductor layer 40 forming the external electrode 14 is formed, cutting (chipping) along the grooves 32 and 33 takes time and effort such as alignment using a dedicated electrode coating machine. The operation can be eliminated, and the conductor layer 40 can be formed at once on the five surfaces (end surface and four side surfaces) of the chip end.

【0028】図5は、本発明の他の実施の形態の積層チ
ップ部品の製造方法を示すもので、先ず、図5(a)に
示すように、例えばガラス等の透光性を有する平滑な板
体50の片面に、例えば図2に示す、スルーホール22
aの内部に導電ペーストを印刷法などで充填したグリー
ンシート20aを積層してシート51を形成し、このシ
ート51に、例えばレーザ加工を施して、グリーン積層
体11の切断線30,31に対応する位置に板体50に
達する切込み52,53を入れる。
FIG. 5 shows a method for manufacturing a laminated chip component according to another embodiment of the present invention. First, as shown in FIG. 5 (a), a light-transmitting smooth material such as glass is used. For example, a through hole 22 shown in FIG.
a, a sheet 51 is formed by laminating a green sheet 20a filled with a conductive paste by a printing method or the like, and this sheet 51 is subjected to, for example, laser processing to correspond to the cutting lines 30 and 31 of the green laminate 11. Cuts 52 and 53 reaching the plate body 50 are made at the positions where they will be.

【0029】次に、図5(b)に示すように、グリーン
積層体11を挟んで、この上下にシート51を板体50
を外側にした状態でサンドイッチ状に配置して熱圧着
し、しかる後、板体50を除去する。これによって、図
5(c)に示すように、グリーン積層体11の上下面に
切込み52,53により溝32,33を形成する。
Next, as shown in FIG. 5B, a sheet 51 is placed above and below the green laminate 11 with a plate 50 therebetween.
Is placed in a sandwich shape with the outside facing, and thermocompression-bonded. Thereafter, the plate body 50 is removed. Thereby, as shown in FIG. 5C, grooves 32 and 33 are formed in the upper and lower surfaces of the green laminate 11 by the cuts 52 and 53, respectively.

【0030】この状態で、前記と同様に、脱バインダ、
電極付け及び乾燥、溝32,33に沿った切断(チッピ
ング)、更には焼成を行って、積層チップ部品を完成さ
せる。この実施の形態によれば、例えば加工精度が高い
レーザ等を使ってシートに切込み52,53を入れ、こ
の切込み52,53で切断線30,31に沿った位置に
溝32,33を形成することで、この溝32,33の加
工精度を高めてチップ自体の小型化に対処することがで
きる。
In this state, the binder removal,
The laminated chip component is completed by performing electrode attachment and drying, cutting (chipping) along the grooves 32 and 33, and further firing. According to this embodiment, for example, cuts 52 and 53 are made in the sheet using a laser or the like having high processing accuracy, and grooves 32 and 33 are formed at positions along cut lines 30 and 31 by these cuts 52 and 53. This makes it possible to increase the processing accuracy of the grooves 32 and 33 and to cope with downsizing of the chip itself.

【0031】なお、上記の実施の形態では、積層チップ
部品をグリーンシート法により製造する例について説明
したが、例えば印刷法についても、本発明の趣旨を逸脱
しない範囲で同様に適用できることは勿論である。
In the above-described embodiment, an example in which the laminated chip component is manufactured by the green sheet method has been described. However, it is needless to say that the printing method can be similarly applied without departing from the gist of the present invention. is there.

【0032】[0032]

【発明の効果】以上に説明したように、本発明によれ
ば、外部電極をチップ状積層体の両端部に設けた小形部
の周囲を覆うように形成することで、外部電極がその厚
さ分だけ積層チップ部品の端部側面から外方に出っ張っ
てしまうことを防止して、寸法精度を良くし、更には、
チップ状積層体の端面に位置する外部電極に中空部を設
けることで、外部電極に起因する損失(渦電流及び浮遊
容量)をより小さくし、チップ部品の小型化に伴う浮遊
容量等の製品特性への影響を軽減して、小型化高周波化
の要請に答えることができる。また、本発明の製造方法
によれば、いわゆるバルク対応のチップ実装に好適で周
波数特性の良好な小型で外部電極の寸法精度を向上させ
た積層チップ部品を生産性を高めて製造することがで
き、又その製造コストを低減し、リードタイムを短縮す
ることができる。
As described above, according to the present invention, the external electrodes are formed so as to cover the small portions provided at both ends of the chip-shaped laminated body, so that the external electrodes have a small thickness. It prevents dimensional protrusion from protruding outward from the end side surface of the laminated chip component, improves dimensional accuracy, and furthermore,
By providing a hollow portion in the external electrode located at the end face of the chip-shaped laminate, the loss (eddy current and stray capacitance) caused by the external electrode is further reduced, and product characteristics such as stray capacitance accompanying miniaturization of chip components To meet the demand for miniaturization and higher frequency. Further, according to the manufacturing method of the present invention, it is possible to manufacture a multilayer chip component which is suitable for so-called bulk-compatible chip mounting, has good frequency characteristics, and has improved dimensional accuracy of external electrodes, with increased productivity. In addition, the manufacturing cost can be reduced, and the lead time can be shortened.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の積層チップ部品を示す斜
視図である。
FIG. 1 is a perspective view showing a laminated chip component according to an embodiment of the present invention.

【図2】図1に示す積層チップ部品の焼成前の分解斜視
図である。
FIG. 2 is an exploded perspective view of the laminated chip component shown in FIG. 1 before firing.

【図3】本発明の他の実施の形態のそれぞれ異なる積層
チップ部品を示す斜視図である。
FIG. 3 is a perspective view showing different laminated chip components according to another embodiment of the present invention.

【図4】本発明の実施の形態の積層チップ部品の製造方
法を工程順に示す図である。
FIG. 4 is a diagram illustrating a method of manufacturing a laminated chip component according to an embodiment of the present invention in the order of steps.

【図5】本発明の他の実施の形態の積層チップ部品の製
造方法を工程順に示す図である。
FIG. 5 is a diagram illustrating a method of manufacturing a laminated chip component according to another embodiment of the present invention in the order of steps.

【図6】従来の積層チップ部品の製造例を工程順に示す
図である。
FIG. 6 is a diagram showing an example of manufacturing a conventional laminated chip component in the order of steps.

【符号の説明】[Explanation of symbols]

10 コイル状内部導体 11 グリーン積層体 11a 未焼成積層体 12 チップ状積層体 12a 小径部 14 外部電極 14a,14b 中空部 20,20a グリーンシート 21 導体パターン 22,22a スルーホール 30,31 切断線 32,33 溝 40 導体層 50 板体 51 シート 52,53 切込み DESCRIPTION OF SYMBOLS 10 Coil-shaped inner conductor 11 Green laminated body 11a Unfired laminated body 12 Chip-shaped laminated body 12a Small diameter part 14 External electrode 14a, 14b Hollow part 20, 20a Green sheet 21 Conductor pattern 22, 22a Through hole 30, 31, Cutting line 32, 33 groove 40 conductor layer 50 plate 51 sheet 52, 53 cut

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 多段に積層した導体パターンで形成され
たコイル状内部導体を有するチップ状積層体と、前記コ
イル状内部導体の端部に電気的に接続した外部電極を備
えた積層チップ部品において、 前記外部電極は、前記チップ状積層体の両端部に設けた
小形部の周囲を覆うように形成されていることを特徴と
する積層チップ部品。
1. A laminated chip component comprising: a chip-shaped laminated body having a coil-shaped internal conductor formed by a multi-layered conductor pattern; and an external electrode electrically connected to an end of the coil-shaped internal conductor. The multilayer chip component, wherein the external electrodes are formed so as to cover small parts provided at both ends of the chip-shaped laminate.
【請求項2】 前記チップ状積層体の端面に位置する外
部電極には、中空部が設けられていることを特徴とする
請求項1記載の積層チップ部品。
2. The multilayer chip component according to claim 1, wherein a hollow portion is provided in an external electrode located at an end face of the chip-shaped multilayer body.
【請求項3】 内部に多段に積層した導体パターンで形
成された多数のコイル状内部導体を有するグリーン積層
体を形成し、 該グリーン積層体の上下両面の前記コイル状内部導体を
個々に分離する切断線に沿った位置に格子状の溝を形成
して脱バインダを行い、 前記脱バインダ後の未焼成積層体の上下両面に外部電極
を構成する導体層を一面に設けた後、 前記溝に沿った切断及び焼成を行うことを特徴とする積
層チップ部品の製造方法。
3. A green laminate having a large number of coiled internal conductors formed by a conductor pattern laminated in multiple stages inside is formed, and the coiled internal conductors on the upper and lower surfaces of the green laminate are individually separated. After forming a lattice-like groove at a position along the cutting line and performing binder removal, a conductor layer constituting an external electrode is provided on one surface on both upper and lower surfaces of the unfired laminate after the binder removal, and then the groove is formed. A method for manufacturing a laminated chip component, comprising cutting and firing along.
【請求項4】 内部に多段に積層した導体パターンで形
成された多数のコイル状内部導体を有するグリーン積層
体を形成し、 該グリーン積層体の上下両面に格子状の切込みを入れた
シートを上下から挟み込むように積層して前記コイル状
内部導体を個々に分離する切断線に沿った位置に前記切
込みによる溝を形成して脱バインダを行い、 前記脱バインダ後の未焼成積層体の上下両面に外部電極
を構成する導体層を一面に設けた後、 前記溝に沿った切断及び焼成を行うことを特徴とする積
層チップ部品の製造方法。
4. A green laminate having a large number of coil-shaped internal conductors formed by a multi-layered conductor pattern formed inside, and a sheet having a grid-shaped cut on both upper and lower surfaces of the green laminate is moved up and down. A groove is formed by cutting at a position along a cutting line that separates the coil-shaped internal conductors by sandwiching them from each other to perform binder removal, and on the upper and lower surfaces of the unfired laminated body after the binder removal. A method for manufacturing a laminated chip component, comprising: providing a conductor layer constituting an external electrode on one surface; and performing cutting and firing along the groove.
JP34862199A 1999-12-08 1999-12-08 Laminated chip parts and manufacturing method of the same Pending JP2001167929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34862199A JP2001167929A (en) 1999-12-08 1999-12-08 Laminated chip parts and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34862199A JP2001167929A (en) 1999-12-08 1999-12-08 Laminated chip parts and manufacturing method of the same

Publications (1)

Publication Number Publication Date
JP2001167929A true JP2001167929A (en) 2001-06-22

Family

ID=18398238

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001167929A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294927A (en) * 2005-04-12 2006-10-26 Murata Mfg Co Ltd Laminated coil
JP2010093061A (en) * 2008-10-08 2010-04-22 Murata Mfg Co Ltd Method of manufacturing electronic component
JP2011009618A (en) * 2009-06-29 2011-01-13 Yoshizumi Fukui Method of manufacturing winding-integrated mold coil
US9178239B2 (en) 2012-04-16 2015-11-03 Denso Corporation Proton conductor, method for manufacturing proton conductor, and fuel cell

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006294927A (en) * 2005-04-12 2006-10-26 Murata Mfg Co Ltd Laminated coil
JP2010093061A (en) * 2008-10-08 2010-04-22 Murata Mfg Co Ltd Method of manufacturing electronic component
JP2011009618A (en) * 2009-06-29 2011-01-13 Yoshizumi Fukui Method of manufacturing winding-integrated mold coil
US9178239B2 (en) 2012-04-16 2015-11-03 Denso Corporation Proton conductor, method for manufacturing proton conductor, and fuel cell

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