JP2001167067A - Multiprocessor system and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly efficiently transfer data at high speed even when the number of processors is increased and the scale of a multiprocessor system is expanded. SOLUTION: This system is provided with plural system modules respectively provided with plural processors, a transfer control part and a first cross bar and a cross bar module provided with a second cross bar for connecting the plural system module and when performing transfer inside one arbitrary system module, the transfer control part internally transfers a control information packet without interposing the second cross bar.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system and a data transfer method, and more particularly, to a multiprocessor system in which a plurality of system modules each having a plurality of processors are connected, and data transfer in such a multiprocessor system. About the method.

[0002]

2. Description of the Related Art In a conventional multiprocessor system,
A plurality of processors are connected via a bus. However, as the number of processors increases and the size of the multiprocessor system increases, contention on the bus frequently occurs. Therefore, it becomes difficult to perform data transfer at high speed and with high efficiency.

[0003]

Therefore, in the conventional multiprocessor system, when the number of processors is very large, it is difficult to perform data transfer at high speed and with high efficiency, and originally the performance of the multiprocessor system is improved. For this reason, there has been a problem that the performance cannot be remarkably improved in terms of data transfer between processors despite the increase in the number of processors.

Therefore, the present invention provides a multiprocessor system and a data transfer method capable of performing data transfer at high speed and with high efficiency even if the number of processors increases and the multiprocessor system increases in scale. The purpose is to do.

[0005]

SUMMARY OF THE INVENTION The above object is achieved by providing a plurality of system modules, each including a plurality of processors, a transfer control unit, and a first crossbar, and a second crossbar connecting the plurality of system modules. And a transfer control unit that transfers control information packets internally without passing through the second crossbar when transfer is performed in any one system module. Is done.

The transfer control unit does not involve data transfer.
Liplion for notification of Liplion Lee transfer
A configuration may also be adopted in which the relay packet is also transferred. The transfer
The control unit is provided from outside the arbitrary one of the system modules.
Priority YC of transfer of control information packet to be transferred_OUT
And transferred within any one of the system modules
Control information packet transfer priority YC_INAnd the optional
Replies transferred from outside one system module
Priority YR of transfer of only packets_OUTAnd the optional
Lipra ions transferred within one system module
Reason packet transfer priority YR_INAnd YC_OUT>
YC_IN> YR_OUT> YR _INTo satisfy the relationship
The buffering may be performed in a fixed manner.

[0007] When the first crossbar performs transfer within the arbitrary one of the system modules, the first crossbar includes a return unit that internally transfers a data packet without passing through the second crossbar. It is good also as composition which has. The above object is to provide a multiprocessor system in which a plurality of system modules each including a plurality of processors, a transfer control unit, and a first crossbar are connected via a crossbar module including a second crossbar. When the transfer is performed in any one system module, the data transfer method includes a step of internally transferring a control information packet and a data packet without passing through the second crossbar. Achieved.

Therefore, according to the present invention, a multiprocessor system and a data transfer method capable of performing data transfer at high speed and with high efficiency even when the number of processors is increased and the multiprocessor system is enlarged. Can be realized.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a multiprocessor system according to the present invention and a data transfer method according to the present invention will be described below with reference to the drawings.

[0010]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a multiprocessor system according to the present invention.
The first embodiment of the multiprocessor system employs the first embodiment of the data transfer method according to the present invention. The multiprocessor system shown in FIG. 1 includes a plurality of system modules (or system boards: SB) 1-1 to 1-N,
Crossbar module (or crossbar board: XB) 2
And a bus 3 connecting the system modules 1-1 to 1-N and the crossbar module 2. Each of the system modules 1-1 to 1-N has the same configuration.

FIG. 2 is a block diagram showing the configuration of one system module 1. In FIG. 1, a system module 1 includes a plurality of processors 11-1 to 11-M each including a CPU or the like and having a cache memory, and a main memory 1
2, a general control unit 13 for controlling access to the main memory 12, etc., a transfer control unit 14, and a level 1 (L1) crossbar 15. The transfer control unit 14 includes a control bus (hereinafter, referred to as a C bus) 3-1 constituting the bus 3,
The L1 crossbar 15 is connected to an address bus 3-3 and a status bus 3-4, and the L1 crossbar 15 is connected to a data bus (hereinafter, referred to as a D bus) 3-2 constituting the bus 3.

FIG. 3 is a block diagram showing the configuration of the crossbar module 2. In the figure, crossbar module 2
Is composed of a transfer control unit 21, an address public information unit 22, and a cache public information unit 23. This crossbar module 2
Is a system module 1- 1 shown in FIG.
It is shown as connecting between 1 and 1-2. As described later, the transfer control unit 21 includes a level 2 (L2) crossbar 25-1 connected to the C bus 3-1 and a D bus 3-2.
And an L2 crossbar 25-2 connected thereto.

First, the procedure of a read process, which is one of the normal transfer processes, will be described. For example, a read request issued from the system module 1-1 is supplied by the crossbar module 2 to each of the system modules 1-2 to 1-N via the address bus 3-3 of the bus 3. The crossbar module 2 broadcasts the requested address of the read request from the address publicizing unit 22 to each of the system modules 1-2 to 1-N via the address bus 3-3 of the bus 3. All the system modules 1-1 to 1-N transmit cache information (status information) indicating the state of the cache memories of the processors 11-1 to 11-M mounted on the respective modules via the status bus 3-4 of the bus 3. To the crossbar module 2. The crossbar module 2 sends the merged cache information from the cache information unit 23 via the bus status bus 3-4 to each system module 1-
Advertise to 1-1-N. As a result, the system module having the memory of the requested address and holding the valid data in the memory is replaced with the system module 1-
If the data exists in 2 to 1-N, the valid data is read out and output to the crossbar module 2 via the transfer control unit 14 and the L1 crossbar 15, and further transferred to the transfer control unit 21 of the crossbar module 2. Is transferred to the requesting system module 1-1 via the. If the requesting system module 1-1 has a memory of the requested address, the data is transferred to the requesting processor in the system module 1-1.

This embodiment is characterized in the data transfer within the system module or between the system modules after the above-mentioned address information and cache information information are broadcast, that is, after preparation for data transfer is completed. is there. In the following description, the read process will be described for convenience of description, but it goes without saying that the same data transfer is performed in the write process.

FIG. 4 is a block diagram showing a main part of this embodiment. In the figure, the same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof will be omitted. Also, for convenience of explanation, FIG. 1 shows only the connection between the system module 1-1 and the system module 1-2 via the crossbar module 2. An arbitration unit 31 that arbitrates requests from the processors 11-1 to 11-M and the like in a transfer control unit 14 in each of the system modules 1-1 and 1-2, and a data arrival determination unit that determines arrival of transfer data. A judgment circuit 32 is provided. The arbitration unit 31 includes an arbitration circuit 31C for C and an arbitration circuit 31 for R.
R. The arbitration unit 31 and the L1 crossbar 15 are connected to the processors 11-1 to 11-M, the main memory 12, an input / output (IO) port (not shown), and receive transfer requests such as read requests including data. Is entered. Data transfer is performed by multiplexing data and control information.

The transfer control unit 1 of the system module 1-1
4 is the L of the crossbar module 2 via the C bus 3-1.
2 Connected to the crossbar 25-1, the system module 1
The -2 transfer control unit 14 is connected to the L2 crossbar 25-1 of the crossbar module 2 via the C bus 3-1. That is, the transfer control unit 14 in each system module
Is the L2 of the C bus 3-1 and the L2 crossbar module 2.
Via the crossbar 25-1, they are connected to the transfer control unit 14 in the same or a different system module.

On the other hand, the L1 crossbar 15 of the system module 1-1 is connected to the L2 crossbar 25-2 of the crossbar module 2 via the D bus 3-2, and the L1 crossbar 15 of the system module 1-2 is connected to the D bus It is connected to the L2 crossbar 25-2 of the crossbar module 2 via 3-2. That is, L1 in each system module
The crossbar 15 is connected to the L1 crossbar 15 in the same or a different system module via the D bus 3-2 and the L2 crossbar 25-2 of the L2 crossbar module 2.

The C bus 3-1 and the D bus 3-2 can transmit and receive data in the same system module 1-1, for example, when data transmission and reception are performed in the same system module 1-1. When data transmission / reception is performed between different system modules 1-1 and 1-2, for example, the C bus 3-1 and the D bus 3-2 are respectively connected to the transmission side system module 1-1 and the reception side. The data is transferred to and from the system module 1-2 on the side. C bus 3-
On 1, the control information is transferred in a control information packet (hereinafter, referred to as C packet) format which is a predetermined unit. D
On the bus 3-2, data is transferred in a data packet (hereinafter, referred to as a D packet) format which is a predetermined unit.

In each of the system modules 1-1 and 1-2, the transfer controller 14 outputs a command signal to the L1 crossbar 15 based on a transfer request. This command signal controls data input / output timing of the L1 crossbar 15 and the like. In the transmission-side system module, when the preparation for data transmission is completed, the transfer control unit 14 transmits one C packet including a header indicating the destination of the packet, and simultaneously transmits a data input command and a D packet header to the L1 crossbar 15. Outputs information as command signals. Then, the L1 crossbar 15 generates and outputs one D packet corresponding to the one C packet from the input data and the header information of the command signal. Accordingly, the transfer controller 14 of the system module on the transmitting side sends the C bus 3
One C packet output to -1 precedes the corresponding one D packet output from the L1 crossbar 15 of the same system module to the D bus 3-2 in time.

As described above, the transfer control unit 14 in the transmitting-side system module can output the C packet ahead of the output of the D packet from the L1 crossbar 15 in the same system module by a certain cycle. For this reason, the transfer control unit 14 in the system module on the receiving side
However, D is added to L1 crossbar 15 in the same system module.
Before the packet arrives, a command signal for controlling the L1 crossbar 15 can be generated.
The data from one crossbar 15 is transferred to the target (CP
U, IO, memory).

By the way, in the present embodiment, in the case of the transfer without the data transfer, the notification can be made without obstructing the transfer with the data transfer. Here, the transfer without data transfer (hereinafter referred to as “replier ion transfer”) means a data error notification, an invalidation completion notification,
Including a data output permission notification and the like, such a lip re-ion transfer is performed using only the C bus 3-1. The data error notification is for notifying that an error has occurred in the data. The invalidation completion notification notifies that the invalidation of data in the cache memory of the processor has been completed, and the data output permission notification is notified as a measure for correcting data concentration.

In the present embodiment, attention is paid to the fact that the consumption cycle of the C bus 3-1 is generally smaller than the consumption cycle of the D bus 3-2. For example, one C packet transferred on the C bus 3-1 has two cycles, and the D bus 3-2
If one D packet transferred above has 5 cycles,
An empty space for three cycles is generated on the C bus 3-1. Therefore, using the vacant space for three cycles on the C bus 3-1, the re-priority transfer without the D packet is performed. That is, in the case of data transfer, the C packet is transferred on the C bus 3-1 and the D packet is transferred on the D bus 3-2.
Transfer on top. On the other hand, in the case of transfer without data transfer, a replies-only packet (hereinafter, referred to as an R packet)
On the C bus 3-1.

FIG. 5 is a diagram showing the bit configuration of the C packet. In the figure, the 1τth and 2τth indicate the first cycle and the second cycle of the C packet, respectively. The node ID is an ID indicating a group when a plurality of system modules are grouped, and the slot ID is an ID indicating each system module. The buffer type indicates a buffer configuration in the L1 crossbar 15, and the port (Port) I
D is an ID indicating an IO port. Reply type 1
Indicates an invalidation completion notification, and the reply type 2 indicates a data error notification or a data output permission notification. The master SB indicates the request source system module that has issued the transfer request. The data transfer amounts # 1 and # 2 are
Indicates the data size of the C packet. For example, if both the data transfer amounts # 1 and # 2 are 1, it indicates that the data size is 64 bytes.

Therefore, both the data transfer amounts # 1 and # 2 are 0
Indicates that the data transfer amount field is 0 bytes. In this case, it is a replies-only transfer, that is, an R packet. FIG. 6 is a diagram showing a C packet and an R packet transferred on the C bus 3-1 and a D packet transferred on the D bus 3-2. In the figure, the horizontal axis indicates time, and for a two-cycle (2τ) C packet (CC), a corresponding D packet of five cycles (5τ) after a delay of four cycles (4τ) from the start of the C packet (D
DDDD) is transferred. On the other hand, for an R packet (RR) of two cycles (2τ), no corresponding D packet exists and is not transferred.

FIG. 7 is a diagram for explaining the priority of packets. 6, the same parts as those of FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted. In this embodiment, the C bus 3-
1, the output priority of the C packet of the transfer accompanied by the data transfer is set higher than the output priority of the R packet of the lip re-ion transfer without the data transfer.

Therefore, in the case indicated by A in FIG. 7, the R packet occurs earlier than the C packet, but when the C packet occurs, the output of the R packet is stopped and the output of the C packet is stopped. Is given priority, and when the output of the C packet is completed, the remaining portion of the R packet is output. In the case indicated by B in the figure, since the R packet and the C packet occur simultaneously, the output of the C packet is given priority first, and the R packet is output when the output of the C packet is completed. Also, in the case indicated by C in the figure, although the C packet is generated before the R packet, the output of the R packet is not performed at the time when the R packet is generated. The R packet is output when the output of the C packet is completed.

In any of the above cases A to C,
The transfer interval of one C packet on the bus 3-1 is equal to the transfer interval of the D packet on the D bus 3-2, that is, 5 cycles (5τ). Therefore, in the case of a transfer involving data transfer, the transfer on the C bus 3-1 always precedes the transfer on the D bus 3-2 by a certain cycle.
It is kept constant regardless of the generation timing of the packet and the R packet.

FIG. 8 is a flowchart for explaining the operation of the arbitration unit 31 of the first embodiment. The process shown in FIG. 13 corresponds to the operation in the arbitration unit 31, particularly the operation related to the C arbitration circuit 31C and the R arbitration circuit 31R. In FIG. 8, when a transfer request is generated, a step S1 determines whether or not the transfer request involves data transfer. If the decision result in the step S1 is YES, a step S2 generates a C packet, and a step S3 decides whether or not the data transfer is a transfer to an external system module. On the other hand, if the decision result in the step S1 is NO, a step S4 decides R
A packet is generated, and step S5 determines whether the data transfer is a transfer to an external system module.

If the decision result in the step S3 is YES, a step S6 decides whether or not the output of the C packet to the external system module is permitted in the C arbitration circuit 31C, and the decision result is YES. If there is, the step S7 outputs the C packet to the external system module, and the transfer processing in the external system module is continued. On the other hand, if the determination result of step S3 is NO
In step S8, the arbitration circuit for C 31C determines whether the output of the C packet within the system module is permitted. If the determination result is YES,
A step S9 outputs the C packet to the inside of the system module, and the transfer processing inside the system module is continued.

If the decision result in the step S5 is YES, a step S11 decides whether or not the output of the R packet to the external system module is permitted in the R arbitration circuit 31R, and the decision result is YES. If there is, the process proceeds to step S12. A step S12 outputs the R packet to the external system module, and a step S13 determines whether or not the C packet is being output to the external system module. Step S1
If the decision result in 3 is NO, the transfer processing in the external system module is continued. On the other hand, step S5
Is NO, the step S14 decides whether or not the output of the R packet in the system module is permitted in the arbitration circuit for R 31R, and if the decision result is YES, the process proceeds to the step S14. Proceed to S15. A step S15 outputs the R packet to the inside of the system module, and a step S16 determines whether or not the C packet is being output to the inside system module. If the decision result in the step S16 is NO, the transfer process inside the system module is continued.

Next, a description will be given of a second embodiment of the multiprocessor system according to the present invention. The basic configuration of this embodiment is
This is the same as the basic configuration of the first embodiment described with reference to FIGS. FIG. 9 shows a second example of the multiprocessor system.
It is a block diagram showing composition of an important section of an example. In the figure,
1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. A second embodiment of the multiprocessor system comprises:
A second embodiment of the data transfer method according to the present invention is employed.
The present embodiment is characterized by data transfer in the system module after the above-described address advertisement and cache information advertisement are performed, that is, after data transfer preparation is completed.

The transfer control unit 14 in the system module shown in FIG. 9 has a destination determination unit 35 and a data buffer unit 36 in addition to an arbitration unit 31 and a data arrival determination circuit 32 (not shown). The destination determining unit 35 determines whether the destination of the C packet to be transferred is in the system module,
Alternatively, it is determined whether the module is an external system module. Specifically, the node I in the C packet shown in FIG.
The destination of the C packet is determined by looking at the D and the slot ID. The C packet to be transferred into the system module is supplied to the buffer unit 36. On the other hand, the C packet to be transferred to the external system module is transmitted to the L bus in the crossbar module 2 via the C bus 3-1.
It is supplied to the two crossbars 25-1. That is, the C packet to be transferred in the system module is transferred in the transfer control unit 14 without passing through the L2 crossbar 25-1.

The buffer unit 36 includes buffers 361, 361-1 to 361-4 for buffering C packets transferred in the system module, and a C packet from an external system module to the L2 crossbar 25-.
And buffers 362, 362-1 to 362-3 for inputting and buffering the data through the I.I. The buffer 361 determines whether a packet coming into the system module is a C packet or an R packet based on the data transfer amount of the C packet. holds the packet R _iN, buffer 361-4 maintains the C packet C _iN. R _IN is the value of R transferred within the same system module.
C _IN indicates a C packet transferred within the same system module.

The buffer 362 determines whether a packet coming from the external system module is a C packet or an R packet based on the data transfer amount of the C packet. 2 is R
While holding the packet R _OUT , the buffer 362-3
Holds the C packet C _OUT . R _OUT indicates an R packet transferred between different system modules, and C _OUT
OUT indicates a C packet transferred between different system modules.

The packets from the buffer section 36 are output to the data arrival determination circuit 32 in one cycle by combining one packet (two cycles). Thus, the C packet to be transferred in the system module is the L2 crossbar 2
Since the transfer is performed in the transfer control unit 14 without passing through the 5-1, the high-speed transfer becomes possible because the distance of the physical path is shorter than that in the case of passing through the L2 crossbar 25-1.

Data arrival determination circuit 3 from buffer unit 36
2 is equal to the L2 crossbar 25-1.
Or more than the sum of the packet outflow amount PQ2 and the packet inflow amount PQ3 in the transfer control unit 14, that is, PQ1 ≧ PQ2 + PQ
3. In this embodiment, a fixed priority is set for the transfer order of the C packet and the R packet. As for the priority of the packet, the priority of the C packet C _OUT transferred between different system modules is YC _OUT , the priority of the C packet C _IN transferred in the same system module is YC _IN , and the transfer is performed between different system modules. R
The priority of the packet R _OUT is YR _OUT , and the priority of the R packet R _IN transferred in the same system module is Y
When represented by R _IN , it is set so as to satisfy YC _OUT > YC _IN > YR _OUT > YR _IN . The delay in the buffer unit 36, that is, the number of stages of the buffer for each packet type is determined based on the packet flow for each of the priorities.

Therefore, in this embodiment, the transfer within the system module and the transfer to the external system module are
Particularly, transfer within the system module can be performed at high speed without limiting transfer. Next, the operation of the buffer unit 36 of the present embodiment will be described with reference to FIGS. In FIGS. 10 to 13, the first cycle,
Is the second cycle, ■ is the R packet output suspension period for using the C bus 3-1 and “C out” is the buffer unit 3
6 shows the output from FIG.

Since the C packet C _OUT transferred to the external system module has the highest priority, the output of the C packet C _OUT is not affected by other packets. Therefore, the first cycle of the C packet C _OUT is buffered by the buffer 362-3, and the second cycle is output through. Therefore, as shown in FIG. 10, for the C packet C _OUT , it is understood that the number of stages of the buffer is one and one cycle is required.

In the case of the C packet C _IN transferred in the system module, the first cycle is buffered by the buffer 361-4, and if an output packet competes with the C packet C _OUT , it is delayed by one cycle. On the other hand, C packet C _IN
, The next C packet C _IN does not come in. Therefore, as shown in FIG. 11, it is understood that the number of stages of the buffer is one and two cycles are necessary for the C packet C _IN .

The R path transferred to the external system module
Ket R_OUT, C packet C _OUTAnd C packet C
_INSince the transfer interval is once every five cycles,
R _OUTMay be delayed by 2 cycles during 5 cycles
You. Also, R packet R_OUTDuring the output of the next R packet
R_OUTThe first cycle comes in. Therefore, the R packet
R_OUTAre buffered in buffers 362-1 and 362-2.
Ring. That is, R packet R_OUTAgainst the figure
As shown in Fig. 12, the number of buffer stages is 2 and 3 cycles
It turns out that it takes minutes.

In the case of the R packet R _IN transferred in the system module, since the transfer interval between the C packet C _OUT and the C packet C _IN is once every five cycles, the R packet R _IN
IN may be delayed by two cycles during seven cycles. At this time, since the output of the R packet R _OUT is a maximum of two packets in seven cycles, the R packet R _IN may be delayed by two cycles in seven cycles. Also, R packet R
Even during _IN output of the first cycle of the next R packet R _IN is incoming. Therefore, the R packet R _IN is stored in the buffer 361.
Buffering is performed at -1 to 361-3. That is, as shown in FIG. 13, for the R packet R _IN , it is understood that the number of stages of the buffer is three and five cycles are required.

In the case described above, the maximum flow rate of packets during eight cycles is obtained as shown in FIG.
In the figure, the unit of the numerical value indicates a cycle. Also, * 1 to * 8
The upper numerical values are obtained as follows. * 1: 8- _CIN output x 2 = 6 * 2: 8- _COUT output x 1- _CIN output x 2 = 5 * 3: 8- _COUT output x 2- _CIN output x 2 = 4 * 4 : 8-C _OUT out x 2 = 6 * 5: 8-C _OUT out x 2 = 6 * 6: 8-C _OUT out x 2-R _OUT out x 2 = 4 * 7: 8-C _OUT out x 2 -R _OUT output x 2-C _IN output x 1 =
3 * 8: 8-C _OUT out x 2-R _OUT out x 2-C _IN out x 2 =
2 Next, transfer of the D packet in the present embodiment will be described. FIG. 15 is a block diagram showing a configuration of a main part of the present embodiment, and shows a part related to transfer of a D packet. In the figure, the same parts as those in FIGS. 1 to 4 and 9 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 15, the L1 crossbar 15 includes a control circuit 151 and a buffer unit 152. The control circuit 151 generates a multiplexer select signal, an IO enable signal, and a buffer control signal to be supplied to the buffer unit 152 based on a command signal from the transfer control unit 14. The buffer unit 152 includes a multiplexer and a buffer connected as shown for each processor, each IO port, and each memory in the same system module. For convenience, the multiplexer is indicated by a vertical double line, and the buffer is indicated by ■ in FIG. The multiplexer at the output stage in the L1 crossbar 15 is connected to the L2 crossbar 25-2 via the D bus 3-2.
It is connected to the.

In this embodiment, when the D packet is transferred in the system module, the D packet is transferred in the L1 crossbar 15 without being output from the L1 crossbar 15 to the L2 crossbar 25-2. More specifically, when the D packet is transferred within the system module, the control circuit 151 performs a multiplexer select for transferring the D packet within the L1 crossbar 15 based on a command signal from the transfer control unit 14. Signal, an IO enable signal, and a buffer control signal, and
Feed to 2.

FIG. 16 is a diagram showing the configuration of the L1 crossbar 15 of this embodiment, and FIG. 17 is a diagram for explaining the transfer of a D packet in the system module. 16 and 17, the L1 crossbar 15 in the system module 1 is
The L1 crossbar 15 is shown as a group of switches arranged in an array so that the function of FIG. Therefore, the signal from the control circuit 151 has an image of controlling on / off of each switch of the switch group. When transferring a D packet in the same system module 1, the switch group is controlled so that the D packet passes through a return section 155 surrounded by a thick line in the L1 crossbar 15 in FIG. The return section 155 is provided with a return path 155A. As a result, the D packet from a certain processor in the system module 1 passes through the return unit 155 in the L1 crossbar 15 as shown by a thick arrow in FIG.
The data is transferred without passing through the crossbar 25-2. In FIG. 17, the switch that is turned on is indicated as on.

As described above, in this embodiment, a packet transferred within one system module must pass through the L2 crossbar 25-1 or 25-2 regardless of the packet type (C packet or D packet). And can be transferred at high speed within the system module. As described above, the present invention has been described with reference to the embodiments. However, it is needless to say that the present invention is not limited to the above embodiments, and various modifications and improvements can be made within the scope of the present invention.

[0047]

According to the present invention, a multiprocessor system and a data transfer method capable of performing data transfer at high speed and with high efficiency even when the number of processors is increased and the multiprocessor system is enlarged. Can be realized.

[Brief description of the drawings]

FIG. 1 shows a first example of a multiprocessor system according to the present invention.
It is a block diagram showing a schematic structure of an example.

FIG. 2 is a block diagram illustrating a configuration of a system module according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a crossbar module according to the first embodiment.

FIG. 4 is a block diagram showing a configuration of a main part of the first embodiment.

FIG. 5 is a diagram illustrating a bit configuration of a C packet.

FIG. 6 is a diagram showing a C packet and an R packet transferred on the C bus and a D packet transferred on the D bus.

FIG. 7 is a diagram for explaining the priority order of packets.

FIG. 8 is a flowchart illustrating the operation of the arbitration unit of the first embodiment.

FIG. 9 shows a second example of the multiprocessor system according to the present invention.
It is a block diagram showing composition of an important section of an example.

FIG. 10 is a diagram for explaining an operation in the buffer unit of the second embodiment.

FIG. 11 is a diagram for explaining an operation in the buffer unit of the second embodiment.

FIG. 12 is a diagram for explaining an operation in the buffer unit of the second embodiment.

FIG. 13 is a diagram for explaining an operation in the buffer unit of the second embodiment.

FIG. 14 is a diagram for explaining the maximum flow rate of packets during eight cycles.

FIG. 15 is a block diagram illustrating a configuration of a portion related to transfer of a D packet according to the second embodiment.

FIG. 16 is a diagram illustrating a configuration of an L1 crossbar according to a second embodiment.

FIG. 17 is a diagram illustrating transfer of a D packet in a system module.

[Explanation of symbols]

 1-1 to 1-N System module 2 Crossbar module 3 Bus 11-1 to 11-M Processor 14, 21 Transfer control unit 15 L1 crossbar 25-1 to 25-2 L2 crossbar

Claims (5)

[Claims] 1. A system comprising: a plurality of system modules each including a plurality of processors, a transfer control unit, and a first crossbar; and a crossbar module including a second crossbar connecting the plurality of system modules. The microprocessor system, wherein when performing transfer within one system module, the transfer control unit transfers the control information packet internally without passing through the second crossbar. 2. The multiprocessor system according to claim 1, wherein the transfer control unit also transfers a replies-only packet for notifying a replies-free transfer without data transfer. 3. The transfer control unit according to claim 2, wherein the priority of transfer of the control information packet transferred from outside the arbitrary one system module is YC _OUT , and the control information packet transferred within the arbitrary one system module is Transfer priority YC _IN , transfer priority YR _OUT of transfer of the replies from outside the arbitrary one system module, and transfer of lip re-ion Lee packets transferred within the arbitrary one system module 3. The multiprocessor system according to claim 2, wherein the priority order YR _IN is set and buffered so as to satisfy a relationship of YC _OUT > YC _IN > YR _OUT > YR _IN . 4. The system according to claim 1, wherein the first crossbar has a return unit for internally transferring a data packet without passing through the second crossbar when performing transfer within the one arbitrary system module. The multiprocessor system according to any one of claims 1 to 3. 5. A multiprocessor system in which a plurality of system modules each including a plurality of processors, a transfer control unit, and a first crossbar are connected via a crossbar module including a second crossbar. A transfer method, comprising: transferring a control information packet and a data packet internally without passing through the second crossbar when transferring in any one system module.