JP2001166965A - Failure analyzing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily analyze a failure generated for the first time, and to operate highly precise failure site specification corresponding to each detected defective part even when plural defective parts are present without repairing any defective part or invalidating any failure detector. SOLUTION: At the time of detecting any failure, any failure detector 104-106 provided in a processor 100 bolds the failure information, and informs a diagnosing device 200. The diagnosing device 200 checks the failure information, and suppress the output from the failure detector at the time of detecting the defective part for releasing the held state of the failure information, and accepts failure information to be generated next.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault analysis circuit used for fault processing in information processing, and more particularly to performing a fault analysis corresponding to each fault when a plurality of faults are detected during operation. The present invention relates to a failure analysis circuit capable of performing the above.

[0002]

2. Description of the Related Art A conventional fault analysis circuit includes a processor,
And a diagnostic device for performing a failure analysis when a failure occurs in the processor. As a specific example of a conventional failure analysis circuit, an “information processing device” is disclosed in Japanese Patent Laid-Open No. Hei 5-73351.

[0003] The operation of the "information processing apparatus" disclosed in Japanese Patent Laid-Open No. Hei 5-73351 will be described. When a fault occurs during the operation of the processor, a fault detector provided corresponding to the fault location detects the fault and outputs "1" as a fault signal. Due to this output, the output of each fault detector is held and output as fault information in the processor, and a fault that has occurred in the processor is reported to the diagnostic device. Then, when receiving the fault report from the processor, the diagnostic device reads the fault information held in the processor, performs a fault analysis based on the fault information, and points out the fault location.

[0004]

However, in the "information processing apparatus" disclosed in Japanese Patent Application Laid-Open No. Hei 5-73351, a location where a failure has occurred is specified first, and then a failure detected from another location is identified. In order to analyze the location, a method of invalidating the output of the failure detector corresponding to the location where the failure first occurred has been adopted. For this reason, it was not possible to determine again whether or not a failure has occurred again at the location where the failure first occurred.

As described above, in the conventional fault analysis circuit, even if there are a plurality of locations that cause a fault, once the fault is detected, the fault information is held, and when the fault is reported, the diagnostic apparatus performs the following steps. Since it is necessary to specify one suspicion, other failure information detected later cannot be accepted, and other failure information cannot be detected. Alternatively, in order to detect other fault information, it is necessary to repair the fault location once detected or to disable the fault detector.

As another method, for a place where a failure has occurred once, it is predicted that the failure will be detected again first, and the output of the failure detector corresponding to the failure place is invalidated. Therefore, if a failure is detected at a location other than the known portion, it is not possible to distinguish whether or not this failure has occurred due to the portion that suppressed the output of the failure detector. There is a problem that the failure analysis cannot be performed flexibly and the resolution of the failure analysis deteriorates.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and enables the first failure to be easily analyzed during a normal operation or an operation test of a processor chip. Alternatively, there is provided a failure analysis circuit which does not invalidate a failure detector and can specify a highly accurate failure portion corresponding to each detected failure portion even when a plurality of failure portions exist. With the goal.

[0008]

In order to achieve the above object, the invention according to claim 1 has a processor for executing a software instruction, and a diagnostic unit for analyzing a fault that has occurred in the processor. A plurality of registers for temporarily holding data according to the operation purpose, a failure detection means provided in correspondence with the plurality of registers to detect a failure occurring in each register and output failure information, and an input from the failure detection means. A fault information register that holds the fault information in each part and outputs a signal, and when a fault report based on the output signal from the fault information register is input from the processor, the state of all the fault information registers at the time of fault occurrence In a fault analysis circuit in which the diagnosis means analyzes a fault location of the processor based on the fault information holding the plurality of registers, the diagnosis means includes a plurality of registers. If one of them is analyzed as a fault location, the output of the signal from the fault information register corresponding to the analyzed fault location is suppressed, and the fault information register uses the fault report as the status holding signal of all fault information registers, The output of the signal from the fault information register is suppressed by the diagnostic means, so that the portion of the fault information register which is set as the target of the fault report suppression is kept in the data holding state, and the fault information is not held. The part can be accepted and a failure report can be made.When executing other software instructions, if the known failure recurs by resetting the processor to the known failure part only after initializing the processor, the failure will still occur. The method is characterized in that information is retained but a known failure is not reported, and another failure is received and a failure report is made.

According to a second aspect of the present invention, in the first aspect of the invention, an AND gate having an output signal from the fault information register as one input is provided corresponding to each part of the fault information register. From the part where the failure information is held, 1 is output to one input terminal of the AND gate.
By analyzing the gate and outputting 0 to the other input terminal of the analyzed AND gate, the output of the signal corresponding to the fault location by the fault information register is suppressed.

According to a third aspect of the present invention, in the second aspect of the invention, the processor is provided with an OR gate which receives an output signal from each AND gate as an input.
When one signal is input to the OR gate from any of the D gates, the OR gate outputs 1 to the diagnostic means as a failure report from the processor, and specifies the first suspected cause of the failure. It is characterized in that all states of the failure information register at the time of occurrence of a failure are held.

According to a fourth aspect of the present invention, in the first aspect of the present invention, when the failure report is input from the processor, the diagnostic means is configured to execute all failure information held from the failure information register. Is read using a scan path.

According to a fifth aspect of the present invention, in the invention of any one of the first to fourth aspects, a failure report at a location found by collecting information after the occurrence of the failure is suppressed by control from the diagnostic means. The fault information register is set to a state in which reception and a fault report are possible, and normal fault analysis is performed for a portion other than a known fault portion.

According to a sixth aspect of the present invention, in the first aspect of the present invention, the fault analysis circuit is configured to include one diagnostic means for a plurality of processors. I do.

[0014]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a failure analysis circuit according to an embodiment of the present invention. According to FIG. 1, the fault analysis circuit comprises a processor 1 for executing software instructions.
00 and a diagnostic device 200 that analyzes a fault that has occurred in the processor 100.

The processor 100 includes a plurality of registers (registers 101 to 103 in this embodiment) for temporarily storing data according to the operation purpose, and registers 101 to 103.
103 and registers 101 to 103
A plurality of fault detectors 10 for detecting a fault occurring in 103
4 to 106 and a fault information register 107 for holding fault information detected by the fault detectors 104 to 106.

The fault analysis circuit is used as a signal line connecting the above-mentioned components and between the processor 100 and the diagnostic device 200 when a fault occurs in any of the plurality of resistors 101 to 103. A signal path 123 used to transmit information to the diagnostic apparatus 200 and to set the failure information register 107 in a data holding state by inputting the transmission signal;
By transmitting the output signal from the fault information register 107 corresponding to the error information register 03, the fault information register 107 itself holds the fault information corresponding to each of the registers 101 to 103 and transmits the individual fault information. Signal paths 120 to 122.

Further, in the prior art, an AND gate is provided on the input side of the fault information register 107 to suppress a fault report, and the logical sum of a fault detection signal and a control signal is input to the fault information register. The input of the fault detection signal to the fault information register is suppressed in response to the control signal. On the other hand, as a characteristic configuration of the present invention, an AND gate 1 is provided on the output side of the fault information register 107.
08 to 110, the output of the fault information from the fault information register 107 is suppressed.

In each of the AND gates 108 to 110, after the fault information is individually held in the fault information register 107,
Signals output from the fault information register 107 to the signal paths 120 to 122 and signals output from the diagnostic device 200 to the signal paths 201 to 203 for suppressing fault information are input. The OR gate 111 receives, as inputs, the signals that have been ORed by the respective AND gates 108 to 110, and the diagnostic device 200 receives, from the OR gate 111, a signal that is the logical product of the above signals.

Here, the output signals from the AND gates 108 to 110 are handled as individual fault reports from the fault detectors 104 to 106, and the output signals from the OR gate 111 are output from the fault detectors 104 to 106. It is an overall failure report that indicates that a failure has occurred in any of the 106, and is treated as a signal for holding the state of all the failure information registers for the purpose of identifying the first suspect.

When the fault information is input from the signal path 123, the diagnostic apparatus 200 reads out all the fault information held from the fault information register 107 by using the scan path 124, and identifies a fault location based on the read contents. It has a means for detecting and a means for outputting a control signal to the signal paths 201 to 203 in order to suppress the output of the fault information from the fault information register 107 which has finished detecting the fault location.

Next, the operation of the fault analysis circuit according to the present embodiment will be described in detail. The processor 100 is a processor for executing software instructions. During operation, the registers 101 to 103 temporarily hold data according to the operation purpose of the device. Fault detector 1
04 to 106 correspond to the respective registers 101
The data set to ３103 are checked, and “1” is output when a failure is detected.

Each information output from the failure detectors 104 to 106 is held in the failure information register 107, respectively. AND gates 108-110 are connected to signal paths 120-
122 and the signal paths 201 to 203 are input, and if the “1” signal is held in the fault information register, the corresponding AND gates 108 to 110 are output from the fault information register 107 via the signal paths 120 to 122. Is input to the processor 100 and the processor 100 is operating normally, the diagnostic device 20 via each signal path 201-203.
From “0”, “1” is input to each of the AND gates 108 to 110.

Here, during the operation of the processor 100, for example, if there is a fault in the register 101, the fault detector 104 detects the fault and outputs "1". This "1" signal is set in the failure information register 107.
The output signal from each flip-flop in the fault information register 107 becomes a state holding signal of the fault information register 107 itself, and is an output signal to the AND gate 108. Is input. The other input of the AND gate 108 is connected to the diagnostic device 2 via the signal path 201.
Since "1" is input from 00, the AND gate 108
Takes the logical sum of both inputs and sets the output to "1".

The OR gate 111 has an AND gate 108
, The output from the OR gate 111 is “1”. This “1” signal is transmitted to the diagnostic device 20
This signal is a signal for outputting a fault report to 0 and for putting the fault information register 107 in a data holding state. Here, when “1” is input to the failure information register 107 via the signal path 123, all information set in the failure information register 107 at the time of occurrence of a failure, that is, information indicating that a failure has occurred in the register 101 , The failure-free information for the register 102 and the failure-free information for the register 103 are held in the fault information register 107 as a data holding state.

At the same time, the output signal “1” from the OR gate 111 is input to the diagnostic device 200 via the signal path 123 as fault information. Thereby, the diagnostic device 200
Reports that a failure has occurred in any of the registers 101 to 103. When a failure report is input from the processor 100, the diagnostic device 200 reads out all the failure information held from the failure information register 107 in the data holding state using the known scan path 124, and then performs failure analysis. Start the application program.

In the diagnostic apparatus 200, when the failure analysis program is started, a failure location in the processor 100 is analyzed and indicated based on the read failure information in the failure information register 107. When pointing out the fault location as the register 101, the diagnostic device 200 changes the signal output to the AND gate 108 from "1" to "0". As a result, the output from the AND gate 108 becomes “0”, and no failure report is output from the OR gate 111 to the diagnostic device 200. At the same time, each part of the fault information register has a flip-flop,
The cause of the data holding state of the failure information register 107 is also eliminated, and in the failure information register 107, a part that does not hold the failure information is changed from the data holding state to a state where reception and failure reporting are possible.

In other words, by suppressing the failure information output when a failure occurs in the register 101, even if a failure occurs in the register 101 in which the failure is predicted again, the corresponding portion of the failure information register 107 can be used. The data of the failure information is held, but the other registers 102, 1
In 03, a data holding state is not established, and a failure that occurs at another location next time can be detected.

In this embodiment, the operation of the failure analysis circuit during the operation of the information processing apparatus has been described as an example. However, the same effect can be obtained in the case of the same operation such as a test of an integrated circuit alone. .

Further, as another embodiment of the present invention, for example, a configuration in which one diagnostic device is provided for a plurality of processors respectively provided in a plurality of LSIs,
Alternatively, even when there are a plurality of processors in the same LSI, it is possible to easily adopt a configuration in which one diagnostic apparatus can cope with the case.

[0031]

As is apparent from the above description, according to the present invention, when the failure detector outputs a failure signal during the operation of the information processing apparatus, all the failure information is not held. Even if there are many fault locations in the processor, fault analysis can be performed flexibly in response to the detected fault locations, and highly accurate fault analysis and improvement in resolution of the fault analysis can be achieved.

Further, according to the present invention, when the same operation is performed not only during the operation of the information processing apparatus, for example, a similar effect can be obtained in a test or the like of an integrated circuit alone.

[Brief description of the drawings]

FIG. 1 is a block diagram of a failure analysis circuit according to an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 processor 101 to 103 register 104 to 106 fault detector 107 fault information register 108 to 110 AND gate 111 OR gate 120 to 122, 123, 201 to 203 signal path 124 scan path 200 diagnostic device

Claims (6)

[Claims] 1. A processor for executing a software instruction, and a diagnostic unit for analyzing a fault occurring in the processor, the processor comprising: a plurality of registers for temporarily holding data according to an operation purpose; Fault detecting means provided corresponding to each of the registers for detecting a fault occurring in each of the registers and outputting fault information; and a fault for holding the fault information input from the fault detecting means in each part and outputting a signal. Information register, when a failure report based on an output signal from the failure information register is input from the processor, based on the failure information that holds the state of the failure information register when a failure occurs In the failure analysis circuit, wherein the diagnosis unit analyzes a failure location of the processor, the diagnosis unit may include any one of the plurality of registers. Is analyzed as a failure location, the output of a signal from the failure information register corresponding to the analyzed failure location is suppressed, and the failure information register uses the failure report as a state holding signal of the all failure information registers. The output of the signal from the fault information register is suppressed by the diagnostic means, so that the portion of the fault information register which is the target of the fault report suppression is continuously set in the data holding state, A part that does not hold information is set to a state in which reception and a failure report are possible, and when executing another software instruction, after the processor is initialized, only the known failure part is set to a failure report suppression state. Even if a fault recurs, it will be kept as fault information but will not report a known fault but will accept another fault and report a fault. A failure analysis circuit characterized in that the failure analysis circuit can 2. An AND gate which receives an output signal from the fault information register as one input is provided corresponding to each part of the fault information register. One is output to one input terminal of the AND gate, and the diagnostic means outputs the one.
By analyzing the AND gate to which the signal is input and outputting 0 to the other input terminal of the analyzed AND gate, the output of the signal corresponding to the fault location by the fault information register is suppressed by the fault information register. The fault analysis circuit according to claim 1, wherein: 3. The processor includes an OR gate that receives an output signal from each of the AND gates, and when one signal is input to the OR gate from any of the AND gates, From the OR gate, 1 is output to the diagnostic means as the fault report from the processor, and all states of the fault information register at the time of the fault occurrence are held to identify the first suspected cause of the fault. The fault analysis circuit according to claim 2, wherein 4. The diagnostic means according to claim 1, wherein, when the failure report is input from the processor, all the failure information held from the failure information register is read using a scan path. 4. The fault analysis circuit according to any one of claims 1 to 3. 5. A method according to claim 5, wherein said fault report is suppressed by control of said diagnostic means at a location found by collecting information after a fault has occurred, so that said fault information register can be received and reported. 5. The failure analysis circuit according to claim 1, wherein a normal failure analysis is performed. 6. The fault analysis circuit according to claim 1, wherein the fault analysis circuit includes one diagnostic unit for a plurality of processors.