JP2001160293A - Writing and erasing method for data in semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dissolve such problems that pattern area occupied by drivers is increased, wafer process is made long, and memory size is increased in the case of using high breakdown voltage transistor. SOLUTION: In a semiconductor memory provided with plural memory cells constituted of transistors to which first power source voltage and second power source voltage being lower than the first power source voltage are given and which have a floating gate and a control gate arranged at the upper side of a floating gate, by applying voltage being higher than the first power source voltage to the control gate and applying voltage being lower than the second power source voltage to a source or a drain of a transistor, electrons are injected to a floating gate, and data written in plural memory cells are erased en bloc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Particularly, electrically erasable and programmable non-volatile memory, E ² PROM (Electrically Erasable and Progra
mable ROM).

[0002]

2. Description of the Related Art A read-only memory (E ² PROM) capable of electrically erasing / writing using a Fowller-Nordheim (hereinafter abbreviated as FN) tunnel current has also entered the megabit era due to advances in semiconductor technology. I am trying to do. In order to be widely used in the field of external storage in the future, higher integration and lower cost are required.

However, most of the memory cells currently used in the E ² PROM obtain an FN tunnel current for erasing / writing within a certain period of time, so that the voltage is lower than the voltage used in a general semiconductor integrated circuit. A considerably high voltage is used (a general semiconductor integrated circuit operates at 5 V, whereas an E ² PROM requires a voltage of 16 to 20 V).

For this reason, compared with transistors used in general semiconductor integrated circuits, the junction withstand voltage is increased, and the junction is made deep to reduce the electric field of the gate oxide film. Many transistors must be used, and E ² PRO
There is a current situation that high integration of M does not progress as compared with other semiconductor memory devices.

Hereinafter, three examples of the prior art will be described. References are ISSCC89 (1989-2-16)
Proceedings P132-133 and JP-A-59-5494.

In the following description, FIGS.
3A to 3D are diagrams respectively showing a circuit configuration diagram, FIGS. 3B and 3C show cross sections of a main structure of a memory cell portion, and FIG. 3B shows a state in the case of erasing. , (C) is a diagram for explaining the state in the case of writing,
(D) is a diagram for explaining the potential relationship of each part in erasing and writing.

(1) Description of Conventional Example 1 FIG. 2 shows erasing (ERASE) by FN tunnel current.
This is a conventional example in which a two-transistor type memory cell using a floating gate type non-volatile memory having a stacked electrode for performing write / write and a batch erase type E ² PROM which can be erased in word line units is provided. This shows the operation of the memory cell. Hereinafter, the configuration of this example and the operation of the memory cell will be described.

The memory cell has a tunnel window type floating gate MOS transistor (hereinafter abbreviated as FLOTOX transistor) in which a tunnel oxide film is formed in a partial region below the floating gate, and a high voltage transistor for selecting a bit. The FLOTOX transistor and the select transistor are connected in series.

FIG. 5 shows the potential difference between the control gate electrode of such a FLOTOX transistor and the diffusion layer electrode in which the tunnel window is formed.
4 shows the relationship with the threshold voltage of an X transistor.

As can be seen from FIG. 5, there is a change in the threshold voltage when erasing and writing are performed at a potential difference of 15 V or more. That is, a tunnel current is generated when the voltage difference is about 15V.

In this conventional example, the potential difference between the control gate electrode and the diffusion layer electrode is set to 18
V is set.

Although a (2 × 2) minimum matrix structure is described here as an example, it will be readily understood that the following discussion can be directly extended to larger matrix structures.

(A) As shown in FIG.
12, 21, 22 are arranged in a matrix, and these memory cells, select lines SL1, SL2, and word line WL
1, WL2, bit lines BL1, BL2 and source line A
S1 and AS2 are connected as follows.

Select line SL1 is connected to the gates of select transistors of memory cells 11 and 12, and select line SL2 is connected to the gates of select transistors of memory cells 21 and 22.

Word line WL1 is connected to memory cells 11 and 1
2 FLOTOX transistor, and the word line WL2 is connected to the memory cells 21 and 22.
Is connected to the control gate of the FLOTOX transistor.

Bit line BL1 is connected to memory cells 11 and 2
The bit line BL2 is connected to the drains of the select transistors of the memory cells 12 and 22.

Source line AS1 is connected to memory cells 11 and 1
2 is connected to the source of the FLOTOX transistor 2 and the source line AS2 is connected to the FLOTOX of the memory cells 21 and 22.
Connected to the source of OX transistor.

The erasing and writing operations will be described below.

(A) Case of Performing Erase (ERASE) (See Figures (a), (b) and (d)) A case of selecting and erasing the memory cells 21 and 22 will be described.

The word line WL2 is set at 18V,
1 is biased to 0V.

The select lines SL1 and SL2 are turned on when the select transistor is turned on and the bit line and the FLO
The bias is biased to a voltage (5 V in this example) that is electrically connected to the drain of the TOX transistor, and both the bit lines BL1 and BL2 are biased to the reference voltage 0V.

The source lines AS1 and AS2 are in a floating state initially set to 0V.

At this time, the drain of the FLOTOX transistor is biased to the bit line potential 0 V via the select transistor.

Therefore, the control gate potential of the FLOTOX transistor is 18 V higher than the potential of the drain in which the tunnel window is formed.
FN tunnel current flows through the tunnel window, electrons are injected into the floating gates of memory cells 21 and 22, and erasing is performed.

On the other hand, since both the control gate and the drain of memory cells 11 and 12 have the same potential of 0 V, no FN tunnel current is generated and no erasing of the memory cells is performed.

(B) In case of writing (WRITE) (see FIGS. 7A, 7B and 7D) Here, a case where the memory cell 21 is selected and written will be described.

Both word lines WL1 and WL2 are biased to a reference potential of 0V.

The selected select line SL2 is biased to 20 V, and the unselected select line SL1 is set to the reference potential 0.
Biased to V.

The selected bit line BL1 is biased to 20V, and the unselected bit line BL2 is biased to the reference potential 0V.

The source lines AS1 and AS2 are initially in a floating state of 0V.

At this time, FLOTO of the selected memory cell 21
The drain of the X transistor has a voltage of 20 V-lower than the potential of the selected bit line BL1 by the threshold voltage V _TW (≒ 2 V) of the select transistor via the select transistor.
Biased to V _TW (≒ 18V).

Therefore, FLOTOX of memory cell 21
The drain potential of the transistor becomes 20V-V _TW (≒ 18V) higher than the control gate potential,
FN tunneling occurs, electrons are emitted from the floating gate to the drain, and writing to the selected memory cell 21 is performed.

On the other hand, an unselected memory cell (memory cell 22 in FIG. 2) on the selected line is connected to bit line BL2.
Is biased to 0 V, and since the control gate and the drain of the FLOTOX transistor are both at the same potential as 0 V, no FN tunnel current is generated and writing is not performed.

Further, unselected memory cells on unselected select line SL1 (memory cells 11 and 12 in FIG. 2)
Is FL because the select transistor is off.
The drain of the OTOX transistor is in a floating state.

At this time, the control gate is at 0 V. In this case, no FN tunnel current occurs and no writing is performed.

As described above, in this conventional example, F
In order to create a potential difference that generates a −N tunnel current between the control gate and the drain, in the case of erasing, F
By setting the drain of the LOTOX transistor to a reference voltage of 0 V and biasing the control gate with a voltage of a potential difference necessary to generate an FN tunnel current, the reference voltage is similarly applied to the control gate of the FLOTOX transistor in the case of writing. A method of biasing 0V and biasing a voltage of a potential difference necessary to generate an FN tunnel current at the drain is used.

At this time, the source of the FLOTOX transistor is in a floating state initially set to 0 V, and the substrate voltage is 0 V.

That is, the potential difference between the control gate and the drain of the FLOTOX transistor required to generate the FN tunnel current is V _Ea for erasing, V _{Wa for} writing, and the control gate, drain and source of the FLOTOX transistor. The applied potential is V
_Assuming that _G , V _D , V _S and the substrate voltage are V _BB , V _GD = V _G −V _D = V _Ea −0 = V _Ea V _BB = 0V for erasing V _DG = V _D −V _{G for} writing = V _Wa −0 = V _Wa V _BB = 0V

(2) Description of Conventional Example 2 FIG. 3 shows erasing by FN tunnel current (ERASE).
This operation is shown in a conventional example in the case where a batch erase type E ² PROM capable of erasing in units of word lines is configured by a transistor type memory cell using a FLOTOX transistor for performing / writing (WRITE).

However, in the conventional example, the definition of erasing / writing is opposite to that of the conventional example shown in FIG. 2, and the emission of electrons is defined as erasing and the injection is defined as writing. .

In the previous example, the FLOTOX transistor for generating the FN tunnel current and the potential difference between the control gate and the drain were 18 V. In the present example, the potential difference was 16 V during erasing and 18 V during writing. F-
A memory cell capable of generating an N tunnel current is used.

The configuration and operation of the memory cell of the conventional example will be described below.

The memory cell is composed of only a FLOTOX transistor. Further, a (2 × 2) minimum matrix structure similar to the conventional example shown in FIG. 2 will be described as an example.

(A) As shown in FIG.
12, 21, 22 are arranged in a matrix, and these memory cells are connected to word lines WL1, WL2, drain lines D1, D2 and source lines S1, S2 as follows.

Word line WL1 is connected to the control gates of memory cells 11 and 12, and word line WL2
Are connected to the control gates of the memory cells 21 and 22.

Drain line D1 is connected to the drains of memory cells 11 and 21, and drain line D2 is connected to the drains of memory cells 12 and 22.

The source line S1 is connected to the memory cells 11 and 21
And the source line S2 is connected to the sources of the memory cells 12 and 22.

The erasing and writing operations will be described below.

(A) Erasing (ERASE) (Refer to (a), (b) and (d)) The case where the memory cells 21 and 22 are erased will be described.

The word line WL2 is set to -11V and the word line W
L1 is biased to 0V and source lines S1 and S2 are biased to 5V.

The drain lines D1 and D2 are in a floating state initially set to 0V. Further, the substrate voltage is 0V.

At this time, the control gates of the memory cells 21 and 22 are biased at -11 V and the sources are biased at 5 V, and the memory cell source potential is 16 V higher than the control gate potential.

Therefore, an FN tunnel current is generated,
Electrons are emitted from the floating gate of the memory cell to the source, and the memory cells 21 and 22 are erased collectively.

On the other hand, non-selected memory cells 11 and 12 have a control gate of 0 V and a source of 5 V, the potential difference is only 5 V, no FN tunnel current is generated, and no erasing is performed.

(B) Case of Performing Write (WRITE) (Refer to FIGS. (A), (c) and (d)) Here, the case of selecting and writing the memory cell 21 will be described.

The selected word line WL2 is biased at 18V, and the unselected word line WL1 is biased at 7V.

The selected source line S1 is biased at a reference voltage of 0V, and the unselected source line S2 is biased at a voltage of 7V.

The drain lines D1 and D2 are in a floating state initially set to 0V. Further, the substrate voltage is 0V.

At this time, the source of the control gate of the selected memory cell 21 which is electrically separated from the floating gate by the tunnel oxide film by 18V is biased to 0V, and the control gate potential becomes 18V higher than the source potential. , FN tunnel current is generated, electrons are injected into the control gate, and writing is performed.

On the other hand, the unselected memory cells (memory cells 22 in FIG. 3) on the selected word line have the word line WL2 biased at 18V and the unselected source line S2 biased at 7V, and the control gate of the memory cell 22 is controlled. The potential is 11 V higher than the source potential. With this potential difference, F-
No N tunnel current is generated, and no writing is performed.

In a non-selected memory cell (memory cell 11 in FIG. 3) on the selected source line, the word line WL1 is biased at 7V and the source line S1 is biased at 0V, and the control gate potential of the memory cell is 7 from source potential
V state is high. Even with this potential difference, no FN tunnel current is generated, and writing is not performed.

Further, the unselected memory cells (memory cell 12 in FIG. 3) on the unselected word line and on the unselected source line have both the word line WL1 and the source line S2 biased to 7V, and No potential difference occurs between the control gate and the source of the cell 12, and no data is written.

As described above, in this conventional example,
In order to create a potential difference that generates an FN tunnel current between the control gate and the drain, in the case of erasing, the potential of the control gate is set to −11 V and one of the source potentials is set to 5 V. In the case of writing, a method is used in which the source of the memory cell is used as a reference potential and a voltage of a potential difference required to generate an FN tunnel current is biased in the control gate.

That is, to generate the FN tunnel current,
V for erasing the necessary potential difference_Eb(V _Eb= V_Eb1 + V
_Eb2 , V_Eb1 > 0, V_Eb2 > 0), V for writing_WbMa
Memory cell control gate potential and drain voltage
And source potentials are V_G , V_D , V_S , Substrate voltage
To V_BBThen, in the case of erasure, V_SG= V_S -V_G = V_Eb1 -(-V_Eb2 ) = V_Eb1 + V
_Eb2 = V_Eb V_BB= 0V, V_D = Float writing V_GS= V_G -V_S = V_Wb−0 = V_Wb V_BB= 0V, V_D = Float.

(3) Description of Conventional Example 3 FIG. 4 shows a memory cell using an MNOS (Metal-Insulator-Oxide-Semiconductor) type non-volatile transistor which performs erasing (ERASE) / writing (WRITE) by tunnel current. Erasure type E ² P that can be erased in word line units
This is a conventional example when a ROM is configured, and shows the memory cell operation.

The configuration of this embodiment and the operation of the memory cell will be described below.

The memory cell is a one-transistor memory cell using an MNOS transistor having a nitride film for accumulating electrons below the gate and a tunnel oxide film formed below the nitride film.

However, in this conventional example, similarly to the example shown in FIG. 3, the emission is defined as erasing and the injection is defined as writing. A (2 × 2) minimum matrix structure will be described as an example.

(A) As shown in FIG.
12, 21, 22 are arranged in a matrix, and these memory cells, word lines WL1, WL2, bit lines BL
1, BL2, source lines AS1, AS2 and well line W
A1 and WA2 are connected as follows.

The word line WL1 is connected to the gates of the MNOS transistors of the memory cells 11 and 12, and the word line WL2 is connected to the gates of the MNOS transistors of the memory cells 21 and 22.

Bit line BL1 is connected to the drains of MNOS transistors of memory cells 11 and 12, and bit line BL2 is connected to MNOS of memory cells 12 and 22.
Connected to the drain of the transistor.

Source line AS1 is connected to the MNOS transistors of memory cells 11 and 21, and source line AS1 is connected to the source line AS1.
2 is connected to the sources of the MNOS transistors of the memory cells 12 and 22.

Well line WA1 is connected to the wells of memory cells 11 and 12, and well line WA2 is connected to the wells of memory cells 21 and 22. Further, the MNOS transistor of this example can generate a tunnel current with a potential difference of 20V.

The erasing and writing operations will be described below.

(A) Case of Performing Erase (ERASE) (See FIGS. 7A, 7B, and 7D) The case of selecting and erasing the memory cells 21 and 22 will be described here.

The selected word line WL2 is biased to -15V and the unselected word line WL1 is biased to 5V. The selected well line WA2 is biased to 5V, and the unselected well line WA1 is biased to 0V.

The bit lines BL1 and BL2 are biased at 5V, and the source lines AS1 and AS2 are biased at 5V. The substrate voltage is 5V.

When biased in this manner, MNOS
The drain, source, and well potentials of the transistor are equal, and this potential is 20 V higher than the gate potential of the MNOS transistor.

Therefore, memory cells 21 and 22
In this case, a tunnel current is generated, electrons are emitted from the nitride film, and the memory cells 21 and 22 are erased. At this time, since the gates, drains, sources and wells of the unselected memory cells 11 and 12 are all at the same potential, erasing is not performed.

(B) Case of Performing Write (WRITE) (Refer to (a), (c) and (d) of FIG.) Here, the case of selecting the memory cell 21 and writing will be described.

The selected word line WL2 is biased at 5V, and the unselected word line WL1 is biased at -15V.

The selected bit line BL1 is in a floating state of -15V, and the unselected bit line BL2 is initially set to 0V.

The well lines WA1 and WA2 are each biased by -15V. Similarly, select source line AS
1 is set to -15 V, and the unselected source line AS2 is set to a floating state in which it is initially set to 0 V. At this time, the substrate voltage is 0V.

At this time, an inversion layer is generated in the channel portion of the MNOS of the memory cell 21. In this case, the potential of the inversion layer is approximately equal to the source and drain potentials, that is, 20 V, and the gate of the MNOS transistor and the inversion layer Is a potential difference sufficient to generate a tunnel current.

Therefore, electrons in the inversion layer are injected into the nitride film, and writing to memory cell 21 is performed.

On the other hand, unselected memory cells 2 in the selected well
2, an inversion layer is formed in the same manner as the memory cell 21, but since the bit line BL2 and the source line AS2 are in a floating state, the potential V _i of the inversion layer of the memory cell 22 is V _i = ( _Co × 5 + _Cd × (−15) / ( _Co + _Cd +
C _BL + C _AS ) where C _o : capacitance per unit area of the gate insulating film, C _d : capacitance per unit area of the depletion layer, C _BL : stray capacitance of BL2, C _AS : stray capacitance of AS2 Memory cell 21 , No tunnel current is generated, and the memory cell 22 is not written.

In the memory cells 11 and 12 in the non-selected wells, no inversion layer is formed in the MNOS channel portion, no electrons are injected, and no data is written. In this way, the memory cell 21 is selectively written.

As described above, in this conventional example,
The potential difference enough to generate a tunnel current
In order to create a voltage between the source, the drain and the well, a method of generating a voltage from both the gate and the source, the drain and the well is used.

That is, it is necessary to generate a tunnel current.
Gate, drain, source and
When erasing the potential difference between the inversion layer and the well,
_EC(V_EC= V_EC1 + V_EC2 , V_EC1 ≧ 0, V_EC2 ≧
0), V for writing_WC(V_WC= V _WC1 + V_WC2 , V
_WC1 ≧ 0, V_WC2 ≧ 0) or the gate of the memory cell,
Source, drain and well potentials to V_G , V_S , V
_D , V_PW, Substrate voltage to V_BBChannel section, inversion layer potential V
_i Then, in the case of erasure, V_iG= V_DG= V_SG= V_S -V_G = V_EC1 -(-V_EC2 )
= V_EC1 + V_EC2 = V_EC V_BB= V_i = V_D = V_S ≧ V_PW When writing V_Gi= V_GD= V_GS= V_G -V_S = V_WC1 -(-V_WC2 )
= V_WC V_BB≧ V_PW It is expressed as

[0090]

However, in the first conventional example shown in FIG. 2, as a method of generating the potential difference (V _Ea and V _Wa ) for generating the _FN tunnel current, one of the control gate and the drain is used. Is set to a reference potential of 0 V, and a voltage corresponding to a potential difference (V _Ea or V _Wa ) causing an FN tunnel current is biased to the other.

For this reason, the source-drain breakdown voltage (hereinafter abbreviated as BV _SD ) and junction breakdown voltage (hereinafter abbreviated as BV _SDJ ) of the transistors constituting the drivers of the word line, bit line and select line and the select transistor of the memory cell are described. Requires V _Ea or V _Wa or more.

It is widely known that the erase / write voltage of a memory cell currently used in an E ² PROM is considerably higher than the voltage used in a normal semiconductor integrated circuit. Therefore, BV _SD and BV _SDJ are also generally used. Significantly higher than that of the semiconductor integrated circuit.

As described above, a transistor having a high BV _SD and a high BV _SDJ (hereinafter abbreviated as a high withstand voltage transistor) has a deeper junction, a thicker gate oxide film, or a longer gate length. Since the withstand voltage is increased, it is difficult to reduce the size, and the transistor size is larger than that of a transistor manufactured for operating at 5 V.

Therefore, (1) The pattern area occupied by the word line, bit line and select line drivers is large. (2) Since the select transistor is constituted by a high breakdown voltage transistor, the reduction of the memory cell is prevented. (3) A wafer process for forming a high breakdown voltage transistor is required, and the wafer process becomes longer. There was a problem.

On the other hand, in the conventional example 2 shown in FIG.
In this case, the source of the memory cell is
The potential difference required for FN tunneling with the reference potential set to 0V
(V _Wb) Is the voltage of the potential difference required for the control gate
Is generated by biasing.

For the word line driver,
After all, it must be constituted by a high breakdown voltage transistor.

Therefore, (4) the pattern area occupied by the word line driver is large. (5) A wafer process for forming a high breakdown voltage transistor is required, and the wafer process becomes longer. In addition, since the select transistor is deleted, (6) complicated control is required to prevent the threshold value of the memory cell from being negative when erasing all the memory cells. There is a problem.

In the conventional example 3 shown in FIG. 4, in the case of erasing,
Set the selected word line WL2 to -V_EC2 , Unselected word line WL1
To V_EC1Is biased to the word line driver
Well potential is −V_EC2 Or V _EC1 It is.

In the case of writing, the selected word line WL2 is set to V
_WC1 , The unselected word line WL1 is set to -V _WC2 Bias to
The word line driver as in the erase operation.
The cell potential is V_WC1 Or -V_WC2 Biased.

That is, the junction withstand voltage in the case of erasing / writing is V _EC1 + V _EC2 = V _EC and V _WC1 + V _WC2 =
V _WC is required. Therefore, the word line driver must be composed of high voltage transistors. Therefore, (7) the pattern area occupied by the word line driver is large due to the use of the high breakdown voltage transistor. (8) A wafer process for forming a high breakdown voltage transistor is required, and the wafer process becomes longer.

(9) Since the memory cells are formed in the wells separated by the word line unit, the interval between the wells is required to be wide, which prevents high integration.

The present invention has the common problems of the prior art described above. (1) The use of a high-breakdown-voltage transistor occupies a large pattern area occupied by the word line bit line or select line driver. (3) that the select transistor of the high breakdown voltage transistor prevents the reduction of the memory cell, and (4) for all the memory cells, In order to eliminate the individual problems of the conventional example that complicated control is necessary so that the threshold value of the memory cell is not negative at the time of erasing, and (5) the well spacing prevents high integration. Another object of the present invention is to provide a new method of erasing / writing a memory cell and a memory cell.

[0103]

In order to solve the above-mentioned problems, the present invention provides a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and a floating gate and a floating gate. In a semiconductor memory device including a plurality of memory cells each including a transistor having a control gate disposed therein, a voltage higher than a first power supply voltage is applied to a control gate, and a second power supply voltage is applied to a source or a drain of the transistor. By applying a lower voltage, electrons are injected into the floating gate to erase data written in a plurality of memory cells at once.

Further, by applying a voltage lower than the second power supply voltage to the control gate and applying a voltage higher than the first power supply voltage to the source or drain of the transistor, the electrons of the floating gate are released, and the memory is released. Data is written to a cell.

[0105]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, and shows its operation.

This embodiment is an example of a case where a 5 V single power supply batch erase type E ² PROM which can be erased in word line units is constituted. Hereinafter, the configuration of the present embodiment and the operation of the memory cell will be described.

The memory cell is composed of an N-channel FLOTOX transistor having a P-type substrate as a base, a tunnel oxide film formed on the entire surface under the floating gate and a select transistor for bit selection as shown in FIGS. The FLOTOX transistor and the select transistor are connected in series.

In this embodiment, a FLOT in which a tunnel oxide film having a thickness of about 100
Although an OX transistor is used, the same can be realized by using a tunnel window type FLOTOX transistor shown in the first conventional example.

Although the (2 × 2) reduced matrix structure is described here as an example, it will be easily understood that the following discussion can be directly extended to a larger matrix structure.

As shown in FIG. 13A, the circuit configuration is such that memory cells 11, 12, 21, 22 are arranged in a matrix, and these memory cells and select lines SL1, SL2,
The word lines WL1 and WL2, the bit lines BL1 and BL2, and the source lines AS1 and AS2 are connected as follows.

Select line SL1 is connected to the gates of select transistors of memory cells 11 and 12, and select line SL2 is connected to the gates of select transistors of memory cells 21 and 22.

The word line WL1 is connected to the control gates of the FLOTOX transistors of the memory cells 11 and 12, and the word line WL2 is connected to the control gates of the FLOTOX transistors of the memory cells 21 and 22.

Bit line BL1 is connected to the drains of the select transistors of memory cells 11 and 21, and bit line BL2 is connected to the drains of the select transistors of memory cells 12 and 22.

The source line AS1 is connected to the sources of the FLOTOX transistors of the memory cells 11 and 12,
The source line AS2 is connected to the FLO of the memory cells 21 and 22.
Connected to the source of the TOX transistor.

In this embodiment, as in the first conventional example, the case where electrons are injected into the floating gate is erased (ER
ASE), and the case where electrons are emitted from the floating gate is defined as writing (WRITE).

The operation of erasing and writing according to the present embodiment will be described below.

(A) When erasing (ERASE) is performed (refer to (a), (b) and (d) of FIG.) A case where the memory cells 21 and 22 are selected and erased will be described here.

The selected word line WL2 is biased to 14V, and the unselected word line WL1 is biased to near 0V.

The select transistors SL1 and SL2 are turned on and the bit lines and FLOTO are connected.
A voltage (0 V in this embodiment) for electrically connecting the X transistor is biased. The source lines AS1 and AS2 are biased at -5V.

The bit lines BL1 and BL2 are in a floating state initially set to 0V. The substrate voltage is biased at -5V.

At this time, the control gate voltage of the memory cells 21 and 22 is 14 V, and the voltage of the drain is −5.
V, and the control gate potentials of the memory cells 21 and 22 are 19 V higher than the drain potentials.

Therefore, an FN tunnel current is generated,
Electrons are injected from the drain to the floating gate,
Erasing of memory cells 21 and 22 is performed.

On the other hand, memory cells 11 on unselected word lines
In Nos. 12 and 13, the control gate has 0 V, the drain has a potential difference of only 5 V from -5 V, and no FN tunnel current is generated and no erasing is performed.

(B) Case of Performing Write (WRITE) (Refer to FIGS. (A), (c) and (d)) Here, the case of selecting the memory cell 21 and writing will be described.

Word lines WL1 and WL2 are biased to -5V. The selected select line SL2 is biased to 14V and the unselected select line SL1 is biased to 0V.

The selected bit line BL1 is biased to 14V, and the unselected bit line BL2 is in a floating state initially set to 0V. Source lines AS1 and AS2
Is a floating state initially set to 0V. The substrate is biased at 0V.

At this time, the FL of the selected memory cell 21 is
A voltage lower than the potential of the selected bit line BL1 by the threshold voltage V _{TW (1) of} the select transistor is biased to the drain of the OTOX transistor via the select transistor.

Here, the threshold voltage V _{TW (1)} of the select transistor is V _{TW (1)} = 1V which is about 1 V lower than the threshold voltage V _TW ≒ 2V of the conventional example (1).

This is because the substrate potential V _{BS based} on the source of the select transistor is raised from 20 V in the conventional example (1) to 14
V and the required withstand voltage of the transistor can be reduced from 20 V to 14 V in the conventional example (1), so that the gate oxide film of the select transistor can be thinned. This is because less was achieved than in Example (1).

Therefore, FLOTOX of memory cell 21
The drain of the transistor is 14V-V _{TW (1)} (≒ 13
V). At this time, the control gate is biased to -5V.

Therefore, the drain potential of memory cell 21 is higher than the potential of its control gate by 14 V-V.
_{TW (1)} − (− 5V) = 19V−V _{TW (1)} (≒ 18V) High state, FN tunnel current is generated, and electrons are emitted from the floating gate of the memory cell 21 through the drain tunnel oxide film. Then, the selected memory cell 21 is written.

On the other hand, unselected memory cells (memory cell 22 in FIG. 1) on the selected select line are connected to bit line BL2.
Are in a floating state initially set to 0 V, and the control gate is at -5 V. Therefore, the potential difference between the control gate and the drain of the unselected memory cell 22 is 5
V or less.

Therefore, no FN tunnel current is generated and no writing is performed.

Further, unselected memory cells on unselected select line SL1 (memory cells 11 and 12 in FIG. 1)
Indicates that the select transistor is in a non-conductive state and the FLO
The drain of the TOX transistor is in a floating state initially set to 0V.

Since the control gate is at -5 V, the potential difference can be set to about 5 V or less as in the case of the memory cell 22, so that no FN tunnel current is generated and no data is written.

As described above, in this embodiment, a potential difference is generated from both the control gate and the source or the drain in order to create a potential difference between the control gate and the source or the drain sufficient to generate a tunnel current. A method and a method of changing the substrate voltage in accordance with the bias state of the memory cell in order to set the diffusion layer and the substrate to zero bias or reverse bias are used.

That is, the potential difference required to generate the tunnel current is V _{E for} erasing and V _W for writing, and the absolute value of the voltage applied to the control gate at erasing is V _E1 ,
The absolute value of the voltage applied to the source is V _E2 , the absolute value of the voltage applied to the write control is V _W1 , the absolute value of the voltage applied to the drain is V _W2 , and the voltages of the control gate, source and drain of the FLOTOX transistor are V.
_Assuming that _G , V _S , V _D , and the substrate voltage are V _BB , when erasing V _GS = V _G −V _S = V _E1 − (− V _E2 ) = V _E1 + V _E2 , when V _BB ≦ V _S writing V _GS = V _D −V _G = V _W2 − (− V _W1 ) = V _W1 + V _W2 , V _BB = 0V Therefore, the memory is expressed as V _E1 + V _E2 = V _E , V _W1 + V _W2 = V _W. The cell and the substrate are biased for erasing / writing.

[0138]

As described above in detail, according to the present invention, a voltage higher than the first power supply voltage is applied to the control gate, and the second voltage lower than the first power supply voltage is applied to the source or drain of the transistor. By applying a voltage lower than the power supply voltage to the floating gate, electrons are injected into the floating gate to erase data written in the plurality of memory cells at a time, and the second power supply is applied to the control gate. By applying a voltage lower than the voltage and applying a voltage higher than the first power supply voltage to the source or drain of the transistor, electrons in the floating gate are emitted and data is written to the memory cell. Reduce the required breakdown voltage of the transistors that make up each driver, and combine the select transistors and their gate voltages. It was possible to reduce the necessary breakdown voltage of the transistor constituting the driver to nest.

That is, the source-drain withstand voltage of the above transistor is BV _SD , and the junction withstand voltage is BV _SD .
_Assuming that the potential difference between the control gate and the source or drain required to generate the _SDJ and _FN tunnel currents is V _E at the time of erasing and V _W at the time of writing, BV _SD > V _E and BV _SD > V _W , BV _SDJ > V _E and BV _SD > V _W (Conventional Examples 1 and 2) BV _SDJ > V _E and BV _SDJ > V _W (Conventional Example 3), but control on erase operation Assuming that the voltage is V _E1 and the voltage applied to the drain during writing is V _W1 , in the present invention, V _E > BV _SD > V _E1 and V _E > BV _SDJ > V _E1 V _W > BV _SD > V _W1 and V _W > It is possible to _satisfy BV _SDJ > V _W1 (1) A reduction in the pattern area occupied by the driver constituting the driver of the word line, bit line or select line can be reduced, and (2) formation of a high breakdown voltage transistor Process removed Can, possible to reduce the wafer process, (3) reduction of the memory cell size due to the reduction of the required withstand voltage of the select transistor is possible, effects such as can be expected.

Although the embodiment has been described by taking as an example a batch erasing type E ² PROM which performs erasing in word line units,
(A) By connecting control gates of all memory cells and providing at least one bias circuit or a specially designed high-withstand-voltage drive circuit to the control gates, which can be constituted only by P-channel transistors, Erase-type E ² PROM for simultaneously erasing memory cells, (b) connecting control gates of memory cells for a desired number of word lines and providing a selection circuit which can be constituted only by P-channel transistors for selecting these control gate groups , A sector erase type E ² PROM, (c) a batch erase type E ² PRO which can be erased in word line units in
In M, the function of once reading the information of the memory cell not to be rewritten on the same word line as the memory cell to be rewritten and adding the function of rewriting at the same time as the writing of the memory cell to be rewritten is performed in byte units. It is clear that the present invention can be applied to an E ² PROM or the like which can be rewritten by the above method.

The reference voltage which further divides V _E and V _W into two can be based on an externally applied voltage, that is, any voltage applied to the device or generated in the device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a memory cell according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a memory cell of Conventional Example 1.

FIG. 3 is an explanatory diagram of a memory cell of Conventional Example 2;

FIG. 4 is an explanatory diagram of a memory cell of Conventional Example 3;

FIG. 5 is a diagram showing a relationship between threshold voltages in a conventional example.

[Explanation of symbols]

 11, 12, 21, 22 Memory cells SL1, SL2 Select lines WL1, WL2 Word lines BL1, BL2 Bit lines AS1, AS2 Source lines WA1, WA2 Well lines

Claims (12)

[Claims] A transistor provided with a first power supply voltage and a second power supply voltage lower than the first power supply voltage, the transistor having a floating gate and a control gate disposed above the floating gate; In a data erasing method for a semiconductor memory device having a plurality of memory cells, a voltage higher than the first power supply voltage is applied to the control gate, and a voltage lower than the second power supply voltage is applied to a source or a drain of the transistor. A method of erasing data written in a plurality of memory cells by collectively erasing data written in a plurality of memory cells by injecting electrons into the floating gate. 2. A semiconductor device comprising: a transistor supplied with a first power supply voltage and a second power supply voltage lower than the first power supply voltage, the transistor having a floating gate and a control gate disposed above the floating gate; In a data writing and erasing method for a semiconductor memory device having a plurality of memory cells, a voltage higher than the first power supply voltage is applied to the control gate, and a voltage lower than the second power supply voltage is applied to a source or a drain of the transistor. Applying electrons to the floating gate to collectively erase data written in the plurality of memory cells, apply a voltage lower than the second power supply voltage to the control gate, Applying a voltage higher than the first power supply voltage to the source or drain of the transistor; And emits electrons from the floating gate,
A data writing and erasing method for a semiconductor memory device, wherein data is written to a memory cell. 3. The method according to claim 1, wherein each of the plurality of memory cells is connected to a corresponding one of a plurality of word lines, and the batch erasing process of the data in the memory cells is performed in word line units. Data erasing method for a semiconductor memory device according to the above. 4. The method according to claim 2, wherein each of the plurality of memory cells is connected to a corresponding one of a plurality of word lines, and a batch erasing process of data for the memory cells is performed in word line units. And method for writing and erasing data in a semiconductor memory device. 5. The data erasing method for a semiconductor memory device according to claim 1, wherein the batch erasing process of the data in the plurality of memory cells is performed on all of the plurality of memory cells. 6. The method of writing and erasing data in a semiconductor memory device according to claim 2, wherein the batch erasing process of the data in the plurality of memory cells is performed on all of the plurality of memory cells. 7. Each of said memory cells is constituted by using a semiconductor base, and when erasing data from said memory cells, said second base is applied to said semiconductor base.
6. The method according to claim 1, wherein a voltage lower than the power supply voltage is applied. 8. Each of said memory cells is constituted by using a semiconductor base, and when erasing data from said memory cells, said second base is applied to said semiconductor base.
3. A voltage lower than the power supply voltage is applied, and when data is written to the memory cell, the second power supply voltage is applied to the semiconductor substrate. 4. The data writing and erasing method for a semiconductor memory device according to any one of items 4 and 6. 9. The method of writing and erasing data in a semiconductor memory device according to claim 2, wherein the data write processing to said memory cells is performed in word line units. 10. In the writing of the memory cell, the same data as the stored data is stored in another memory cell connected to the same word line as the memory cell in which new data is to be written. 10. The data writing method according to claim 9, wherein the data is rewritten. 11. The system according to claim 1, wherein the voltage higher than the first power supply voltage is a positive voltage, and the voltage lower than the second power supply voltage is a negative voltage. The data erasing method for a semiconductor memory device according to any one of the above. 12. The system according to claim 2, wherein a voltage higher than the first power supply voltage is a positive voltage, and a voltage lower than the second power supply voltage is a negative voltage. ,
11. The data writing and erasing method for a semiconductor memory device according to any one of items 9 and 10.