JP2001160290A - Memory control device and memory access method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control device and a memory access method in which power consumption can be reduced in the case of memory access when regularity exists in setting an address. SOLUTION: Relating to a memory control device 1 provided with a word line selecting information storing section arranged between a memory cell array 9 and a row decoder 33, a column selecting information storing section 17 arranged between a column selector 39 and a column decoder 37, and a control circuit 19, each selecting information storing section 11, 17 is constituted of sift registers including a selector 23 and a flip-flop 21. When the control circuit 19 receives such information that an address accessed at the next time is set conforming to the prescribed regulation, the circuit 19 stops operation of two decoders, to supply control signals S1, S2, CLK to each selecting information storing section 11, 17, to shift just previous selecting position information in accordance with the regulation, to output it as the next selecting information, and a memory cell is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory control device and a memory access method capable of reducing power consumption in a case where a memory access mode is regular.

[0002]

2. Description of the Related Art A semiconductor memory device is one of the essential components of a semiconductor integrated circuit, and has conventionally been designed on the assumption that it is accessed randomly. Therefore,
Even if there is some regularity in accessing memory,
Generally, address decoding is performed for each access.

[0003]

However, in memory access, it is very difficult to access an address which has a regular relationship with the address accessed immediately before, typically, an address adjacent to the address accessed immediately before. Many Even in such a case, conventionally, address decoding had to be performed for each access, so that wasteful power was consumed correspondingly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the purpose of making use of information about an address accessed immediately before when a regular memory access is performed. An object of the present invention is to provide a memory control device and a memory access method that can reduce power consumption.

[0005]

The present invention solves the above-mentioned problems by the following means.

That is, according to the first aspect of the present invention, the storage means for storing the physical position information of the memory cell in the memory array corresponding to the supplied address, and the next access address are predetermined. Control means for determining and accessing a physical position of a memory cell to be accessed next based on the physical position information accessed immediately before and stored in the storage means, There is provided a memory control device comprising:

According to the memory control device, when the address is set according to a predetermined rule, the control means should access next based on the physical position information stored in the storage means. Since the physical position of the memory is determined and accessed, writing and reading can be performed without using an address decoder.
Thereby, power consumption can be significantly reduced.

It is preferable that the memory control device further includes a signal line for supplying a signal for determining whether or not the next access address is set according to the rule to the control means.

The number of the signal lines is usually one or two.
The number of lines is overwhelmingly smaller than the address signal lines. Therefore, when the address to be accessed next is set in accordance with the above rules, the signal need only be supplied to the signal line without sending the address from the accessing side, and the number of signal lines to be driven is greatly reduced. Thus, the power consumption of the entire system can be reduced.

According to a second aspect of the present invention, an address decoder for controlling access to a memory array based on an address signal, and the address decoder interposed between the address decoder and the memory array, Receiving storage means for storing physical position information of a memory cell in the memory array corresponding to a signal, and receiving a determination signal as to whether an address to be accessed next is set according to a predetermined rule; If not set according to the rules, the operation of the address decoder is allowed.If set according to the rules, the operation of the address decoder is stopped, and the next access is performed based on the physical position information corresponding to the immediately preceding address. Control means for controlling the storage means so as to output an address signal of an address to be provided. It is provided.

According to the memory control device, when an address to be accessed next is set according to the rule, a selection signal of an address to be accessed next is based on the physical position information corresponding to the immediately preceding address. Is provided to the storage means, there is no need to operate the address decoder when accessing the memory cell, and therefore there is no need to supply an address signal to the address line to the address decoder. This provides a memory control device that realizes power saving.

In the above-described memory control device, the storage means is provided between the storage element corresponding to the output terminal of the address decoder and the output terminal of the address decoder corresponding to the storage element. When the control means receives a control signal generated based on the determination signal and the next address to be accessed is not set in accordance with the rule, the address signal output from the output terminal is selected and the storage element is selected. Output to
When an address to be accessed next is set in accordance with the rule, selecting means for selecting an output signal of a storage element connected to the corresponding storage element and outputting the output signal to the corresponding storage element is preferable. It is.

When the access is set in accordance with the above rules, there are a case where the column number simply changes, a case where the row number changes, and a case where both the column number and the row number change. In such a case, the storage means can be operated as a shift register as necessary, and the data stored in the storage element can be shifted. As a result, it is possible to generate position information to be accessed next by utilizing the immediately preceding address and supply the generated position information to the memory array.

The above-mentioned predetermined rule is one of a first rule for subtracting 1 from the address value of the address accessed immediately before and a second rule for adding 1 to the address value of the address accessed immediately before. Including at least one.

The shift of data in the storage means is as follows.
If the predetermined rule is, for example, the first rule, one or both of the row number and the column number are shifted in a countdown direction, and if the predetermined rule is the second rule, one of the row number or the column number is shifted. Alternatively, both are shifted in the direction of counting up.

In the above-described memory control device, the memory control device is interposed between the storage means and the word line of the memory, and outputs data stored in the storage means to the word line at the time of reading and writing. It is desirable to further include a logic circuit that cuts off other than at the time of writing and disconnects the storage means from the memory cells constituting the memory array.

According to the logic circuit, a word line connecting the storage means and the memory is provided only during a period from when a physical position of a memory cell to be accessed next is determined to when writing or reading is completed. Activate. This can further reduce power consumption.

The memory cell includes a first switching element having a first threshold value and driven by a first voltage, wherein the address decoder and the selection means are connected to the first switching element.
A second switching element having a second threshold value lower than the first threshold voltage and being driven by a second voltage lower than the first voltage, wherein the storage element includes the first voltage Preferably has a voltage conversion function of converting the second voltage into the second voltage.

Thus, the address decoder can be driven at a low voltage, and the power consumption can be further reduced. On the other hand, since the second threshold value is lower than the first threshold value, it is possible to prevent the operation speed of the circuit from decreasing even if the drive voltage is reduced.

According to a third aspect of the present invention, there is provided an address signal input step of inputting an address signal from a decoder to a memory array, and physical position information of a memory cell in the memory array corresponding to the address signal. A physical position information storing step, a regularity determining step of determining whether a next access address is set according to a predetermined rule, and the next access address being set according to the rule. In this case, the decoder is deactivated, and based on the physical position information of the memory cell corresponding to the immediately preceding address,
A physical position determining step of determining a physical position of a memory cell to be accessed next, there is provided a memory access method.

According to the memory access method of the present invention, when an address to be accessed next is set in accordance with the above rules, a next address is stored based on the physical position stored in the physical position information storing step. Since the physical position of the memory cell to be accessed is determined, the memory cell can be accessed without operating the decoder.
Also, since the device for accessing the memory only needs to supply the adjacent address access detection signal instead of the address, the driving power is small. As a result, the power required for memory access can be reduced.

The physical position information storing step is a step of storing the physical position information corresponding to each output of the decoder, and the physical position determining step is:
Preferably, the step is a step of determining the physical position of the next memory cell to be accessed by shifting the stored physical position information according to the rule.

If the predetermined rule is, for example, the first rule, the physical position information is shifted in a direction in which the row number or the column number is counted down as necessary. In the case of the second rule, the row number or the column number is shifted in the direction of counting up.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same portions are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

(1) First Embodiment FIG. 1 is a block diagram showing a first embodiment of a memory control device according to the present invention. The memory control device 1 of the present embodiment is an example in which the present invention is applied to an SRAM. As shown in FIG.
In addition to the column selector 39, the column decoder 37, the sense amplifier and the write circuit 41, a word line selection information storage unit 11, a column selection information storage unit 17, and a control circuit 19, which are characteristic in this embodiment, are provided.

The memory array 9 has memory cells 31 arranged in a matrix and connected to word lines WL and bit lines BL, respectively.

The row decoder 33 has a word line output terminal.
2 via the line selection information storage unit 11 ⁿ= K word lines
WL and receives an input of an n-bit row address.
By decoding this, k word lines WL
Select one word line WL from 0 to WL (k-1)
I do.

Each output terminal of the column decoder 37 is connected to the column selector 39 via the column selection information storage unit 17, receives an m-bit column address, decodes the input, and supplies it to the column selector 39. . The column selector 39 selects one bit line pairs per 2 ^m sets of bit line pairs based on the column address inputted from the column decoder 37 is connected to the sense amplifier or write circuit.

The control circuit 19 is connected to the row decoder 33 and the column decoder 37 and supplies an enable signal WE. The control circuit 19 is also connected to the word line selection information storage unit 11 and the column selection information storage unit 17, and supplies control signals S1, S2, and CLK to these. In addition,
Word line selection information storage unit 11 and column selection information storage unit 1
7 are controlled independently of each other by a control circuit 19.

As described above, the feature of the memory control device 1 of the present embodiment is that the row decoder 33 is not directly connected to the word line WL, and the word line selection information storage section is provided between the row decoder 33 and the word line WL. 11 and the column selection information storage unit 17 is interposed between the column selector 39 and the column decoder 37 without the column selector 39 being directly connected to the column decoder 37.

Since the word line selection information storage unit 11 and the column selection information storage unit 17 have the same configuration, the word line selection information storage unit 11 will be described as a representative in the following description.

FIG. 2 is a circuit diagram showing a detailed configuration of the word line selection information storage section 11 provided in the memory control device 1 shown in FIG. As shown in the figure, the word line selection information storage unit 11 is disposed so as to form a pair between a word line WL and each output terminal of the row decoder 33 corresponding to the row number of the word line WL. It includes a selector 23 and a flip-flop 21. The selector 23 has three input terminals D1 to D
3 of which the input terminal D2 is connected to the output terminal of the row decoder 33 in the same row. The output terminal of the selector 23 is connected to the input terminal D of the flip-flop 21 on the same row.

The output terminal Q of the flip-flop 21 is connected to the word line WL of the corresponding row number and is connected to the input terminal D of two flip-flops 21 adjacent in the opposite direction. Connected to D1 or D3. In the present embodiment, the output terminal Q of each flip-flop 21 is connected to the input terminal D3 of the selector 23 with the next higher row number and the input terminal D1 of the selector 23 with the next lower row number.

As described above, the input terminal D of each selector 23
1 and D3 are connected to the output terminals Q of the flip-flops 21 in the adjacent upper and lower rows. However, since the periodicity is broken at both ends of the decoder, the lowermost row (the row number value is the maximum value) ) And the top row (the row with the smallest row number value) require a different connection relationship with other selectors 23. An example of this connection processing method will be described with reference to FIG.

As shown in FIG. 3, in this embodiment, it is connected to the input terminal D1 of the selector 23 ₀ in the bottom row word line WL (k-1) on the top line, the word line WL0 of the uppermost row It is connected to the input terminal D3 of the selector 23 _{(k-1) in} the bottom row.

Referring back to FIG.
The lock terminal is connected to a common control signal line l. _CLKControl via
Circuit 19 is connected to receive clock signal CLK.

Further, each of the selectors 23 are connected in common to the control circuit 19 via two control signal lines _{l S1, l S2,} receives the control signal S1, S2.

The operation of the memory control device shown in FIG. 1 will be described with reference to FIG. Hereinafter, the row address side will be representatively described.

First, an operation in the case where addresses to be accessed are set at random as objects of comparison is shown in FIG.
This will be described with reference to FIG. Arrows indicated by broken lines in FIG. 4A indicate signal flows. In this case, an address from the outside is required, and information indicating that the address to be accessed is not adjacent to the address accessed immediately before is input to the adjacent address access detection signal ADJ. Thereby, the control circuit 19 supplies the enable signal WE to each decoder so that the address can be decoded, and supplies the control signals S1 and S2 to each address storage unit so that the terminal D2 is selected as an input of each selector 23. . Accordingly, each flip-flop 21 outputs a signal decoded at the rise of the CLK signal to each word line. In this way, the word line of the selected row is opened as in the normal memory access method, and the bit line of the selected column is connected to the sense amplifier and the write circuit 41. The power consumption in this case is almost the same as that of a normal SRAM, and there is no particular advantage of this configuration.

Next, the operation when the address to be accessed is set according to a predetermined rule is shown in FIG.
This will be described with reference to FIG. In the present embodiment, for simplicity of description, a case will be described in which an address to be accessed next (from now on) has a regularity of being adjacent to an address accessed immediately before. In this case, the generation of the address signal AD becomes unnecessary, and instead, the adjacent address access detection signal ADJ includes "the address to be accessed now is the address immediately before the address accessed immediately before" or "now. Is the address after the address accessed immediately before ". The control circuit 19 receiving this information stops supplying the enable signal WE to the decoder. As a result, the row decoder 33 becomes inactive as shown by the broken line in FIG. On the other hand, the control circuit 19 stores the data (physical position) of the selected row and the selected column in the immediately preceding access stored in the flip-flops 21 of the word line selection information storage unit 11 and the column selection information storage unit 17, respectively. Control signal S so that the information is shifted upward (in the direction of the lower row number) or downward (in the direction of the higher row number) by one as necessary.
1, S2 are supplied. More specifically, for example, assuming that WL1 is selected in the immediately preceding access in FIG. 4B, only WL1 is at H level, and all other word lines including WL0 and WL2 are at L level. It has become. Here, if it is determined from the information of the adjacent address access detection signal ADJ that “the cell to be accessed next is connected to the word line one row below”, the D1 input of each selector 23 is determined by the S1 and S2 signals. There are controlled to be selectively, flip-flop 21 ₀
-21k _-1 transfers data from the top row to the bottom row. That is, the word line selection information storage unit 11 forms a shift register.

Thereafter, when the data of the flip-flop 21 is updated by a trigger by CLK, WL2 changes to H level, and all other word lines including WL0 and WL1 change to L level. In this way, the row located immediately below the row accessed immediately before is selected without operating the decoder.

Here, according to the configuration of the cell array 9 and the physical position of the memory cell 31 to be accessed, the shift is performed in both the word line selection information storage unit 11 and the column selection information storage unit 17, or in either case. Note that it may shift. However, how to control these storage units is uniquely determined by the decoding result in the immediately preceding access, and there is no need to transmit an address from an external device. For example, as shown in FIG. 1, if the column information currently selected is given to the control circuit (CC) 19 by the column selection information signal line (CSIG), the memory cell to be accessed next becomes the current word line. Therefore, it is not necessary to newly send the address information. When there is no need for shifting, it goes without saying that control is performed so that the CLK signal is not supplied to the corresponding selection information storage unit.

As described above, according to the memory access method of the present embodiment, when accessing an adjacent address, the device requesting the access does not need to drive the address signal line of the memory, and the memory device has Since it is not necessary to perform address decoding, power consumption can be significantly reduced as compared with the conventional memory access method.

(2) Second Embodiment Next, a second embodiment of the memory control device according to the present invention will be described with reference to the drawings. The feature of this embodiment is that the word line selection information storage unit 11 and the memory array 9
And an AND gate 25 interposed between the column selection information storage unit 17 and the column selector 39, or an AND gate 25 interposed between both. This is controlled by the enable signal WE. Other configurations are the same as those of the memory control device 1 shown in FIG.

FIG. 5 is a circuit diagram showing a main part of the memory control device 2 according to the present embodiment. Of the two address storage units, a configuration between the word line selection information storage unit 11 and the word line WL is representative. This is shown in FIG.

As shown in the figure, the memory control device 2
In addition to the word line selection information storage unit 11 shown in FIG. 2, an AND gate 25 is provided between each word line WL and the corresponding flip-flop 21. One of the input terminals of the AND gate 25 is connected to the output of the flip-flop 21, the other input terminal is connected to the enable signal output terminal of the control circuit 19, and the output terminal of the AND gate 25 is connected to the word line. ing. With such a configuration, the output of the word line selection information storage unit 11 is input to the AND gate 25, and the output from the AND gate 25 to the word line WL is an enable signal (WLE in the figure) supplied from the control circuit 19. Is controlled by As a result, the period during which the word line WL is activated can be limited to the period from the determination of the physical position of the memory cell 31 to be accessed to the end of the write or read operation.

As described above, since the output from the flip-flop 21 is not directly connected to the word line WL, any one of the word lines WL does not always remain activated, thereby reducing power consumption. be able to. This is particularly effective for power saving, because it prevents current from continuing to flow from the memory cell to the bit line even after reading is completed.

As described above, according to the present embodiment, the timing at which the decoding result is output to the word line WL or the bit line BL can be adjusted, and the content of the flip-flop 21 is changed to the word line WL only at a predetermined timing. Alternatively, it can be controlled to propagate to the column selection line.
Thereby, in addition to the effects of the above-described first embodiment, it is possible to further contribute to power saving.

(3) Third Embodiment Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a circuit diagram of a main part of the memory control device 3 of the present embodiment, and shows the row address side as a representative.

As is clear from comparison with FIG. 5, the circuit arrangement of the memory control device 3 is the same as that of the above-described second embodiment, but the feature of this embodiment is that The decoder 34 and the selector 24 shown in the figure are constituted by field effect transistors having a low threshold value, and the flip-flop 22 is constituted by a flip-flop having a voltage level conversion function.

As described above, when the decoder 34 and the selector 24 are constituted by the field effect transistors having a low threshold value, the operation can be performed at a low voltage without reducing the operation speed. As a result, power consumption can be further reduced as compared with the above-described embodiment.

In the present embodiment, as indicated by hatching in FIG. 6, an AND gate 2 for driving a word line WL is provided.
The part 6 is driven by a high voltage. This is the memory cell 3
If one part is constituted by a field effect transistor having a low threshold, cell stability is impaired or power consumption is increased due to a leak current. This is because driving is advantageous.

The decoder 34 and the selector 24, which are a low voltage drive part, and the AND gate 2 which is a high voltage drive part
In the present embodiment, a flip-flop 22 having a voltage conversion function is used to connect the flip-flop 6 with the flip-flop 6. Such a flip-flop 22 is, for example, a 1998 Custom Inte
At the grated Circuit Conference, Hamada (lecture number 24.
1) Use the ones proposed by them. The flip-flop 22 receives a low voltage signal at a D input,
Data is fetched at the edge of the clock signal CKL, converted to a high voltage, and output to the output terminal Q.

[0055]

As described in detail above, the present invention has the following effects.

That is, according to the memory control device of the present invention, the storage means for storing the physical position information of the memory cell corresponding to the address, and the address to be accessed next are set according to a predetermined rule. In this case, there is provided control means for determining the physical position of the memory to be accessed next based on the physical position information of the memory cell corresponding to the immediately preceding address stored in the storage means. Writing and reading can be performed without any problem. Thereby, power consumption can be significantly reduced.

According to the memory access method of the present invention, the step of storing the physical position information of the memory cell corresponding to the address signal, and the step of storing the next access address according to a predetermined rule Deactivating the decoder to determine the physical position of the next memory cell to be accessed based on the physical position information corresponding to the immediately preceding address,
If the setting of the address is regular, the memory cell can be accessed without operating the decoder. As a result, the power required for memory access can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory control device according to the present invention.

FIG. 2 is a circuit diagram showing a main part of the memory control device shown in FIG.

FIG. 3 is a circuit diagram showing a detailed configuration of a word line selection information storage unit included in the memory control device shown in FIG.

4 is an explanatory diagram of an operation of a word line selection information storage unit shown in FIG.

FIG. 5 is a circuit diagram showing a main part of a second embodiment of the memory control device according to the present invention;

FIG. 6 is a circuit diagram showing a main part of a third embodiment of the memory control device according to the present invention.

[Explanation of symbols]

 1-3 Memory control device 9 Memory array 11, 13 Word line selection information storage unit 17 Column selection information storage unit 19 Control circuit 21 Flip-flop 22 Flip-flop with voltage conversion function 23 Selector 24 Low-voltage driven selector 25 AND gate 26 High Voltage driven AND gate 31 Memory cell 33 Row decoder 34 Low voltage driven row decoder 37 Column decoder 39 Column selector 41 Sense amplifier and write circuit ADJ Adjacent address access detection signal S1, S2, CLK Control signal

Claims (10)

[Claims] 1. A storage means for storing physical position information of a memory cell in a memory array corresponding to a supplied address, and immediately before when an address to be accessed next is set according to a predetermined rule. A control unit for determining a physical position of a memory cell to be accessed next on the basis of the physical position information accessed and stored in the storage unit and accessing the memory cell. 2. The memory according to claim 1, further comprising a signal line for supplying a signal for determining whether said next access address is set according to said rule to said control means. Control device. 3. An address decoder for controlling access to a memory array based on an address signal, and a memory cell in the memory array corresponding to the address signal, interposed between the address decoder and the memory array. Storage means for storing physical position information of the address decoder; and a determination signal for determining whether an address to be accessed next is set according to a predetermined rule. If the setting is made according to the rule, the operation of the address decoder is stopped, and an address signal of an address to be accessed next is output based on the physical position information corresponding to the immediately preceding address. A control unit for controlling the storage unit. 4. The storage means is interposed between a storage element corresponding to an output terminal of the address decoder, an output terminal of the address decoder, and the storage element respectively corresponding to the output terminal. When the control unit receives a control signal generated based on the determination signal and the address to be accessed next is not set according to the rule, the address signal output from the output terminal is selected to select the storage element. Output to
When an address to be accessed next is set in accordance with the rule, selecting means for selecting an output signal of a storage element connected to the corresponding storage element and outputting the output signal to the corresponding storage element. The memory control device according to claim 3, wherein: 5. The predetermined rule includes a first rule for subtracting 1 from an address value of an address accessed immediately before and a second rule for adding 1 to an address value of an address accessed immediately before. The memory control device according to claim 3, wherein at least one of the memory control devices is included. 6. A memory interposed between the storage means and a word line of the memory, and outputs data stored in the storage means to the word line at the time of reading and writing, and shuts off except at the time of reading and writing. 6. The memory control device according to claim 3, further comprising a logic circuit that disconnects said storage means from memory cells forming said memory array. 7. The memory cell includes a first switching element having a first threshold value and driven by a first voltage, wherein the address decoder and the selection unit are configured to: A second threshold lower than the value,
A second voltage driven by a second voltage lower than the first voltage;
7. The storage element according to claim 6, wherein the storage element has a voltage conversion function of converting the first voltage to the second voltage.
3. The memory control device according to 1. 8. An address signal inputting step of inputting an address signal from a decoder to a memory array; a physical position information storing step of storing physical position information of a memory cell in the memory array corresponding to the address signal; A regularity determining step of determining whether an address to be accessed next is set according to a predetermined rule; and setting the decoder to an inactive state when the address to be accessed next is set according to the rule. Determining a physical position of the next memory cell to be accessed based on the physical position information of the memory cell corresponding to the immediately preceding address. 9. The physical position information storing step is a step of storing the physical position information corresponding to each output of the decoder, and the physical position determining step is a step of storing the stored physical position. 9. The memory access method according to claim 8, further comprising: determining a physical position of the next memory cell to be accessed by shifting information according to the rule. 10. The predetermined rule includes a first rule for subtracting 1 from an address value of an address accessed immediately before, and a second rule for adding 1 to an address value of an address accessed immediately before. 10. The memory access method according to claim 8, wherein at least one of them is included.