JP2001157082A - Synchronization separation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization separating circuit, capable of reliably separating a synchronization pulse by simple constitution concerning the synchronization separating circuit for separating a synchronization signal from a composite video signal. SOLUTION: A charging circuit 10 charges a capacitor C1 with a bias voltage Vbias to clamp a composite video signal inputted to an input terminal Tin, the composite signal clamped by the capacitor C1 is additionally clamped by a clamp circuit 42 using a capacitor C2, and the synchronization pulse is separated from the composite video signal clamped by the circuit 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit, and more particularly to a sync separation circuit for separating a sync signal from a composite video signal.

[0002]

2. Description of the Related Art FIGS. 5 and 6 show waveform diagrams of a composite video signal. The composite video signal 1 is, as shown in FIG.
It comprises a horizontal synchronization pulse 3, equalization pulses 4, 5, a vertical synchronization pulse 6, and a burst signal 7. The video signal 2 is composed of a luminance signal and a chrominance signal, and forms a video. The horizontal synchronization pulse 3 is used to synchronize the video signal 2 with the screen in the horizontal direction. The equalizing pulse 4 is provided between the horizontal synchronizing pulse 3 and the vertical synchronizing pulse 6 so that the vertical synchronizing pulse 6 can be taken out stably. Vertical sync pulse 6
Is used to synchronize the video signal 2 with the vertical direction of the screen.

As shown in FIG. 6A, a white level Lw, a black level Lb, and a sync tip level Ls are set in the composite video signal 1. The white level Lw indicates a white level of the video signal. The black level Lb indicates the black level of the video signal. The video signal 2 is composed of a luminance signal and a chrominance signal. The horizontal synchronization pulse 3, the equalization pulses 4, 5 and the vertical synchronization pulse 6 are separated from the composite video signal 1 by a synchronization separation circuit. The sync separation circuit has a sync chip level L
s and a reference voltage Vsepa smaller than the black level Lb.
Is separated from the composite video signal 1.

FIG. 7 is a block diagram showing an example of a conventional sync separation circuit. At this time, the synchronization separation circuit 8 includes a resistor R
1, a capacitor C1 and an IC 9 for synchronizing separation. One end of the capacitor C1 is supplied with the composite video signal, and the other end is connected to the input terminal Tin of the sync separation IC 12. The resistor R1 is connected between one end of the capacitor C1 and ground.

The IC 9 for synchronizing and separating includes a charging circuit 10, an amplifier circuit 11, a reference power supply 12, and a comparison circuit 13. The charging circuit 10 includes a transistor Q1 and a reference power source 1
4 The transistor Q1 has a base connected to the reference power supply 14, a collector applied with the power supply voltage Vcc, and an emitter connected to the input terminal Tin. Reference power supply 1
4 applies a bias voltage Vbias to the base of transistor Q1.

The transistor Q1 has a bias potential of Vbi
as, the base-emitter voltage of transistor Q1 is VBE
When the emitter potential falls below (Vbias-VBE), the transistor is turned on to charge the capacitor C1. The potential of the input terminal Tin becomes (Vbias-VBE) or less during the period of the horizontal synchronization pulse 3, the equalization pulses 4, 5, the vertical synchronization pulse 6, and the burst signal 7 shown in FIGS. When the potential of the input terminal Tin becomes equal to or less than (Vbias-VBE), the horizontal synchronization pulse 3, the equalization pulses 4, 5, the vertical synchronization pulse 6,
During the period of the burst signal 7, the transistor Q1 turns on,
The capacitor C1 is charged, and the composite video signal is converted to (Vbias-V
BE).

[0007] The amplifier circuit 11 is connected to the input terminal Tin and amplifies and outputs the composite video signal. Reference power supply 12
Applies a reference voltage to the non-inverting input terminal of the comparison circuit 13. The comparison circuit 13 has an inverting input terminal connected to the input terminal Tin. The comparison circuit 13 outputs the composite video signal to the reference power source 1.
A signal is output at a low level when the reference voltage is higher than the reference voltage, and at a high level when it is lower than the reference voltage. This output becomes a synchronization signal.

At this time, the horizontal synchronizing pulse 3 is
As shown in (A), the pulse width is set to th0, and the duty ratio is set to (th0 / th1). As shown in FIG. 6B, the pulse width of the vertical synchronization pulse 6 is set to the period tv1 and the duty ratio is set to (th0 / th1). As described above, the duty ratios of the horizontal synchronization pulse 3 and the vertical synchronization pulse 6 are different.

In the sync separation circuit 8 shown in FIG. 7, when the discharge amount of the capacitor C1 due to the discharge current I2 is large, the duty ratio of charge and discharge differs between the period of the vertical synchronization pulse 6 and the period of the horizontal synchronization pulse 3. The base-emitter voltage VBE of the transistor Q1 changes. If the thermal voltage is VT, the emitter current is IE, and the saturation current is Is, the base-emitter voltage VBE of the transistor can be expressed as VBE = VT · ln (IE / Is). The base-emitter voltage VBE of Q1 will change.

When the base-emitter voltage VBE of the transistor Q1 changes, a sag occurs. When the sag is raised above Vsepa, the synchronization pulse cannot be detected. For this reason, there has been proposed a synchronization separation circuit that prevents the occurrence of sag. FIG. 8 shows a block diagram of another example of the related art. In the figure, the same components as those in FIG.
The description is omitted.

The synchronization separation circuit 20 includes a synchronization separation circuit IC2
1 differs from the sync separation circuit 10 of FIG. The charging circuit 22 includes a transistor Q2
, Q3, Q4, resistor R2, current source 23, reference power source 14
Consists of The charging circuit 22 forms a feedback circuit, and includes a base-emitter voltage VBE of the transistor Q1.
Does not occur. For this reason, generation of sag can be suppressed.

However, the sync separation circuit 1 shown in FIGS.
0 and 20, the composite video signal has fluttering as shown in FIG. 9, and the lowest point of the synchronization pulse is (Vbias-VBE).
For example, when it becomes larger, the synchronization pulse cannot be detected. The relationship between the voltage rise amount Verr of the synchronization pulse and the convergence time t can be expressed by Verr = (∫I2 dt) / C1.

That is, if the current I2 is increased in order to reduce the sag, fluttering increases,
If the current I2 is reduced in order to reduce fluttering, the sag increases. Thus, sag and flutter are in a reciprocal relationship. A sync separation circuit that prevents sag and flutter has been proposed. FIG. 10 shows a block diagram of another example of the related art. 7, the same components as those of FIG. 7 are denoted by the same reference numerals, and the description thereof will be omitted.

The synchronization separation circuit 30 includes a synchronization separation IC 31
The configuration of the charging circuit 32 incorporated in the sync separation circuit 20 of FIG. The charging circuit 32 includes a transistor Q2,
It comprises Q3, Q4, Q5, Q6, current sources 22, 33, switches 34, 35, and a reference power source 14. Current source 33
Is connected to the input terminal Tin and draws current from the input terminal Tin. The switch 34 is connected between the transistors Q2 and Q3 and the current source 22, and is switched according to a timing signal supplied from a control terminal Tc. The switch 34 is connected between the input terminal Tin and the current source 33, and is switched according to a timing signal supplied from the control terminal Tc.

The timing signal supplied to the control terminal Tc turns on the switches 34 and 35 at the timing of the synchronizing pulse, and turns off during other periods. The timing signal is
It is supplied from the timing generation circuit 36.

[0016]

However, in the conventional synchronous separation circuits 10 and 20, when the sag is reduced,
When fluttering becomes large and fluttering is made small, there is a problem that sag becomes large.
Also, in order to reduce both the sag and the flutter, FIG.
When a circuit as shown in FIG. 1 is configured, a timing generation circuit 36 for generating a pulse for separating the synchronization pulse is required separately to separate the synchronization pulse, which is expensive. In addition, a terminal for connecting the timing generation circuit 36 to the sync separation IC 31 is required.
There were problems such as hindering downsizing of C31.

The present invention has been made in view of the above points, and an object of the present invention is to provide a sync separation circuit capable of reliably separating sync pulses with a simple configuration.

[0018]

According to the first aspect of the present invention, a first clamping means (10, 10) for clamping a composite video signal is provided.
14) and a second clamp means which is set to have a different response speed from the first clamp means (10, 14) and clamps the composite video signal clamped by the first clamp means (10, 14). (42; 52).

The second clamping means (10, 10)
14) is configured to supply a charging current to the first capacitor (C1) during the synchronizing signal period of the composite video signal. Claim 3 provides that the second clamping means (42) is
A differential amplifier circuit (43) for outputting a difference voltage between the composite video signal clamped to a predetermined level by the clamping means (10, 14) and the charging voltage charged in the second capacitor (C2); A predetermined current is discharged from the current amplifier circuit (44) for supplying a current corresponding to the difference between the output of the dynamic amplifier circuit (43) and the clamp level to the second capacitor (C2), and the second capacitor (C2). Discharging means (46) for causing
It consists of:

[0020] The fourth clamping means (52).
Is supplied with a current source (54) for drawing a current corresponding to the charging voltage charged in the second capacitor (C2), and a composite video signal one end of which is clamped by the first clamping means (10, 14). A resistor (53) having the other end connected to the current source (54); and a current corresponding to a difference between a voltage at a connection point between the resistor (53) and the current source (46) and a predetermined voltage. It comprises a current amplifying circuit (44) for outputting and discharging means (46) for discharging the second capacitor (C2).

The fifth clamping means (4)
2; 52) is compared with the synchronization detection level to detect and separate the synchronization signal. According to the present invention, sag can be prevented by the first clamp means and output as a video signal, fluttering can be prevented by the second clamp means, and the synchronization signal can be reliably detected. For this reason, the video signal can be output without distortion, and the synchronization signal can be reliably detected.

It should be noted that the reference numerals in the parentheses are provided for easy understanding of the present invention, are merely examples, and are not limited to the illustrated embodiment.

[0023]

FIG. 1 is a block diagram showing a first embodiment of the present invention. 6, the same components as those of FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted. The sync separation circuit 40 of the present embodiment is different from the sync separation IC 41 in the configuration.
The synchronization separation IC 41 includes a charging circuit 10, an amplification circuit 11,
In addition to the reference power supply 12 and the comparison circuit 13, a clamp circuit 42 as second clamp means is provided.

The clamp circuit 42 includes a differential amplifier 43, a conductance amplifier 44, a reference power supply 45, and a constant current source 46.
Consists of The differential amplifier 43 has a non-inverting input terminal connected to the video input terminal Tin, and an inverting input terminal connected to the clamping capacitor connection terminal T11. Differential amplifier 4
Reference numeral 3 outputs a differential voltage between the signal on the input terminal Tin and the voltage of the capacitor C2. The output of the differential amplifier 43 is connected to the inverting input terminal of the comparison circuit 13 and the conductance amplifier 44.
Is supplied to the non-inverting input terminal of.

A reference voltage is applied from a reference power supply 45 to a non-inverting input terminal of the conductance amplifier 44. The conductance amplifier 44 outputs a current according to the difference between the output of the differential amplifier 43 and the reference voltage. The output of the comparator 13 is connected to the conductance amplifier 44.
The conductance amplifier 44 is driven when the output of the comparator 13 is at a high level, and stops operating when the output of the comparator 13 is at a low level.

The output current of the conductance amplifier 44 is
It is supplied to the clamping capacitor connection terminal T11. An externally connected capacitor C2 is connected to the clamping capacitor connection terminal T11, and a constant current source 46 is connected to the inside, and an inverting input terminal of the differential amplifier 43 is connected to the inside. The constant current source 46 draws a constant current I4 from the capacitor C2. The capacitor C2 is a conductance amplifier 4
4 and discharged by the constant current source 46.

When the potential of the input terminal Tin reaches the sync tip level, the output of the differential amplifier 43 drops to the sync tip level. When the output of the differential amplifier 43 falls to the sync chip level, the output of the comparator 13 goes to high level. When the output of the comparator 13 becomes high level, the conductance amplifier 44 operates. Conductance amplifier 4
4 charges the capacitor C2 so that the output of the differential amplifier 43 becomes the bias voltage Vbias2. The above operation clamps the output of the differential amplifier 43 to the bias voltage Vbias2.

When a signal Verr having fluttering is supplied to the input terminal Tin, it can be expressed as: Verr = (∫I4 dt) / C2. FIG. 2 shows an operation waveform diagram of one embodiment of the present invention. 2A shows a waveform at the input terminal Tin, and FIG. 2B shows a waveform at the inverting input terminal of the comparator 13.

As shown in FIG. 2A, even if there is fluttering in the composite video signal input to the input terminal Tin, the sync pulse is clamped to the bias voltage Vbias2, so that the comparator 13 reliably uses the voltage Vsepa. Can detect the synchronization pulse. According to the present embodiment, since the response is improved by forcibly discharging the capacitor C2 by means other than the synchronization pulse, the synchronization pulse can be reliably separated.

FIG. 3 is a block diagram of another embodiment of the present invention.
FIG. 4 is a circuit diagram showing another embodiment of the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The sync separation circuit 50 of the present embodiment is different from that of FIG. Synchronous separation IC
The clamp circuit 52 of the first embodiment has a conductance amplifier 4
4, reference power supply 45, constant current source 46, level shift resistor 5
3. It is composed of a variable current source 54.

The level shift resistor 54 has one end connected to the output of the amplifier circuit 11 and the other end connected to the inverting input terminal of the comparator 13. The variable current source 54 is connected between the connection point between the level shift resistor 54 and the inverting input terminal of the comparator 13 and the ground. The variable current source 54 is connected to the clamping capacitor connection terminal T11, and draws a current i according to the charging voltage of the capacitor C2 from the level shift resistor 54.

The conductance amplifier 44 is connected to the comparator 13
By controlling the charging current of the capacitor C2 in accordance with the inverting input terminal of the comparator 13, the voltage of the inverting input terminal of the comparator 13 is changed to the bias voltage Vbi
Control to be as2. An effect similar to that of the above-described embodiment can be obtained.

[0033]

As described above, according to the present invention, sag is suppressed by the first clamp means, output as a video signal, fluttering is prevented by the second clamp means, and the synchronization signal is reliably detected. it can. For this reason, it is possible to output a video signal without distortion and to reliably detect a synchronization signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of one embodiment of the present invention.

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of another embodiment of the present invention.

FIG. 5 is a waveform diagram of a composite video signal.

FIG. 6 is a waveform diagram of a main part of the composite video signal.

FIG. 7 is a block diagram of a conventional example.

FIG. 8 is a block diagram of another example of the related art.

FIG. 9 is a diagram showing a state where fluttering is present in a composite video signal.

FIG. 10 is a block diagram of another example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Charge circuit 11 Amplification circuit 12, 14, 45 Reference power supply 13 Comparator 40, 50 Synchronization separation circuit 41, 51 For synchronization separation 42, 52 Clamp circuit 43 Differential amplifier 44 Conductance amplifier 46 Constant current source 53 Level shift resistance 54 Variable Current source

Claims (5)

[Claims] 1. A synchronizing separation circuit for separating a synchronizing signal from a composite video signal, wherein: a first clamping means for clamping the composite video signal; and a response speed different from that of the first clamping means, A second clamping unit for clamping the composite video signal clamped by the first clamping unit. 2. The synchronization separation circuit according to claim 1, wherein said first clamping means supplies a charging current to a first capacitor during a synchronization signal period of said composite video signal. 3. A differential circuit for outputting a differential voltage between a composite video signal clamped to a predetermined level by the first clamp unit and a charged voltage charged in a second capacitor. An amplifier circuit; a current amplifier circuit that supplies a current corresponding to a difference between an output of the differential amplifier circuit and a clamp level to the second capacitor; and a discharging unit that discharges a predetermined current from the second capacitor. 3. The synchronization separation circuit according to claim 1, further comprising: 4. The second clamp means supplies a current source for drawing a current corresponding to a charging voltage charged in a second capacitor, and a composite video signal one end of which is clamped by the first clamp means. A resistor having the other end connected to the current source, a current amplifier circuit that outputs a current corresponding to a difference between a voltage at the connection point between the resistor and the current source and a predetermined voltage, 3. The synchronization separating circuit according to claim 1, further comprising: discharging means for discharging the two capacitors. 5. The synchronization separation device according to claim 1, further comprising a comparison circuit for comparing an output of said second clamp means with a synchronization detection level and detecting a synchronization signal. circuit.